Semiconductor wafer inspection apparatus

- Tokyo Electron Limited
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Description

FIG. 1 is a front elevational view of a semiconductor wafer inspection apparatus, showing my new design;

FIG. 2 is a bottom view thereof;

FIG. 3 is a right side elevational view thereof;

FIG. 4 is a left side elevational view thereof;

FIG. 5 is a top view thereof;

FIG. 6 is a rear elevational view thereof; and,

FIG. 7 is a perspective view thereof.

The broken line showing in each of the figures is for illustrative purposes only and forms no part of the claimed design.

Claims

The ornamental design for a semiconductor wafer inspection apparatus, as shown and described.

Referenced Cited
U.S. Patent Documents
5465145 November 7, 1995 Nakashige et al.
6906794 June 14, 2005 Tsuji
20050062960 March 24, 2005 Tsuji et al.
20080246497 October 9, 2008 Furukawa et al.
Patent History
Patent number: D612879
Type: Grant
Filed: Apr 4, 2006
Date of Patent: Mar 30, 2010
Assignee: Tokyo Electron Limited (Tokyo)
Inventor: Munetoshi Nagasaka (Nirasaki)
Primary Examiner: Sandra Snapp
Assistant Examiner: Patricia Palasik
Attorney: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
Application Number: 29/257,350
Classifications
Current U.S. Class: Miscellaneous (D15/199)