Differential charge pump circuit with high differential and low common mode impedance
A high gain, low voltage differential amplifier exhibiting extremely low common mode sensitivities includes a load element exhibiting a high differential resistance, but a low common mode resistance. The load element contains a positive differential load resistance and a negative differential load resistance, which offsets the positive differential load resistance. The output common mode level of the differential amplifier is one p-channel source to gate voltage drop below the power supply voltage prohibiting the common mode output voltage from drifting far from an active level. The differential amplifier also has application for use in a differential charge pump circuit. The high differential impedance of the differential amplifier allows the attainment of extremely small leakage, while a low common-mode impedance results in simplified biasing.
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Claims
2. The differential charge pump circuit of claim 1, wherein said first and second transistors comprise n-channel MOSFETs, and said current sourcing transistors comprise p-channel MOSFETs so as to provide an output common mode level at said output terminal being a p-channel MOSFET source to gate voltage below a voltage of said power supply.
6. The CMOS differential charge pump circuit of claim 5, wherein said positive differential load resistance comprising said third and fourth p-channel MOSFETs possesses a high resistance such that any imperfections in said first and second p-channel MOSFETs results in a proportionally small effect.
9. The differential charge pump circuit of claim 8, wherein said first and second transistors comprise n-channel MOSFET transistors, and said plurality of current sourcing transistors comprise p-channel MOSFET transistors so as to provide an output common mode level at said output terminal being a p-channel MOSFET source to gate voltage below a voltage of said power supply.
10. The differential charge pump circuit of claim 8, wherein said third and fourth current sourcing transistors comprise a high resistance so that any imperfection in said first and second current sourcing transistors in cancellation results in a proportionately negligible effect.
11. The differential charge pump circuit of claim 7 wherein at least one capacitor comprise a single capacitor coupled across said first terminal of said first transistor and said first terminal of said second transistor.
12. The differential charge pump circuit of claim 7 wherein at least one capacitor comprise two capacitors, a first capacitor being coupled from said first terminal of said first transistor to ground, and a second capacitor being coupled from said first terminal of said second transistor to ground.
14. A differential charge pump circuit comprising:
- first and second transistors each comprising a first terminal for receiving current, a second terminal, and a third terminal for controlling the amount of biasing current flowing from said first terminal to said second terminal, said third terminal on said first and second transistor receiving control signals comprising large input swings sufficient to switch all said biasing current in either said first transistor or said second transistor;
- a load element comprising:
- a positive differential load resistance coupling power to said first terminal of said first transistor and to said first terminal of said second transistor; and
- a negative differential load resistance coupling power to said first terminal of said second transistor and to said first terminal of said first transistor, said negative differential load resistance comprising an absolute value being substantially equal to a value of said positive differential resistance; and
- a least one capacitor for generating a capacitance across said first terminal of said first transistor and said first terminal of said second transistor, wherein said load element exhibits high differential impedance to prohibit leakage of the at least one capacitor, said control signals controlling said third terminals of said first and second transistors so as to switch a portion of said biasing current, in both directions, from said load element across said capacitance..Iaddend..Iadd.
15. A method for generating charge across a capacitor in accordance with control signals, said method comprising the steps of:
- providing first and second transistors each comprising a first terminal for receiving a biasing current, a second terminal for dispensing said biasing current, and a third terminal for controlling the amount of biasing current flowing from said first terminal to said second terminal;
- inputting, on said third terminal of said first and second transistors, said control signals comprising large input swings sufficient to switch all of said biasing current in either said first transistor or said second transistor;
- providing a positive differential load resistance;
- coupling power from said positive differential load resistance to said first terminal of said first transistor and to said first terminal of said second transistor;
- providing a negative differential load resistance comprising an absolute value being substantially equal to a value of said positive differential resistance;
- coupling power from said negative differential load resistance to said first terminal of said second transistor and to said first terminal of said first transistor; and
- generating a capacitance across said first terminal of said first transistor and said first terminal of said second transistor, wherein said load element exhibits high differential impedance to prohibit leakage of the at least one capacitor, said control signals controlling said third terminals of said first and second transistors so as to switch substantially half of all of said biasing current, in both directions, from said load element across said capacitance..Iaddend.
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Type: Grant
Filed: Jun 6, 1997
Date of Patent: Dec 29, 1998
Assignee: Rambus, Inc. (Mountain View, CA)
Inventor: Thomas H. Lee (Cupertino, CA)
Primary Examiner: James B. Mullins
Law Firm: Blakely, Sokoloff, Taylor & Zafman LLP
Application Number: 8/870,638
International Classification: H03K 1756; H03F 345;