Differential charge pump circuit with high differential and low common mode impedance

- Rambus, Inc.

A high gain, low voltage differential amplifier exhibiting extremely low common mode sensitivities includes a load element exhibiting a high differential resistance, but a low common mode resistance. The load element contains a positive differential load resistance and a negative differential load resistance, which offsets the positive differential load resistance. The output common mode level of the differential amplifier is one p-channel source to gate voltage drop below the power supply voltage prohibiting the common mode output voltage from drifting far from an active level. The differential amplifier also has application for use in a differential charge pump circuit. The high differential impedance of the differential amplifier allows the attainment of extremely small leakage, while a low common-mode impedance results in simplified biasing.

Skip to:  ·  Claims  ·  References Cited  · Patent History  ·  Patent History

Claims

2. The differential charge pump circuit of claim 1, wherein said first and second transistors comprise n-channel MOSFETs, and said current sourcing transistors comprise p-channel MOSFETs so as to provide an output common mode level at said output terminal being a p-channel MOSFET source to gate voltage below a voltage of said power supply.

6. The CMOS differential charge pump circuit of claim 5, wherein said positive differential load resistance comprising said third and fourth p-channel MOSFETs possesses a high resistance such that any imperfections in said first and second p-channel MOSFETs results in a proportionally small effect.

9. The differential charge pump circuit of claim 8, wherein said first and second transistors comprise n-channel MOSFET transistors, and said plurality of current sourcing transistors comprise p-channel MOSFET transistors so as to provide an output common mode level at said output terminal being a p-channel MOSFET source to gate voltage below a voltage of said power supply.

10. The differential charge pump circuit of claim 8, wherein said third and fourth current sourcing transistors comprise a high resistance so that any imperfection in said first and second current sourcing transistors in cancellation results in a proportionately negligible effect.

11. The differential charge pump circuit of claim 7 wherein at least one capacitor comprise a single capacitor coupled across said first terminal of said first transistor and said first terminal of said second transistor.

12. The differential charge pump circuit of claim 7 wherein at least one capacitor comprise two capacitors, a first capacitor being coupled from said first terminal of said first transistor to ground, and a second capacitor being coupled from said first terminal of said second transistor to ground.

14. A differential charge pump circuit comprising:

first and second transistors each comprising a first terminal for receiving current, a second terminal, and a third terminal for controlling the amount of biasing current flowing from said first terminal to said second terminal, said third terminal on said first and second transistor receiving control signals comprising large input swings sufficient to switch all said biasing current in either said first transistor or said second transistor;
a load element comprising:
a positive differential load resistance coupling power to said first terminal of said first transistor and to said first terminal of said second transistor; and
a negative differential load resistance coupling power to said first terminal of said second transistor and to said first terminal of said first transistor, said negative differential load resistance comprising an absolute value being substantially equal to a value of said positive differential resistance; and
a least one capacitor for generating a capacitance across said first terminal of said first transistor and said first terminal of said second transistor, wherein said load element exhibits high differential impedance to prohibit leakage of the at least one capacitor, said control signals controlling said third terminals of said first and second transistors so as to switch a portion of said biasing current, in both directions, from said load element across said capacitance..Iaddend..Iadd.

15. A method for generating charge across a capacitor in accordance with control signals, said method comprising the steps of:

providing first and second transistors each comprising a first terminal for receiving a biasing current, a second terminal for dispensing said biasing current, and a third terminal for controlling the amount of biasing current flowing from said first terminal to said second terminal;
inputting, on said third terminal of said first and second transistors, said control signals comprising large input swings sufficient to switch all of said biasing current in either said first transistor or said second transistor;
providing a positive differential load resistance;
coupling power from said positive differential load resistance to said first terminal of said first transistor and to said first terminal of said second transistor;
providing a negative differential load resistance comprising an absolute value being substantially equal to a value of said positive differential resistance;
coupling power from said negative differential load resistance to said first terminal of said second transistor and to said first terminal of said first transistor; and
generating a capacitance across said first terminal of said first transistor and said first terminal of said second transistor, wherein said load element exhibits high differential impedance to prohibit leakage of the at least one capacitor, said control signals controlling said third terminals of said first and second transistors so as to switch substantially half of all of said biasing current, in both directions, from said load element across said capacitance..Iaddend.
Referenced Cited
U.S. Patent Documents
3771063 November 1973 Barrett
4156851 May 29, 1979 Winters
4178554 December 11, 1979 Sase et al.
4285006 August 18, 1981 Kurahashi et al.
4291274 September 22, 1981 Suzuki et al.
4364082 December 14, 1982 Tonomura et al.
4479202 October 23, 1984 Uchida
4506175 March 19, 1985 Reitmeier et al.
4520321 May 28, 1985 Nakatsugawa et al.
4623805 November 18, 1986 Flora et al.
4635097 January 6, 1987 Tatami
4721904 January 26, 1988 Ozaki et al.
4751469 June 14, 1988 Nakagawa et al.
4868512 September 19, 1989 Bridgman
4870303 September 26, 1989 McGinn
4893094 January 9, 1990 Herold et al.
4904948 February 27, 1990 Asami
4929916 May 29, 1990 Fukuda
4963817 October 16, 1990 Kohiyama et al.
5095233 March 10, 1992 Ashby et al.
5121010 June 9, 1992 Hoshizaki et al.
5128554 July 7, 1992 Hoshizaki
5148113 September 15, 1992 Wight et al.
5164838 November 17, 1992 Okuda
5179303 January 12, 1993 Searles et al.
5187448 February 16, 1993 Brooks et al.
5220294 June 15, 1993 Ichikawa
5223755 June 29, 1993 Richley
5248946 September 28, 1993 Murakami et al.
5253042 October 12, 1993 Yasuda
5253187 October 12, 1993 Kaneko et al.
5309162 May 3, 1994 Uematsu et al.
5362995 November 8, 1994 Kubo
5394024 February 28, 1995 Buckenmaier et al.
5422918 June 6, 1995 Vartti et al.
5432480 July 11, 1995 Popescu
5440274 August 8, 1995 Bayer
Foreign Patent Documents
0 490 690 A1 June 1992 EPX
0 521 215 A1 January 1993 EPX
Other references
  • Patent Abstracts of Japan, vol. 4, No. 67 (E-11) (549) May 20, 1980 & Japan Application, 55 035 516 (Tokyo Shibaura Denki K.K.) Mar. 12, 1980.
Patent History
Patent number: RE36013
Type: Grant
Filed: Jun 6, 1997
Date of Patent: Dec 29, 1998
Assignee: Rambus, Inc. (Mountain View, CA)
Inventor: Thomas H. Lee (Cupertino, CA)
Primary Examiner: James B. Mullins
Law Firm: Blakely, Sokoloff, Taylor & Zafman LLP
Application Number: 8/870,638