Data processor with bus-sizing function

A data processor capable of controlling memory accessing by the same controls regardless of the bus width to be used. A register is provided for storing data to be inputted and completing a block of data with a size equal to that of the whole bus width of the external data bus when the microprocessor accesses external memory by using only a part of the bus width of an external data bus according to a bus-sizing function. A bus interface is provided for starting memory access by dividing a bus cycle into plural portions according to the bus width and for controlling operation so as to access data equal in size to the case where the whole bus width of the external data bus is used for accessing.

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Claims

1. A data processor comprising a microprocessor, an external data bus having a variable n-byte width, wherein n is an even integer and an external memory which is connected with said microprocessor through said external data bus and whose memory area is composed of a plurality of memory boundaries defined by n-bytes as one unit, wherein said microprocessor is provided with:

bus-size switching means for switching between a first case of using said external data bus in n-bytes width and a second case of using said external data bus in n/2 byte width when accessing said external memory;
accessing means for, in said first case, successively accessing m memory boundaries, wherein m is an even integer, including a memory boundary where an address to be accessed exists by wrapping around from said memory boundary where an address to be accessed exists, and in said second case, successively accessing m/2 memory boundaries including a memory boundary where an address to be accessed exists by wrapping around from said memory boundary where an address to be accessed exists;
address generating means for generating a head address of said memory boundary of n-byte units, said n-byte units including said address to be accessed; and
a bus interface circuit for accessing successively the inside of said memory area in an order from the head address of addresses generated by said address generating means.

2. A data processor as set forth in claim 1, wherein said microprocessor is further provided with:

an internal data bus having n-byte width and to which data is inputted from said external data bus, and
a register having n-byte width which connects said external data bus with said internal data bus, and said bus interface circuit,
when said external memory is successively accessed by using the entire n-byte bus width of said external data bus, outputs data of n-bytes on said external data bus directly to said internal data bus at every access, in the absence of using said register and
when said external memory is successively accessed by using n/2 byte bus width of said external data bus, stores data of n/2 bytes from said external data bus into said register at every time of accessing, and outputs data of n/2 bytes stored in said register to bit positions corresponding to said internal data bus and outputs data of n-bytes on said internal data bus by outputting data of n/2 bytes to bit positions corresponding to said internal data bus from said external data bus at every even numbered access.

3. The data processor of claim 1 where n=8 and m=4.

4. A data processor comprising a microprocessor, an external data bus having a bus width, and an external memory which is connected with said microprocessor, wherein

said microprocessor is provided with:
bus-sizing means for switching between a state of using a part of the bus width of said external data bus and a state of using all of said bus width for accessing said external memory;
accessing means for accessing said external memory successively by executing a predetermined number of external bus accesses as a set, and
a bus interface circuit for, receiving a request for an access start and starting an external bus access to said external memory; and
wherein said bus interface circuit, in response to a single request for an access start
when all of said bus width of said external data bus is used, generates a single set of successive external bus accesses, and
when a part of the bus width of the external data bus is used, generates a plurality of sets of successive external bus accesses, starts each set of successive external bus accessing by generating addresses for the first external bus access of each set of successive external bus accesses, and accesses successively a memory area of the same size as in the case where all of said bus width of said external data bus is used.

5. A method for accessing memory in a data processor, said data processor having a microprocessor, means for storing a block of data, an external data bus having an effective bus width selectable between n-bytes and n/2 bytes, wherein n is an even integer and an external memory which is connected to said microprocessor through said external data bus, said external memory having a plurality of addressable memory locations each having a width of n-bytes, the method comprising the steps of:

selecting whether said effective bus width of said external data bus is to be n-bytes or n/2 bytes;
generating, in said microprocessor, an access request to access a specific addressable memory location in said external memory;
generating, in an address generating circuit, a head address of a block of data to be accessed, wherein said head address is generated based on said specific addressable memory location;
accessing said external memory, wherein said accessing is accomplished in a series of accesses sufficient to retrieve a block of data;
generating a bus transfer finishing signal upon completion of each of said series of accesses;
transferring said block of data through an internal data bus, said internal data bus having a bus width equal to n-bytes;
storing said block of data, wherein said storing is accomplished in a certain order if said external bus width is n-bytes, and is accomplished in the same order if said external bus width is n/2 bytes;
transferring said block of data to said means for storing.

9. The method of claim 5 wherein said means for storing is a cache.

10. The method of claim 5 wherein said step of transferring said block of data through an internal data bus further comprises the step of transferring said block of data to an alignment register.

11. A method, for accessing memory in a data processor, said data processor having a microprocessor, means for storing a block of data, an external data bus having an effective bus width selectable between n-bytes and n/2 bytes, wherein said n is 8 and wherein said block of data is 256 bits wide said data processor having an external memory which is connected to said microprocessor through said external data bus, said external memory having a plurality of addressable memory locations each having a width of n-bytes, the method comprising the steps of:

selecting whether said effective bus width of said external data bus is to be n-bytes of n/2 bytes;
generating, in said microprocessor, an access request to access a specific addressable memory location in said external memory;
generating, in an address generating circuit, a head address of a block of data to be accessed, wherein said head address is generated based on said specific addressable memory location;
accessing said external memory, wherein said accessing is accomplished in a series of accesses sufficient to retrieve a block of data;
generating a bus transfer finishing signal upon completion of each or said series of accesses;
transferring said block of data through an internal data bus, said internal data bus having a bus width equal to n-bytes;
storing said block of data, wherein said storing is accomplished in a certain order if said external bus width is n-bytes, and is accomplished in the same order if said external bus width is n/2 bytes;
transferring said block of data to said means for storing.

12. The method of claim 11 wherein said means for storing is a cache.

13. The method of claim 11 wherein said step of transferring said block of data through an internal data bus further comprises the step of transferring said block of data to an alignment register..Iadd.

14. A data processor comprising a microprocessor, an external data bus having a variable n-byte width, wherein n is an even integer, and an external memory which is connected to said microprocessor through said external data bus and whose memory area is composed of a plurality of memory boundaries defined by at least one addressable memory location as one unit, wherein said data processor is provided with;

bus-size switching means for switching between a first case of using said external data bus in n-bytes width and a second case of using said external bus in n/2 byte width when accessing said external memory;
accessing means for, in said first case, successively accessing a plurality of memory boundaries, including a memory boundary where an address to be accessed exists by wrapping around from said memory boundary where an address to be accessed exists, and successively providing n-byte units derived therefrom to said external bus, and in said second case, successively accessing a plurality of memory boundaries including a memory boundary where an address to be accessed exists by wrapping around from said memory boundary where an address to be accessed exists, and successively providing n/2-byte units derived therefrom to said external bus;
address generating means for generating a head address of said memory boundary where said address to be accessed exists; and
a bus interface circuit for accessing successively the inside of said memory area in an order from the head address of addresses generated by said address generating means..Iaddend..Iadd.15. A data processor comprising a microprocessor, an external data bus having a variable n-byte width, wherein n is an even integer and an external memory which is connected to said microprocessor through said external data bus and whose memory area is composed of a plurality of memory boundaries defined by at least one addressable memory location as one unit, wherein said data processor is provided with;
bus-size switching circuitry for switching between a first case of using said external data bus in n-bytes width and a second case of using said external bus in n/2 byte width when accessing said external memory;
accessing circuitry for, in said first case, successively accessing a plurality of memory boundaries, including a memory boundary where an address to be accessed exists by wrapping around from said memory boundary where an address to be accessed exists, and successively providing n-byte units derived therefrom to said external bus, and in said second case, successively accessing a plurality of memory boundaries including a memory boundary where an address to be accessed exists by wrapping around from said memory boundary where an address to be accessed exists, and successively providing n/2-byte units derived therefrom to said external bus;
address generating circuitry for generating a head address of said memory boundary where said address to be accessed exists; and
a bus interface circuit for accessing successively the inside of said memory area in an order from the head address of addresses generated by

said address generating means..Iaddend..Iadd.16. A data processor comprising a microprocessor, an external data bus having a variable n-byte width, wherein n is an even integer and an external memory which is connected to said microprocessor through said external data bus and whose memory area is composed of a plurality of n-byte memory boundaries defined by n-bytes as one unit, each of said n-byte units having an upper half and a lower half, wherein said data processor is provided with;

bus-size switching means for switching between a first case of using said external data bus in n-bytes width and a second case of using said external bus in n/2 byte width when accessing said external memory;
accessing means for, in said first case, successively accessing a plurality of memory boundaries, including a memory boundary where an address to be accessed exists, by wrapping around from said memory boundary where an address to be accessed exists, and successively providing n-byte units derived therefrom to said external bus, and in said second case, successively accessing a plurality of memory boundaries, including a memory boundary where an address to be accessed exists, by wrapping around from said memory boundary where an address to be accessed exists, and successively providing n/2-byte units derived therefrom to said external bus;
address generating means for generating a head address of said memory boundary where said address to be accessed exists, which head address is on an n-byte memory boundary, both in the case in which the address to be accessed is within the upper half of the n-byte unit beginning at said memory boundary, and the case in which the address to be accessed is within the lower half of said n-byte unit; and
a bus interface circuit for accessing successively the inside of said memory area in an order from the head address of addresses generated by said address generating means..Iaddend..Iadd.17. A data processor comprising a microprocessor, an external data bus having a variable n-byte width, wherein n is an even integer, and an external memory which is connected to said microprocessor through said external data bus and whose memory area is composed of a plurality of n-byte memory boundaries defined by n-bytes as one unit, each of said n-byte units having an upper half and a lower half, wherein said data processor is provided with:
bus-size switching circuitry for switching between a first case of using said external data bus in n-bytes width and a second case of using said external bus in n/2 byte width when accessing said external memory;
accessing circuitry for, in said first case, successively accessing a plurality of memory boundaries, including a memory boundary where an address to be accessed exists, by wrapping around from said memory boundary where an address to be accessed exists, and successively providing n-byte units derived therefrom to said external bus, and in said second case, successively accessing a plurality of memory boundaries, including a memory boundary where an address to be accessed exists, by wrapping around from said memory boundary where an address to be accessed exists, and successively providing n/2-byte units derived therefrom to said external bus;
address generating circuitry for generating a head address of said memory boundary where said address to be accessed exists, which head address is on an n-byte memory boundary, both in the case in which the address to be accessed is within the upper half of the n-byte unit beginning at said memory boundary, and the case in which the address to be accessed is within the lower half of said n-byte unit; and
a bus interface circuit for accessing successively the inside of said memory area in an order from the head address of addresses generated by said address generating circuitry..Iaddend..Iadd.18. A data processor comprising a microprocessor, an external data bus having a variable n-byte width, wherein n is an even integer, and an external memory which is connected to said microprocessor through said external data bus and whose memory area is composed of a plurality of memory boundaries defined by n-bytes as one unit, each of said n-byte units having an upper half and a lower half, wherein said data processor is provided with:
bus-size switching circuitry for switching between first case of using said external data bus in n-bytes width and a second case of using said external bus in n/2 byte width when accessing said external memory;
accessing circuitry for, in said first case, successively accessing a plurality of memory boundaries, including a memory boundary where an address to be accessed exists, by wrapping around from said memory boundary where an address to be accessed exits, and successively providing n-byte units derived therefrom to said external bus, and in said second case, successively accessing a plurality of memory boundaries, including a memory boundary where an address to be accessed exists, by wrapping around from said memory boundary where an address to be accessed exists, and successively providing n/2-byte units derived therefrom to said external bus;
address generating circuitry for generating a head address of said memory boundary where said address to be accessed exists; and
a bus interface circuit for (1) accessing successively the inside of said memory area in an order from the head address of addresses generated by said address generating circuitry, and (2) in each of said first and second cases, accomplishing said accessing in an order which does not vary depending on whether said address to be accessed is within the upper half of an n-byte unit beginning at the memory boundary where said address to be accessed exists, or the lower half of said n-byte unit..Iaddend..Iadd.19. A data processing apparatus comprising:
a processor;
a data bus having a bus width;
a first memory for storing blocks of data which is coupled to or within said processor;
a second memory which is coupled to said processor through said bus, said second memory having a plurality of addressable memory locations which are capable of being organized into blocks of data;
a bus-sizer for switching between a state of using a part of the bus width of said data bus for accessing said second memory and a state of using all of said bus width for accessing said second memory;
circuitry for, responsive to a signal representative of a condition in which an operand desired by the processor is not stored in the first memory, (a) accessing a block in the second memory containing said operand through a series of accesses of memory locations sufficient to retrieve said block, (b) transmitting said block over said bus through a series of successive transfers of data units over said bus, said units having a first width in the case in which all of said bus width of said data bus is used, and having a second width less than said first width in the case in which a part of the bus width of said data bus is used, and (c) storing

said transmitted block in said first memory..Iaddend..Iadd.20. The apparatus of claim 19 wherein said processor comprises a microprocessor,

and said first memory comprises a cache memory..Iaddend..Iadd.21. A method for accessing memory in a data processing system including a microprocessor, a first memory for storing blocks of data, a data bus having an effective bus width selectable between a first width and a second width less than said first width, and a second memory which is connected to said microprocessor through said data bus, said second memory having a plurality of addressable memory locations which are capable of being organized into blocks, and which define a plurality of memory boundaries spaced by said first width, the method comprising the steps of:

selecting whether the effective bus width of said data bus is to be said first width or said second width;
generating a signal indicating that an operand desired by the microprocessor is not present in said first memory;
responsive to said signal, generating an address of a memory location within a block of the second memory which contains the operand;
accessing said block through a series of accesses of memory locations sufficient to retrieve said block;
transmitting said block over said bus through a series of successive transfers of data units over said bus, said data units having a width which is less than or equal to said selected width;
if the effective bus width is selected to be said first width, beginning said transmitting with a data unit beginning on one of said memory boundaries and containing at least part of said desired operand;
if the effective bus width is selected to be said second width, beginning said transmitting with a data unit beginning on one of said memory boundaries and wholly excluding said desired operand; and
storing said transmitted block in said first memory..Iaddend..Iadd.22. A method for accessing memory in a data processing system including a microprocessor, a first memory for storing blocks of data, a data bus having an effective bus width selectable between a first width and a second width less then said first width, ad a second memory which is connected to said microprocessor through said data bus, said second memory having a plurality of addressable memory locations which are capable of being organized into blocks of data segments having said first width, the method comprising the steps of:
selecting whether the effective bus width of said data bus is to be said first width or said second width;
generating a signal indicating that an operand desired by the microprocessor is not present in said first memory;
responsive to said signal, generating an address of a memory location within a particular data segment of a block of the second memory at which said operand begins;
accessing said block through a series of accesses of memory locations sufficient to retrieve said block;
transmitting said block over said bus through a series of successive transfers of data units aver said bus, said data units having a width which is less than or equal to said selected width;
when the effective bus width is either of said first and second widths accomplishing said transmitting in an order which does not vary depending on where the desired operand begins within said particular segment having said first width; and
storing said transmitted block in said first memory..Iaddend..Iadd.23. A method of accessing a block of memory through a data bus in a data processing system including a microprocessor, cache memory coupled to or within the microprocessor for storing blocks of data, an external data bus having a selectable width, and an external memory coupled to said microprocessor through said bus, comprising the steps of:
selecting a width from a plurality of predetermined widths;
sizing said bus to said selected width;
in response to a cache miss condition, accessing said block from said external memory, and transmitting said block over said bus through a burst of successive transfers of data units, said data units having a width which is less than or equal to said selected width;
accomplishing said transmitting beginning with a data unit wholly excluding said desired operand; and
updating said cache memory with said transmitted block..Iaddend..Iadd.24. A method for accessing memory in a data processing system including a microprocessor, a first memory for storing blocks of data, a data bus having an effective bus width selectable between a first width and a second width less than said first width, and a second memory which is connected to said microprocessor through said data bus, said second memory having a plurality of addressable memory locations which are capable of being organized into blocks of data, the method comprising the steps of:
selecting whether the effective bus width of said data bus is to be said first width or said second width;
generating a signal indicating that an operand desired by the microprocessor is not present in said first memory;
responsive to said signal, generating an address of address of a memory location within a block of the second memory which contains the operand;
accessing said block through a series of accesses of memory locations sufficient to retrieve said block;
transmitting said block over said bus through a series of successive transfers of data units over said bus, said data unit having a width which is less or equal to said selected width;
if said effective width of said data bus is selected to be said first width, accomplishing said transmitting beginning with a data unit containing at least in part the desired operand;
if said effective width said data bus is selected to be said second width, accomplishing said transmitting beginning with a data unit wholly excluding said desired operand; and

storing said transmitted block in said first memory..Iaddend..Iadd.25. A method for accessing memory in a data processor, said data processor having a microprocessor, means for storing a block of data, an external data bus having an effective bus width selectable, between n-bytes and n/2 bytes, wherein n is an even integer, and an external memory which is connected to said microprocessor through said external data bus, said external memory having a plurality of addressable memory locations each having width of n-bytes and each having upper half and a lower half, the method comprising the steps of:

selecting whether said effective bus width of said external data bus is to be n-bytes, or n/2 bytes;
generating an access request to access a specific addressable memory location in said external memory;
generating a head address of a block of data to be accessed, wherein said head address is generated based on said specific addressable memory location;
accessing said external memory, wherein said accessing is accomplished in a series of accesses sufficient to retrieve a block of data;
generating a bus transfer finishing signal upon completion of each of said series of accesses;
transferring said block of data through an internal data bus said internal data bus, having a bus width equal to n-bytes;
when the effective bus width is n-bytes and when the effective bus width is n/2-bytes, storing said block of data, wherein said storing is accomplished in an order which does not vary depending upon whether said specific addressable memory location begins within the upper half of an n-byte unit, or within the lower half of the n-byte unit; and
transferring said block of data to said means for storing..Iaddend..Iadd.26. A method for accessing memory in a data processor, said data processor having a microprocessor, means for storing a block of data, an external data bus having an effective bus width selectable between n-bytes and n/2 bytes, wherein n is an even integer, and an external memory which is connected to said microprocessor through said external data bus, said external memory having a plurality of addressable memory locations each having a width of n-bytes and each having upper half and a lower half the method, comprising the steps of:
selecting whether said effective bus width of said external data bus is to be n-bytes or n/2 bytes;
generating an access request to access a specific addressable memory location said external memory;
generating a head address of a block of data to be accessed, wherein said head address is generated based on said specific addressable memory locations;
accessing said external memory, wherein said accessing is accomplished in a series of accesses sufficient to retrieve a block of data;
generating a bus transfer finishing signal upon completion of each of said series of accesses;
transferring block of data through an internal data bus, said internal data bus having a bus width equal to n-bytes;
when the specific addressable memory location begins within the upper half of an n-byte unit, and when it begins within the lower half of an n-byte unit storing said block of data, wherein said storing is accomplished in a certain order if said external bus width is n-bytes, and is accomplished in the same order if said external bus width is n/2 bytes; and
transferring said block of data to said means for storing..Iaddend..Iadd.27. The method of claim 26 in which n is 8 and said block of data is 256 bits wide..Iaddend..Iadd.28. A method for accessing memory in a data processing system including a microprocessor, a first memory for storing blocks of data, a data bus having an effective bus width selectable between a first width and a second width less than said first width, and a second memory which is connected to said microprocessor through said data bus, said second memory having a plurality of addressable memory locations which are capable of being organized into blocks, the method comprising the steps of:
selecting whether the effective bus width of said data bus is to be said first width or said second width;
generating a signal indicating that an operand desired by the microprocessor is not present in said first memory;
responsive to said signal, generating an address of a memory location within a block of the second memory which contains the operand;
accessing said block through a series of accesses of memory locations sufficient to retrieve said block;
transmitting said block over said bus through a series of successive transfers of data units over said bus, said data units having a width which is less than or equal to said selected width;
if said effective bus width is selected to be said first width, providing said data units to an internal bus;
if said effective bus width is selected to be said second width, successively combining selected ones of said data units into combined data units, and providing said combined data units to said internal bus; and
storing said transmitted block in said first memory..Iaddend..Iadd.29. A method of accessing a block of memory having a width and containing a desired operand through a data bus in a data processing system including a microprocessor, a cache memory coupled to or within the microprocessor for storing blocks of data, an external data bus having a selectable width, and an external memory coupled to said microprocessor through said bus, comprising the steps of:
selecting a width from a plurality of predetermined widths;
sizing said bus to said selected width;
in response to a cache miss condition, accessing said block from said external memory, and transmitting said block over said bus through a burst of successive transfers of data units, said data units having a width which is less than or equal to said selected width;
successively combining selected ones of said data units into combined data units, and providing said combined units to said internal bus; and
updating said cache memory with said transmitted block..Iaddend..Iadd.30. A data processor apparatus comprising:
a processor;
a data bus having a bus width;
a first memory for storing blocks of data which is coupled to said processor through an internal bus;
a second memory which is coupled to said processor through said data bus, said second memory having a plurality of addressable memory locations which are capable of being organized into blocks of data;
a bus-sizer for switching between a state of using a part of the bus width of said data bus for accessing said second memory and a state of using all of said bus width for accessing said second memory;
circuitry for, responsive to a signal representative of a condition in which an operand desired by the processor is not stored in the first memory, (a) accessing a block in the second memory containing said operand through a series of accesses of memory locations sufficient to retrieve said block, (b) transmitting said block over said bus through a series of successive transfers of data units over said bus, said units having a first width in the case in which all of said bus width of said data bus is used, and having a second width less than said first width in the case in which a part of the bus width of said data bus is used, (c) if all of said bus width of said data bus is used, providing said data units to said internal bus, (d) if part of said bus width of said data bus is used, successively combining selected ones of said data units into combined units, and providing said combined units to said internal bus, and (e) storing said transmitted block in said first memory..Iaddend..Iadd.31. A data processor apparatus comprising:
a processor;
a data bus having a bus width;
a first memory for storing blocks of data which is coupled to said processor through an internal bus;
a second memory which is coupled to said processor through said data bus, said second memory having a plurality of addressable memory locations which are capable of being organized into blocks of data;
a bus-sizer for switching between a state of using a part of the bus width of said data bus for accessing said second memory and a state of using all of said bus width for accessing said second memory;
circuitry for, responsive to a signal representative of a condition in which an operand desired by the processor is not stored in the first memory, (a) accessing a block in the second memory containing said operand through a series of accesses of memory locations sufficient to retrieve said block, (b) transmitting said block over said bus through a series of successive transfers of data units over said bus, said data units having a first width in the case in which all of said bus width of said data bus is used, and having a second width less than said first width in the case in which a part of the bus width of said data bus is used, (c) if all of said bus width of said data bus is used, beginning said transmitting with a data unit containing at least in part said desired operand, (d) if part of said bus width of said data bus is used, beginning said transmitting with a data unit which may wholly exclude said desired operand, and (e) storing said transmitted block in said first memory..Iaddend..Iadd.32. A data processor apparatus comprising:
a processor;
a data bus having a bus width;
a first memory for storing blocks of data which is coupled to said processor through an internal bus;
a second memory which is coupled to said processor through said data bus, said second memory having a plurality of addressable memory locations which are capable of being organized into blocks of data defining a plurality of memory boundaries spaced by a first width;
a bus-sizer for switching between a state of using a part of the bus width of said data bus for accessing said second memory and a state of using all of said bus width for accessing said second memory;
circuitry for, responsive to a signal representative of a condition in which an operand desired by the processor is not stored in the first memory, (a) accessing a block in the second memory containing said operand through a series of accesses of memory locations sufficient to retrieve said block, (b) transmitting said block over said bus through a series of successive transfers of data units over said bus, said data units having said first width in the case in which all of said bus width of said data bus is used, and having a second width less than said first width in the case in which a part of the bus width of said data bus is used, (c) if all of said bus width of said data bus is used, beginning said transfers with a data unit beginning on one of said plurality of memory boundaries spaced by said first width, (d) if part of said bus width of said data bus is used, also beginning said transfers with a data unit beginning on one of said plurality of memory boundaries, even if said data unit wholly excludes said desired operand, and (e) storing said transmitted block in

said first memory..Iaddend..Iadd.33. A method for accessing memory in a data processing system including a microprocessor, a first memory for storing blocks of data, a data bus having an effective bus width selectable between a first width and a second width less than said first width, and a second memory which is connected to said microprocessor through said data bus, said second memory having a plurality of addressable memory locations which are capable of being organized into blocks of data, the method comprising the steps of:

selecting whether the effective bus width of said data bus is to be said first width or said second width;
generating a signal indicating that an operand desired by the microprocessor is not present in said first memory;
responsive to said signal, generating an address of a memory location within a block of the second memory which contains the operand;
accessing said block through a series of accesses of memory locations sufficient to retrieve said block;
transmitting said block over said bus through a series of successive transfers of data units over said bus, said data units having a width which is less than or equal to said selected width;
if said effective width of said data bus is selected to be said first width, accomplishing said transmitting in a certain order beginning with a data unit containing at least in part the desired operand;
if said effective width of said data bus is selected to be said second width, accomplishing said transmitting in the same order beginning with a data unit wholly excluding said desired operand; and

storing said transmitted block in said first memory..Iaddend..Iadd.34. A data processor comprising a microprocessor, an external data bus having a bus width, and an external memory which is connected to said microprocessor, and which has a plurality of addressable memory locations which are capable of being organized into blocks of data segmented by memory boundaries spaced by a first width, wherein said data processor is provided with:

bus-sizing means for switching between a state of using a part of the bus width of said external data bus and a state of using all of said bus width for accessing said external memory;
accessing means for, responsive to a signal representative of a condition in which an operand desired by the processor is not stored in the external memory, accessing said external memory successively by executing a predetermined number of external bus accesses as a set, and
a bus interface circuit for receiving a request for an access start and starting an external bus access to said external memory; and
wherein said bus interface circuit, in response to a request for an access start
when all of said bus width of said external data bus is used, generates a single set of successive external bus accesses, and receives successive data units over said external bus in response thereto, the data units having said first width, beginning with a data unit on one of said memory boundaries spaced by said first width, and
when a part of the bus width of the external data bus is used, generates a plurality of sets of successive external bus accesses, starts each set of successive external bus accessing by generating addresses for the first external bus access of each set of successive external bus accesses to access successively a memory area of the same size as in the case where all of said bus width of said external data bus is used, and, for each set, receives successive data units over said external bus in response thereto, the data units having a width less than said first width, beginning with a data unit on one of said memory boundaries spaced by said first width even when the data unit wholly excludes the desired operand..Iaddend.
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Patent History
Patent number: RE36052
Type: Grant
Filed: Mar 18, 1996
Date of Patent: Jan 19, 1999
Assignee: Mitsubishi Benki Kabushiki Kaisha
Inventors: Souichi Kobayashi (Hyogo), Yuichi Saito (Hyogo)
Primary Examiner: Glenn A. Auve
Law Firm: Lyon & Lyon LLP
Application Number: 8/617,467
Classifications
Current U.S. Class: 395/307; 395/855
International Classification: G06F 1340;