Patents Issued in May 3, 2001
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Publication number: 20010000644Abstract: A secure enclosure (10) for an automated banking machine includes a chest portion (12) and a moveable door (14). The door is supported on hinge assemblies (20, 22) which enable mounting and accurately positioning the door despite misalignment of the hinges. The chest portion is manufactured from panels (28, 36, 38, 66, 76) which include interengaging projections and recesses. The projections and recesses ensure that the proper panels are used in the assembly of the particular type secure enclosure, as well as that the panels which make up the enclosure are properly oriented.Type: ApplicationFiled: December 1, 2000Publication date: May 3, 2001Applicant: InterBoldInventors: Kim R. Lewis, Richard C. Lute, Jeffrey A. Hill, Howard E. Antram
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Publication number: 20010000645Abstract: A color cathode-ray tube includes a panel portion, a neck portion, a funnel portion connecting the panel and neck portions, a fluorescent layer formed on an inner surface of a face plate of the panel portion, a shadow mask disposed opposite to the fluorescent layer, an electron gun housed in the neck portion, and an internal magnetic shield disposed in the funnel portion. The internal magnetic shield is formed in a substantially quadrangular pyramid-shape having a substantially rectangular first opening with a smaller diagonal dimension at one end adjacent to the electron gun and a substantially rectangular second opening with a larger diagonal dimension than the smaller diagonal dimension at the other end adjacent to the shadow mask.Type: ApplicationFiled: December 11, 2000Publication date: May 3, 2001Inventor: Mutsumi Maehara
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Publication number: 20010000646Abstract: A test system for testing semiconductor components, such as bumped dice and chip scale packages, is provided. The test system includes a base for retaining one or more components, and an interconnect for making temporary electrical connections with the components. The test system also includes an alignment fixture having an alignment surface for aligning the components to the interconnect. In addition, the components can include alignment members, such as beveled edges, bumps, or posts configured to interact with the alignment surface. The alignment fixture can be formed as a polymer layer, such as a layer of resist, which is deposited, developed and then cured using a wafer level fabrication process. The alignment surface can be an opening in the polymer layer configured to engage edges of the components, or alternately to engage the alignment members.Type: ApplicationFiled: December 20, 2000Publication date: May 3, 2001Inventors: Salman Akram, Warren M. Farnworth, David R. Hembree
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Publication number: 20010000647Abstract: A method of testing integrated circuitry includes providing a substrate comprising integrated circuitry to be tested. The circuitry substrate to be tested has a plurality of exposed conductors in electrical connection with the integrated circuitry. In one implementation, at least some of the exposed conductors of the circuitry substrate are heated to a temperature greater than 125° C. and within at least 50% in degrees centigrade of and below the melting temperature of the exposed conductors of the circuitry substrate. In one implementation, such are heated to a temperature below their melting temperature yet effective to soften said at least some of the exposed conductors to a point enabling their deformation upon application of less than or equal to 30 grams of pressure per exposed conductor. The circuitry substrate is engaged with a tester substrate.Type: ApplicationFiled: December 15, 2000Publication date: May 3, 2001Inventor: Salman Akram
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Publication number: 20010000648Type: ApplicationFiled: December 15, 2000Publication date: May 3, 2001Inventor: Salman Akram
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Publication number: 20010000649Abstract: This invention teaches an apparatus and method for determining a more efficient quality assurance or reliability test screen without falsely rejecting, i.e., over stressing, short channel length devices during voltage stress test screening. Short channel lengths devices fabricated on a semiconductor wafer have a higher tendency to fail at voltage levels that would otherwise not harm long channel length devices. The failures, however, are not related to device defects. Protection to the more vulnerable devices is provided by determining the speed of the die prior to the voltage test screen, thus, segregating the devices based on operational speed performance. Next, a lower voltage is effectively applied during wafer probe test to the faster devices, which directly correspond to the population of short channel devices. A preferred measurement for device speed entails measuring the drain-to-source current of each FET, and dividing the resultant sum by the device gate channel width.Type: ApplicationFiled: December 15, 2000Publication date: May 3, 2001Inventors: Roger W. Fleury, Jon A. Patrick
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Publication number: 20010000650Abstract: A test system for testing semiconductor components includes an interconnect having contacts for making temporary electrical connections with terminal contacts on the components. The interconnect contacts can be configured to electrically engage planar terminal contacts (e.g., bond pads, test pads) or bumped terminal contacts (e.g., solder bumps, solder balls) on the components. The test system also includes an alignment member for aligning the components to the interconnect. Different embodiments of the alignment member include: a curable polymer material molded in place on the interconnect; an alignment opening formed as an etched pocket in a substrate of the interconnect; and a separate fence attached to the interconnect using an alignment fixture.Type: ApplicationFiled: December 27, 2000Publication date: May 3, 2001Inventors: Salman Akram, Warren M. Farnworth, Michael E. Hess, David R. Hembree
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Publication number: 20010000651Type: ApplicationFiled: December 26, 2000Publication date: May 3, 2001Inventors: Tom G. Miller, Roger L. Verkuil, Gregory S. Horner
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Publication number: 20010000652Abstract: An output synchronization-free NOR gate detects the all-zero scenario for an n-bit word. The n-bit word has a selected bit that is defined using a high-inactive convention, and (n−1) non-selected bits that are defined using a high-active convention. The NOR gate includes an output FET, a pre-charging circuit, a first evaluation circuit, and (n−1) second evaluation circuits. The pre-charging circuit charges the output FET gate, drain, and source to a pre-charge voltage during a low clock cycle. During a high clock cycle, the first evaluation circuit evaluates the selected bit and discharges the pre-charge voltage on the output FET source if the selected bit is a voltage high. The (n−1) second evaluation circuits evaluate the non-selected bits and maintain the pre-charge voltage on the output FET gate if each of the non-selected bits is a voltage low. The output FET conducts if the pre-charge voltage is maintained on the output FET gate and if the output FET source is discharged to ground.Type: ApplicationFiled: December 13, 2000Publication date: May 3, 2001Inventor: Jimmy Lee Reaves
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Publication number: 20010000653Abstract: The object of the present invention is to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor.Type: ApplicationFiled: December 28, 2000Publication date: May 3, 2001Inventors: Yoji Nishio, Kosaku Hirose, Hideo Hara, Katsunori Koike, Kayoko Nemoto, Tatsumi Yamauchi, Fumio Murabayashi, Hiromichi Yamada
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Publication number: 20010000654Abstract: A voltage level translator is disclosed which translates a CMOS input signal into a CMOS output signal where the low voltage level of the output signal is equal to the high voltage level of the input signal. The voltage level translator is described in an integrated circuit such as memory circuits, including DRAMs. Specifically, the voltage level translator produces an output signal which can be used as a gate voltage on a precharge transistor for a booted circuit where the gate voltage need only drop to the high voltage level of the input signal to shut the transistor off. The voltage level translator described, therefore, reduces the time and power required to translate an input signal by limiting the voltage swing of the output signal.Type: ApplicationFiled: December 19, 2000Publication date: May 3, 2001Applicant: Micron Technology, Inc.Inventors: Todd A. Merritt, Troy A. Manning
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Publication number: 20010000655Abstract: An internal power supply voltage generation circuit includes a main amplifier that supplies a current from an external power supply node to an internal power supply line in accordance with the difference between a reference voltage from a reference voltage generation circuit and an internal power supply voltage on the internal power supply line. The current supply amount by the main amplifier is adjusted by a level adjust circuit, according to the difference between the external power supply voltage and the reference voltage. The internal power supply voltage generation circuit can suppress reduction in the internal power supply voltage in the vicinity of the lower limit area of the differential power supply voltage.Type: ApplicationFiled: December 19, 2000Publication date: May 3, 2001Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Fukashi Morishita
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Publication number: 20010000656Abstract: A conducting film is formed on a dielectric block in a dielectric waveguide resonator, and a through-hole is formed in the dielectric block. The unloaded Q is set by selecting the outside dimensions of the dielectric block. The resonance frequency is set by selecting the size and location of the through-hole as well as the outside dimensions of the dielectric block. A terminal electrode is formed on a side surface of the dielectric block. A coupling hole is formed in the dielectric block and a coupling electrode is formed on the inner surface of the coupling hole. One end of the coupling electrode is connected to the terminal electrode and the coupling electrode extends toward the conducting film formed on the opposite side surface and one end surface of the dielectric block. The above structure allows an increase in the degree of freedom in the design of the characteristics including the resonance frequency and unloaded Q of the dielectric waveguide resonator.Type: ApplicationFiled: December 5, 2000Publication date: May 3, 2001Inventors: Shigeji Arakawa, Kikuo Tsunoda
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Publication number: 20010000657Abstract: A bandpass filter having three waveguide cavities problessly coupled in a tri-section for producing an asymmetric response about a passband. In another aspect, the bandpass filter also includes first and second waveguide tri-sections coupled in series via a common waveguide cavity, providing a bandpass waveguide filter having transmission zeroes on only one side a filter passband.Type: ApplicationFiled: December 20, 2000Publication date: May 3, 2001Applicant: K&L Microwave, Inc.Inventor: Rafi Hershtig
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Publication number: 20010000658Abstract: An electronic device has three conductive polymer layers sandwiched between two external electrodes and two internal electrodes. The electrodes are staggered to create a first set of electrodes, in contact with a first terminal, alternating with a second set of electrodes in contact with a second terminal.Type: ApplicationFiled: December 6, 2000Publication date: May 3, 2001Inventors: Andrew Brian Barrett, Steven D. Hogge, Wen Been Li, Kun Ming Yang
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Publication number: 20010000659Abstract: A reader and/or writer apparatus having an antenna lying substantially in a plane for generating an electromagnetic field to supply power to an IC card and a conductor member to be disposed in a plane substantially parallel to the plane of the antenna, wherein the distance between the antenna and the conductor member is no greater than 20 mm. A power supplying system supplies power using electromagnetic waves from the reader and/or writer apparatus to the IC card. The IC card includes a circuit for converting the supplied power to a D.C. voltage and for supplying the D.C. voltage to an internal circuit of the IC card.Type: ApplicationFiled: December 22, 2000Publication date: May 3, 2001Inventors: Yoshihiko Hayashi, Takashi Suga, Kouichi Uesaka, Ryouzou Yoshino, Keisuke Igarashi
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Publication number: 20010000660Abstract: The method and apparatus of the present invention is directed to architectures for signal processing, such as for performing analog-to-digital and digital-to-analog conversions, in which the source signal is decomposed into subband signals by an analysis filter, processed, and the processed subband signals combined to form a reconstructed signal that is representative of the source signal.Type: ApplicationFiled: December 4, 2000Publication date: May 3, 2001Applicant: DATA FUSION CORPORATIONInventors: Wolfgang Kober, John K. Thomas
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Publication number: 20010000661Abstract: According to the present invention, various logic circuits, AD converters, DA converters and counter circuits can be constituted with a small number of transistors by employing a capacitive coupling circuit.Type: ApplicationFiled: December 21, 2000Publication date: May 3, 2001Applicant: Fujitsu LimitedInventor: Yoshihiro Miyamoto
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Publication number: 20010000662Abstract: In a display having a case where an image signal is inputted to the same row of a display section at an odd field period and an even field period, even if an AC driving is performed, a problem of a deterioration of a device due to a burning of a liquid crystal of an image display section by inputting the image signal including a still image such as a character or the like. Therefore, the polarity of the image signal is inverted every field and the polarity is further inverted every arbitrary n frames. In the n-frame inversion, a 1-field inversion pulse like &phgr;FRP that is outputted from a control circuit is further converted to an arbitrary n-frame inversion pulse by using an inverter, a switch, a counter, and the like. Thus, a signal processing circuit converts the image signals (R, G, B) to image signals like FIG. 1B whose polarities are inverted every one field and n fields.Type: ApplicationFiled: December 18, 2000Publication date: May 3, 2001Inventors: Seiji Hashimoto, Daisuke Yoshida
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Publication number: 20010000663Abstract: Improvements in haptic feedback control devices include several embodiments. A haptic feedback control device includes a housing and a pair of moveable pincher members coupled to the housing. Each pincher member is contacted by a finger of the user when the device is operated and moveable in a degree of freedom approximately within a single plane. An actuator outputs force feedback on the pincher members in the degrees of freedom, and a sensor detects a position of the pincher members in the degrees of freedom. The device housing includes a fixed portion and a moveable portion, where the user grips both fixed and moveable portions. A coupling, such as a flexure, allows the moveable portion to move relative to the fixed portion in a direction parallel to an outer surface of the moveable portion contacted by the user. An actuator outputs a force on the flexure to cause the moveable portion to move, such as an oscillating force to cause vibration.Type: ApplicationFiled: December 19, 2000Publication date: May 3, 2001Applicant: Immersion CorporationInventors: Erik J. Shahoian, Christopher J. Hasser, Louis B. Rosenberg
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Publication number: 20010000664Abstract: In an electronic device, a combination of an electronic visual display on a housing, electronic circuitry in the housing, the housing having at least one human user depressible surface with associated analog pressure-sensitive element for output of a signal of variable value utilized by the circuitry to control or manipulate one or more functions of the device. The at least one analog pressure-sensitive element receives pressure applied by a user's finger or thumb to the depressible surface, varied pressure applied by the user determines varied value of the signal. The resultant control manipulation from the analog variable value is in some manner indicated, displayed or made visually detectable on the display at least at the time of manipulation so that the user receives visual feedback allowing termination, increase or decrease, if needed or desired, of finger pressure on the depressible surface of the analog sensor.Type: ApplicationFiled: December 8, 2000Publication date: May 3, 2001Inventor: Brad A. Armstrong
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Publication number: 20010000665Abstract: A screen operator or artificial finger tip for entering commands and data into a personal data device, such as an electronic notebook, by contacting the screen of the personal data device. The screen operator comprises a partially rigid base that encircles the finger, generally conforming to the finger, and a rigid tip member which projects forwardly from the base to contact the screen. The extreme tip of the tip member is of reduced diameter at the point of contact with the screen. The base is tubular (preferably with a gap) and resiliently grips the finger. A hook member extends downwardly and back from the tip member to engage the underside of the user's finger tip. The hook member functions to retain the screen operator on the user's finger tip.Type: ApplicationFiled: December 18, 2000Publication date: May 3, 2001Inventor: Karl Robb
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Publication number: 20010000666Abstract: A transmitter pen positioning system is provided, in which a pen, having multiple output elements, is used to accurately determine the location of the pointing tip of the pen, in relation to the writing area of a surface, such as a white board. The first output element, preferably an infrared transducer, transmits a first output signal from the transmitter pen. The second output element, preferably an ultrasonic transducer, transmits a second output signal, having a lower propagation velocity than the first output signal, from the transmitter pen to two or more receivers. In a basic embodiment, the first output signal arrives at one or more receivers generally concurrently.Type: ApplicationFiled: December 18, 2000Publication date: May 3, 2001Inventors: Robert P. Wood, Serge Plotkin, Jacob Harel, Alfred Samson Hou
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Publication number: 20010000667Abstract: The present invention provides a display control system for controlling data which is displayed on a screen of a display unit. The system includes a pointing device for pointing to a position on the screen of the display unit, a deleting unit for gradually deleting elements of data from the screen of the display unit as if the elements were gradually being sucked at the position pointed to by the pointing device, and a density controller for controlling the density of elements remaining on the screen of the display unit so that the density is gradually decreased in accordance with suction of the elements.Type: ApplicationFiled: December 13, 2000Publication date: May 3, 2001Inventors: Toru Okawa, Ryuichi Matsukura, Yasuo Sato
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Publication number: 20010000668Abstract: A portable computing device or “information appliance” having terse user input (e.g., limit set of keys) is provided with a user interface for navigating user data. Application programs, which are provided for user operation of the device, are implemented as separate modules controlled by a module selector. The module selector serves as a user interface or shell representing the top-level or “home” display presented to a user. The module selector presents the user with selection icons for navigating to different applications or modules of functionality. The user interface implements a “single-click” style of button operation, so that users can associate each button with a particular task for a given program context. In addition to the single-click style, “click consistency” is imposed for each button.Type: ApplicationFiled: December 22, 2000Publication date: May 3, 2001Inventor: Eric O. Bodnar
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Publication number: 20010000669Abstract: An ink jet recording apparatus for discharging ink to perform recording comprises a carriage member for mounting recording means for discharging ink, a cleaning member arranged to face the regions other than the region for the aforesaid recording means to clean the discharging port formation face of the aforesaid recording means, transporting means for transporting the aforesaid cleaning member to a position to clean recording means and a position not to clean it, and driving means for relatively driving the aforesaid carriage member and transporting means for the aforesaid cleaning member to clean the aforesaid discharging port formation face. The aforesaid cleaning member is provided with a first cleaning member mainly used for cleaning the discharging port formation portion of the aforesaid recording means and a second cleaning member mainly used for cleaning the circumference of the aforesaid discharging port formation portion.Type: ApplicationFiled: December 20, 2000Publication date: May 3, 2001Inventors: Haruo Uchida, Hiroshi Tajika
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Publication number: 20010000670Abstract: K replacement for color digital image printing reduces the computational complexity and processing resource requirements of an image printing system. The invention is implemented using a variety of devices capable of reproducing image data including color photo-copy machines, color facsimiles, color printers, black and white printers, and digital printers. The image printing system is employed in a multi-functional peripheral capable of performing several functions. The image printing system detects whether or not ink is to be printed using all of the available print channels in the system. If ink is to be printed using a predetermined number of the print channels, the image printing system performs K replacement and applies error diffusion to a predetermined number of the print channels. In certain embodiments, K replacement is performed only when the spectral content of a given pixel falls within a predetermined range of a spectrum.Type: ApplicationFiled: December 21, 2000Publication date: May 3, 2001Inventor: Anatoly Moskalev
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Publication number: 20010000671Abstract: A thermal head of a thermal printer is provided with an array of parallel connected heating elements and transistors connected in series to the heating elements in one to one relation. In a resistance measuring mode, one of the transistors connected to one heating element whose resistance is to measure is turned on, and other transistors are turned off. In this condition, a capacitor connected in parallel to the heating element is charged up to a predetermined voltage, and then discharged. A counter circuit starts time-counting by a short unit time t0 when a predetermined delay time Tmin has passed since the start of discharging, and outputs a count Q when the charged voltage goes down to a predetermined level. Based on a discharge time T=Tmin+t0·Q, the resistance of the heating element is calculated.Type: ApplicationFiled: December 6, 2000Publication date: May 3, 2001Inventor: Junji Hayashi
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Publication number: 20010000672Abstract: A video scope has an entry section which can advance into an object; and a grip section which is disposed at the back of the entry section and to be held by an operator, wherein a light reflecting body, an objective lens, a solid-state image pickup device, a light source, a window of incidence for image pickup rays and illumination windows located in the vicinities of the window of incidence are disposed in the entry section, and wherein at least a power source is disposed in the grip section for driving the light source. A portable accommodation case has an accommodation space for accommodating the video scope; and a lid which has a thin display attached thereto, and can rotate freely and stop at an optional position, wherein the thin display is capable of displaying an image which is picked up by the video scope.Type: ApplicationFiled: December 28, 2000Publication date: May 3, 2001Inventors: Kiyoko Ooshima, Hiroshi Atsuta, Shinji Uchida, Hiroyuki Yamakita
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Publication number: 20010000673Abstract: Method of evaluating degradation of electrical signals is disclosed. The method involves visually comparing a visual representation of a reference signal generated by a test signal source, which can be made identical to an original signal, and a degraded signal generated by another test signal source after passing through a video system.Type: ApplicationFiled: December 20, 2000Publication date: May 3, 2001Inventor: Jack Gershfeld
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Publication number: 20010000674Abstract: An automatic focus adjusting device is provided with an AF evaluation value detecting circuit for detecting an AF evaluation value indicative of a focusing state of a lens, a lens driving part for moving the lens in an optical axis direction, a control circuit for controlling the lens driving part on the basis of the AF evaluation value detected by the AF evaluation value detecting circuit in such a way as to cause the lens to move back and forth by a predetermined amount of movement at a time until the AF evaluation value becomes a maximum value, an inversion detecting circuit for detecting inversion of a direction of movement of the lens, and an altering circuit for altering the predetermined amount of movement of the lens in response to detection of the inversion by the inversion detecting circuit.Type: ApplicationFiled: December 15, 2000Publication date: May 3, 2001Inventor: Hitoshi Yasuda
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Publication number: 20010000675Abstract: Plural n number of encoders 21, 22 . . . 2n carry out reading in advance of parameter information PAR. #1, #2 . . . #n with respect to respective n number of programs prog. 1, 2 . . . n to allow a controller 3 to estimate encoding difficulty related information “difficulty” when picture is encoded, and to compression-encode the plural n number of programs on the basis of target encoding rate that the controller 3 has calculated on the basis of the parameter information. The controller 3 calculates allocation code quantities target_rate #1, #2 . . . #n every respective programs from the parameter information PAR. #1, #2 . . . #n. A multiplexer 4 multiplexes streams “stream” #1, #2 . . . #n that the encoders 21, 22 . . . 2n have encoded in correspondence with the allocation code quantities target_rate #1, #2 . . . #n.Type: ApplicationFiled: December 18, 2000Publication date: May 3, 2001Applicant: SONY CORPORATION.Inventors: Nobuhisa Obikane, Kanji Mihara, Takuya Kitamura
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Publication number: 20010000676Abstract: A display device using a novel semiconductor device, which includes a pixel matrix, an image sensor, and a peripheral circuit for driving those, that is, which has both a camera function and a display function, and is made intelligent, is provided and a method of manufacturing the same is also provided. One pixel includes a semiconductor device for display and a semiconductor for light reception, that is, one pixel includes semiconductor devices (insulated gate-type field effect semiconductor device) for controlling both display and light reception, so that the display device having a picture reading function is made miniaturized and compact.Type: ApplicationFiled: December 29, 2000Publication date: May 3, 2001Inventors: Hongyong Zhang, Masayuki Sakakura, Hideaki Kuwabara
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Publication number: 20010000677Abstract: An image observing apparatus is arranged to observe outside information from the outside and a display image displayed on an image display device via an optical combiner and via an eyepiece lens superimposed. The outside information and the display image are imaged so as to be superimposed on a surface of a spatial modulator having a two-dimensional pixel structure. Part or all of the outside information and display image is selected on an area basis by the spatial modulator. The outside information and image information thus selected is observed through the eyepiece lens.Type: ApplicationFiled: December 15, 2000Publication date: May 3, 2001Inventors: Akinari Takagi, Yoshihiro Saito, Naosato Taniguchi, Toshiyuki Sudo
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Publication number: 20010000678Abstract: The projection type display apparatus according to the present invention has a prism for separating incident light into a plurality of light components and combining the plurality of modulated color components. The prism is constituted by a plurality of prism assemblies, each including an optical member made of an optically transparent material having a photoelastic constant whose absolute value is not greater than +1.5×10−8 cm2/N with respect to the incident light. More preferably, these plurality of prism assemblies are arranged such that each of a plurality of the separated color components is totally reflected by any of the prism assemblies.Type: ApplicationFiled: December 14, 2000Publication date: May 3, 2001Inventors: Tetsuo Hattori, Masatoshi Sato, Mikio Okamoto, Yoshiro Oikawa
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Publication number: 20010000679Abstract: A curved mirrored surface is used to collect radiation scattered by a sample surface and originating from a normal illumination beam and an oblique illumination beam. The collected radiation is focused to a detector. Scattered radiation originating from the normal and oblique illumination beams may be distinguished by employing radiation at two different wavelengths, by intentionally introducing an offset between the spots illuminated by the two beams or by switching the normal and oblique illumination beams on and off alternately. Beam position error caused by change in sample height may be corrected by detecting specular reflection of an oblique illumination beam and changing the direction of illumination in response thereto. Butterfly-shaped spatial filters may be used in conjunction with curved mirror radiation collectors to restrict detection to certain azimuthal angles.Type: ApplicationFiled: December 21, 2000Publication date: May 3, 2001Inventors: Mehdi Vaez-Iravani, Stanley Stokowski, Guoheng Zhao
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Publication number: 20010000680Abstract: Prevention of the formation of unwanted profiles in the ABS surface by etching of the slider ABS surface, even when gap layers are formed from non-alumina-base nonmagnetic materials differing from the component material of the substrate. Numerous thin film magnetic head elements, consisting of multiple layers including magnetic gap layers composed of nonmagnetic materials, are formed in a lattice array on the surface of a wafer. In the process of formation of these elements, the component materials of the magnetic gap layers existing in the region to be etched in order to form the slider shape are removed in advance. The wafer on the surface of which the elements are formed is cut into individual head blocks, and the surfaces opposing the magnetic recording media, consisting of a cut surface of said head block, are formed into a slider shape by etching.Type: ApplicationFiled: December 20, 2000Publication date: May 3, 2001Inventors: Naoto Matono, Tatsuya Shiromoto, Tomihito Miyazaki
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Publication number: 20010000681Abstract: In a magnetic disk drive which comprises a magnetic head slider, a magnetic head slider support mechanism for supporting the magnetic head slider and moving it to a predetermined position, and a load/unload mechanism for detaching the magnetic head slider from the surface of a magnetic disk or moving it thereto, when the magnetic head slider is detached from the magnetic disk surface for unloading, the magnetic head slider support mechanism is restrained against displacement in at least one direction perpendicular to the magnetic disk surface by a restraining part which is provided at a position, on other than the load/unload mechanism, between the magnetic head slider and a pivot of the magnetic head slider support mechanism. Thus, it is possible to enhance impact resistance of the magnetic disk drive during non-ration.Type: ApplicationFiled: November 29, 2000Publication date: May 3, 2001Applicant: Hitachi, Ltd.Inventors: Akira Iida, Masaaki Matsumoto, Shinsuke Higuchi
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Publication number: 20010000682Abstract: A magnetoresistive effect type reproducing head is formed by stacking a lower magnetic shield made of magnetic material, a lower inter-layer insulation film, a magnetoresistive effect type element for detecting magnetic field by using a magnetoresistive effect, an upper inter-layer insulation film, and an upper magnetic shield made of magnetic material, on a substrate in this order, wherein a resistivity of at least one of the lower and upper magnetic shields is more than 200 &mgr;&OHgr;·cm.Type: ApplicationFiled: December 27, 2000Publication date: May 3, 2001Inventors: Shun-ichi Narumi, Hiroshi Fukui, Katsumi Hoshino, Katsuo Watanabe, Kazue Kudo, Moriaki Fuyama
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Publication number: 20010000683Abstract: A protection device for monitoring current in a power cable to an electrical device and for controlling a remotely located starter for the electrical device in response to a system controller. The device includes a transformer magnetically linked with the power cable to produce a voltage signal in response to the presence of a changing current within the power cable. An input circuit located in a single housing together with the transformer is electrically connected to the transformer so as to receive the voltage signal. The input circuit produces, in response to the voltage signal, either a first signal or a first circuit condition at the output terminal of the input circuit, representative of the changing current in the power cable. A switch circuit also in the same container with the transformer has a terminal for sensing either a second signal or a second circuit condition of the remotely located system controller.Type: ApplicationFiled: December 20, 2000Publication date: May 3, 2001Inventors: Kent J. Holce, Roger S. Cota
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Publication number: 20010000684Abstract: A heat sink is provided for use with stacks of integrated chips. The heat sink includes a thermally conductive body having a heat absorbing section which is inserted within the chip stack, and heat transfer and dissipating sections which are located outside of the chip stack.Type: ApplicationFiled: December 22, 2000Publication date: May 3, 2001Inventors: Kevin G. Duesman, L. Jan Bissey
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Publication number: 20010000685Abstract: A flashlight having a head assembly, a switch assembly and a removable tail cap with a spare bulb holder provided by the tail cap. The spare bulb holder includes a resilient body having an internal, U-shaped wall defining a slot configured to receive a flashlight bulb, a cylindrical wall about the slot and ribs extending between the U-shaped wall and the cylindrical peripheral wall. The slot extends through the cylindrical peripheral wall and includes a first section for receiving the plug of a flashlight bulb, a second section for receiving the flange of a flashlight bulb and a third section for receiving a lens of the flashlight bulb.Type: ApplicationFiled: December 22, 2000Publication date: May 3, 2001Applicant: MAG INSTRUMENT, INC.Inventor: Anthony Maglica
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Publication number: 20010000686Abstract: A first lamp base assembly is provided which includes two separate base components. The first base component is attachable to a lamp via a lamp retainer and to the second base component. The second base component is attachable to the first base component and to a connector. The first component includes a retainer clamp to the lamp. The retainer includes two parallel folded back walls. The retainer is then coupled to outward facing spring arms that slip behind the parallel walls. The retainer and spring arms are adjusted with in plane shifts, including rotations with respect to each other thereby providing final lamp adjustments. The walls and the spring arms are then welded with out pressing directly on the lamp. The spring arms may be further formed with heat conduction resistant slots. A lamp including the foregoing lamp base assemblies is also provided.Type: ApplicationFiled: January 3, 2001Publication date: May 3, 2001Applicant: OSRAM SYLVANIA Inc.Inventor: Charles M. Coushaine
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Publication number: 20010000687Abstract: A 64 Mb DRAM which comprises memory cell array areas 15, sense amplifier areas 16, subword driver areas 17, and cross areas 18. For each horizontal input/output line IOH parallel to the word line W, through holes on the sense amplifiers provide connections between the second metal line hierarchy M2 and the third metal line hierarchy M3. The vertical input/output line IOV parallel to the bit line BL runs through a plurality of memory cell array areas 15 in a direction parallel to the column selection signal line YS and connects to the main amplifier MA outside the memory cell array areas 15. In this input/output line configuration, the greater the number of word lines W selected, the greater the number of bits that can be output.Type: ApplicationFiled: December 12, 2000Publication date: May 3, 2001Inventors: Goro Kitsukawa, Yoji Idei, Kanji Oishi, Akira Ide
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Publication number: 20010000688Abstract: Each of memory cells of a ferroelectric nonvolatile memory includes a MOS field effect transistor and first and second ferroelectric capacitors whose remnant polarization amounts are substantially equal to each other. One-side electrodes of the first and second ferroelectric capacitors are connected to the gate electrode of the MOS field effect transistor. Information is stored by polarizing the thin ferroelectric films of the first and second ferroelectric capacitors in opposite directions to each other with respect to the gate electrode of the MOS field effect transistor. Information is read out by applying a positive voltage pulse to one of the other electrodes of the first and second ferroelectric capacitors while the other one of the other electrodes is kept in the electrically floating state. Further a negative voltage pulse having an absolute value smaller than the positive voltage pulse may be applied, if necessary.Type: ApplicationFiled: December 27, 2000Publication date: May 3, 2001Applicant: Semiconductor Technology Academic Research CenterInventor: Hiroshi Ishiwara
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Publication number: 20010000689Abstract: Trench capacitors are arranged in the form of a matrix at a constant pitch in row directions while being sequentially shifted between adjacent rows by a predetermined pitch. An element isolating insulator film is formed so as to surround active regions, each of which is adjacent to adjacent two capacitors in row directions, together with a partial region of the two capacitors. Transistors, which have gate electrodes continuously formed as word lines, are formed so as to be adjacent to the respective capacitors. One of the source and drain diffusion layers is connected to the capacitor node layer of a corresponding one of the capacitors via a connecting conductor. The other of the source and drain diffusion layers serves as a bit line contact layer shared by adjacent two transistors in the row directions, so that bit lines connected to the respective bit line contact layers in the row directions are formed. Three word lines are provided between adjacent bit line contact layers.Type: ApplicationFiled: December 15, 2000Publication date: May 3, 2001Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Takeshi Kajiyama
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Publication number: 20010000690Abstract: A memory cell array includes spare elements for saving a defective cell. Fuse sets each contain a defective address and mapping information indicative of the relationship between the fuse sets and the spare elements. When the defective address matches an input address, each fuse set outputs a signal for activating a corresponding spare element. The number of the fuse sets within a chip is smaller than the number of the spare elements.Type: ApplicationFiled: December 19, 2000Publication date: May 3, 2001Inventor: Satoru Takase
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Publication number: 20010000691Abstract: In a semiconductor integrated circuit in which an internal voltage generation circuit operating on a power supply voltage supplied through an external terminal forms either or both of a low voltage and a boosted voltage to operate internal circuits, a first internal circuit operating on the power supply voltage supplied through the external terminal or the boosted voltage formed by the internal voltage generation circuit is constituted by a first MOSFET with a gate insulation film having a large thickness adapted to the power supply voltage or boosted voltage, and a second internal circuit operating on the low voltage is constituted by a second MOSFET with a gate insulation film having a small thickness adapted to the low voltage.Type: ApplicationFiled: December 22, 2000Publication date: May 3, 2001Inventors: Hiroki Fujisawa, Kazuhiko Kajigaya, Kenichi Fukui, Toshikazu Tachibana
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Publication number: 20010000692Abstract: A method for a VPX banked architecture. The method of one embodiment first segments a memory array into at least two banks. Each bank comprises of memory cells. The banks are provided with a supply voltage.Type: ApplicationFiled: December 22, 2000Publication date: May 3, 2001Applicant: Intel CorporationInventors: Sandeep K. Guliani, Rajesh Sundaram, Mase J. Taub
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Publication number: 20010000693Abstract: A command decoder receives an externally supplied command independently of an internal clock signal, decodes the command, generates a column access mode instruction signal, and activates a column address activation signal when the internal clock signal uses. An internal column address signal generating circuit generates an internal column address signal from an externally supplied address signal according to the column address activation signal. Accordingly, the internal column address is generated at an advanced timing to enable a following column selecting operation to be started at a faster timing. A synchronous semiconductor memory device capable of performing the column selecting operation at a high speed is thus provided.Type: ApplicationFiled: November 30, 2000Publication date: May 3, 2001Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Takeshi Hamamoto, Zenya Kawaguchi, Motoko Hara