Patents Issued in June 28, 2001
  • Publication number: 20010005120
    Abstract: A method of controlling a powered manipulator in a plurality of workspaces is disclosed. The manipulator includes a handle, a motor, a force sensor, and is in combination with a processor controlling the manipulator. The method includes the steps of imparting force on the control handle, sensing direction and magnitude of the force, and sending data of the force to the processor, The data is processed to establish movement commands for the manipulator. The processor is programmed to establish at least one virtual constraint in a first workspace for limiting movement of the manipulator to prevent an operator from moving the manipulator to a limit of this workspace. After the manipulator is moved in this workspace, the manipulator is relocated from the first workspace into a second workspace different from the first workspace where the manipulator is then moved again.
    Type: Application
    Filed: January 23, 2001
    Publication date: June 28, 2001
    Inventors: Peter Swanson, H. Dean McGee
  • Publication number: 20010005121
    Abstract: A motor controller for an electric power steering system which performs a steering assist operation by applying a torque generated by an electric motor to a steering mechanism. The controller includes: a current command value setting circuit for setting a current command value indicative of an electric current to be applied to the electric motor; a d-q command value setting circuit for setting a d-axis current command value and a q-axis current command value in a d-q coordinate system on the basis of the current command value; and a voltage controlling circuit for controlling a voltage to be applied to the electric motor on the basis of the d-axis current command value and the q-axis current command value.
    Type: Application
    Filed: December 27, 2000
    Publication date: June 28, 2001
    Inventor: Masahiko Sakamaki
  • Publication number: 20010005122
    Abstract: A battery discriminating method discriminates between smart battery packs and dry battery cell packs with a simple structure. A dry battery cell pack is composed of a case for storing a plurality of dry batteries connected in series, plus and minus electrodes which are provided in the case and connected to the poles of the series-connected dry batteries, and a resistance element of which one end is connected to a predetermined connecting point of the series-connected dry batteries and the other end is connected to a terminal provided in the case. A predetermined voltage is supplied to a terminal for discriminating the battery of a battery pack via a resistor, and the voltage value of this terminal is detected to discriminate the type of the battery pack according to the detected voltage value.
    Type: Application
    Filed: January 5, 2001
    Publication date: June 28, 2001
    Applicant: SONY CORPORATION
    Inventor: Yoshinari Higuchi
  • Publication number: 20010005123
    Abstract: An apparatus for monitoring the condition of a battery. The apparatus includes a battery clip that is used to secure a battery to a battery connection and a battery monitoring IC. The battery monitoring IC takes a “load vs. no-load measurement” and the results are recorded in a register. When the battery reaches a certain low voltage state, register bits are set and an output is generated. Furthermore, the exemplary embodiment includes a removal detection circuit for detecting removal and replacement of the battery and for preventing voltage floating on the battery output line.
    Type: Application
    Filed: January 31, 2001
    Publication date: June 28, 2001
    Inventors: Brian W. Jones, Scott E. Jones
  • Publication number: 20010005124
    Abstract: A charge control method by which batteries can be efficiently charged, even if the charging is aborted, as well as a computer which employs such a charge control method is provided. The charge to the main battery is started and then the charge to the main battery is stopped when the amount of electric energy in the main battery reaches a predetermined value (steps 200 to 204). Next, the charge to the second battery is started and then the charge to the second battery is stopped when the amount of electric energy in the second battery reaches a predetermined value (steps 206 to 210). Next, the charge to the main battery is restarted and then the charge to the main battery is stopped when the amount of electric energy in the main battery reaches 100%. Thereafter, the charge to the second battery is restarted and then the charge to the battery is stopped when the amount of electric energy in the second battery reaches 100% (steps 212 to 222).
    Type: Application
    Filed: December 7, 2000
    Publication date: June 28, 2001
    Inventors: Shigefumi Odeohhara, Atsushi Kumaki, Hiroshi Nakagawa, Toshitsugu Mito, Tetsuji Nakamura
  • Publication number: 20010005125
    Abstract: A rectifying circuit (a) comprising a diode Da and a capacitor Ca is provided for a winding Ta on the secondary side of a transformer T. A rectifying circuit (b) comprising Db and Cb is provided for a winding Tb. A charging device Ra connected to one output of the circuit (a) is connected to the+side of a secondary battery E1. The+side of E1 is connected to an output terminal To1 and the+side of E3 through a switching circuit S1. The−side of E1 is connected to the other output of the circuit (a) and connected to the−side of E3 through S2. Rb connected to one output of the circuit (b) is connected to the+side of E2. The+side of E2 is connected to the+side of E4 through S2. The−side of E2 is connected to the other output of the circuit (b) and connected to the−side of E4 through S3. The−side of E4 is connected to an output terminal To2. S4 is provided between the+side of E1 and the−side of E4.
    Type: Application
    Filed: December 26, 2000
    Publication date: June 28, 2001
    Inventors: Tamiji Nagai, Tamon Ikeda
  • Publication number: 20010005126
    Abstract: A charging system for portable equipment is provided which may be used in a system including an information terminal and portable equipment connected to the information terminal. The charging system includes a power supply output device provided with the information terminal and a first battery control device provided with the portable equipment. The power supply output device is capable of supplying electric power, which is supplied to the information terminal, to the portable equipment. The first battery control device receives electric power supplied from the power supply output device and performs a charging operation for a battery of the portable equipment.
    Type: Application
    Filed: December 27, 2000
    Publication date: June 28, 2001
    Inventors: Masaki Ichihara, Kozo Maemura
  • Publication number: 20010005127
    Abstract: A battery charger is capable of accurately determining that a battery has reached a fully charged condition regardless of the kind of the batteries to be charged, the condition of the battery, battery temperature at the time when charging starts, charge current, and ambient temperature. A battery temperature is sampled at every predetermined timing, and a change in battery temperature rise gradient is computed each time the battery temperature is sampled. It is determined that the battery has reached the fully charged condition based on a transition changing from increment to decrement of the change in battery temperature rise gradient.
    Type: Application
    Filed: December 4, 2000
    Publication date: June 28, 2001
    Inventors: Nobuhiro Takano, Shigeru Moriyama
  • Publication number: 20010005128
    Abstract: The present invention relates to a method to generate at least a supply voltage to supply energy to a hearing device, whereas the ratio between the supply voltage and the source voltage is adjustable. The hearing device substantially comprises a source (Q), at least a switching element (S1, . . . , Sn), at least an energy transfer element (EUE), at least an energy storing element (ES), a load (Z) and a control unit (CTRL), whereas the method consists in that, in a first step, the control unit (CTRL) acts on the switching elements (S1, . . . , Sn), such that energy is transferred from the source (Q) to the energy transfer elements (EUE), that, in a second step, the control unit (CTRL) acts on the switching elements (S1, . . . , Sn), such that at least a part of the energy stored in the energy transfer elements (EUE) is transferred to the energy storing elements (ES) to build a supply voltage across the load (Z).
    Type: Application
    Filed: January 16, 2001
    Publication date: June 28, 2001
    Inventors: Enrique M. Blumenkrantz, Erik W. Rasmussen
  • Publication number: 20010005129
    Abstract: A voltage regulator with a current limiter includes a voltage regulating circuit including an amplifier circuit and a feedback circuit. The amplifier circuit includes a ballast or pass resistor and the feedback circuit supplies a first feedback voltage to the amplifier circuit, which is compared to a reference voltage. The voltage regulator further includes a current limiter circuit including a current limiter transistor in series with the ballast transistor and an output of the voltage regulator and a feedback circuit supplying a second feedback voltage to a controller for controlling the current limiter transistor. The controller causes the current limiter transistor to operate between saturation and blocking conditions depending on whether the second feedback voltage, which is representative of the output of the voltage regulator, is above or below a predetermined threshold voltage.
    Type: Application
    Filed: December 11, 2000
    Publication date: June 28, 2001
    Applicant: STMicroelectronics S.A.
    Inventor: Claude Renous
  • Publication number: 20010005130
    Abstract: Apparatus and method are disclosed for providing a classification of inclusions in molten metal. The apparatus and method include the steps of and means for obtaining an analog signal stream from a data collection apparatus, passing the analog signal stream through an analog to digital converter to convert the analog signal stream to a digital signal stream, and partitioning the digital signal stream into a discrete time frame of 5 milliseconds. The digital signal stream is vector normalized to provide a normalized signal stream having a largest amplitude magnitude of 1. The normalized signal stream is compared to a control of a prototype shape for determining a classification for the digital signal stream over the discrete time frame by decision logic to determine hard inclusions versus soft inclusions in the liquid metal.
    Type: Application
    Filed: April 13, 1999
    Publication date: June 28, 2001
    Inventors: RICHARD A. MANZINI, DAVID H. DE YOUNG
  • Publication number: 20010005131
    Abstract: The present invention relates to electronic calibration equipment for verifying the high frequency characteristics of electronic test equipment, including oscilloscopes and time interval analyzers.
    Type: Application
    Filed: December 13, 2000
    Publication date: June 28, 2001
    Applicant: Fluke Precision Measurement Ltd
    Inventor: Simon Timothy Hollingworth
  • Publication number: 20010005132
    Abstract: A method and apparatus for generating a test Pattern enabling the detection of malfunctions produced on loading on an actual equipment in advance such as at the time of production testing. Using a logical analyzer, signal waveform data during a time period beginning with a first time point going back from the time of the malfunction and running until a second time point including the malfunctioning time is acquired. This signal waveform data is converted by a test pattern generating device into a test pattern for an automatic testing equipment for testing a semiconductor device as a device to be test. The test pattern so generated is output and used to change data at the time of malfunction into normal data to generate a pattern of expected values for an output signal of the semiconductor device. It is then checked whether or not input signal setting required in connection with an output signal of the semiconductor device is present in the signal waveform data.
    Type: Application
    Filed: December 22, 2000
    Publication date: June 28, 2001
    Applicant: NEC Corporation
    Inventors: Katsumi Nishikawa, Kazuo Shibata
  • Publication number: 20010005133
    Abstract: A non-contact linear position center has juxtaposed transmit and receive sections with a coupler or slider section interposed therebetween carrying a symmetrical attenuating conductive pattern. The inductive coupling of coils on the transmitter and receive sections is attenuated in accordance with the linear position of the pattern on the coupler. A unique sinusoidal signal is generated whose phase is indicative of the linear position of the coupler.
    Type: Application
    Filed: January 17, 2001
    Publication date: June 28, 2001
    Applicant: BEI Sensors & Systems Company, Inc.
    Inventors: Asad M. Madni, Jim B. Vuong
  • Publication number: 20010005134
    Abstract: A circuit configuration compensates for disturbance variables in a measurement pickup which has a measured-variable dependent resistance that is added from a fundamental resistance, which is independent of measured variables, and a measuring resistance, which is dependent on measured variables. The fundamental resistance and the measuring resistance are disturbance variable-dependent in opposite directions. A bridge circuit has two measurement pickups using difference evaluation to eliminate the disturbance variable dependency of the fundamental resistance. A bridge voltage controller sets the bridge diagonal voltage in the opposite direction to the disturbance variable dependency of the measuring resistance, and thus compensates for the disturbance variable-dependency of the measuring resistance.
    Type: Application
    Filed: December 14, 2000
    Publication date: June 28, 2001
    Inventors: Jorg Friedel, Ludwig Schifferl
  • Publication number: 20010005135
    Abstract: In a method for the operation of a magnetic resonance tomography apparatus having a gradient system and a radio-frequency system that, among other things, serve for location coding, a region to be imaged in an examination subject is placed in an imaging volume of the apparatus. Image datasets of at least parts of the region to be imaged are generated in a time sequence. A positional change of at least a part of the region to be imaged with respect to the imaging volume is determined by a comparison of at least a first image dataset to a second image dataset that have been generated in chronological succession. A location coding is adapted corresponding to the identified positional change for at least one image dataset that is generated following the compared image datasets in time.
    Type: Application
    Filed: December 11, 2000
    Publication date: June 28, 2001
    Applicant: Siemens Aktiengesellschaft
    Inventor: Stefan Thesen
  • Publication number: 20010005136
    Abstract: A magnetic resonance imaging receiver/transmitter coil system for providing images for regions of interest includes a first phased array formed of a plurality of electrically conductive members and defining an array volume and a second phased array formed of a second plurality of electrically conductive members and disposed at least partially within the defined array volume. At least one of the first and second phased arrays is adapted to apply a magnetic field to the defined array volume. At least one of the first and second phased arrays is further adapted to receive said applied magnetic field. The first phased array is extendible to define a further array volume and is provided with a switch for electrically coupling and decoupling an extension to effectively extend the length of the first phased array and thereby define the further array volume. In this manner the length of the first phased array is effectively extended to approximately twice its unextended length.
    Type: Application
    Filed: February 2, 2001
    Publication date: June 28, 2001
    Applicant: Medrad, Inc.
    Inventor: George J. Misic
  • Publication number: 20010005137
    Abstract: In a pair of electrodes where a potential difference is changed in accordance with acidity or basicity of oil, a reference electrode is made of cobalt or a cobalt alloy, and a sensitive electrode is made of tungsten or a tungsten alloy. The sensitive electrode is used in combination with the reference electrode. Accordingly, it is possible to provide a pair of electrodes for detecting the acidity or the basicity of the oil which use a novel electrode material not hazardous to the environment and at the same time, suited for use in a semiconductor fabrication technique.
    Type: Application
    Filed: December 14, 2000
    Publication date: June 28, 2001
    Inventors: Kazuyuki Horie, Kiwamu Naito, Hayaki Teramoto, Tatsuhiko Nonoyama, Kazushi Asami, Takahiko Yoshida, Hiroshi Ueda
  • Publication number: 20010005138
    Abstract: An article identification device 4 is mounted on a trap of which operation is diagnosed. The identification device 4 includes a memory 47 in which trap identification data is stored. When the identification device 4 receives an electromagnetic wave from a trap operation diagnosing device, a rectifier 46 derives DC power from the electromagnetic wave, which DC power drives the memory 47 and a modulator 48 so that an electromagnetic wave containing the trap identification data can be sent to the operation diagnosing device. The operation diagnosing device derives the trap identification data from the received electromagnetic wave to identify the trap whose operation the operation diagnosing device diagnoses.
    Type: Application
    Filed: December 11, 2000
    Publication date: June 28, 2001
    Applicant: TLV Company, Limited
    Inventor: Yoshihiko Usaki
  • Publication number: 20010005139
    Abstract: An electrostatic capacitive encoder includes a scale (1) and a sensor head (2), which is arranged opposing to and relatively movable to the scale (1). A plurality of protrusions (24) for sliding, processed in a certain pattern, are located on a flat region surrounding a transmitting electrodes (21) and receiving electrodes (22) of the sensor head (2).
    Type: Application
    Filed: December 26, 2000
    Publication date: June 28, 2001
    Applicant: Mitutoyo Corporation
    Inventors: Satoshi Adachi, Kenichi Nakayama, Akihito Takahashi, Toshihiro Hasegawa, Masaaki Nagata
  • Publication number: 20010005140
    Abstract: A waveform observing jig for observing a waveform of a signal outputted from a predetermined signal terminal, comprises: a contact for a signal, for contacting with a signal terminal of a board to be observed, and a plurality of contacts for a ground, for contacting with a ground pattern of the board to be observed, wherein at least one contact for a ground is in contact with the ground pattern of the board to be observed when the contact for a signal is in contact with a predetermined signal terminal of the board to be observed.
    Type: Application
    Filed: November 29, 2000
    Publication date: June 28, 2001
    Inventor: Takahiro Nagata
  • Publication number: 20010005141
    Abstract: A configuration for testing chips includes a printed circuit board having conductive probe needles to electrically connect the printed circuit board to chips and for testing the chips on the printed circuit board in parallel, some of the probe needles configured as dummy needles for mechanically self-aligning the chips. The board is configured closely to the application such that many chips (1) can be tested simultaneously in parallel. The chips can have markings or depressions to be engaged with free ends of the dummy needles remote from the board. Adapters can be disposed between the probe needles and the chips. Also, the chips can have structures disposed thereon between the probe needles and the chips. The board can have alignment aids for orienting the chips.
    Type: Application
    Filed: December 21, 2000
    Publication date: June 28, 2001
    Inventor: Peter Pochmuller
  • Publication number: 20010005142
    Abstract: The present invention relates to a socket for testing a module, including a contact pin that is an electrical connecting device for mutually connecting a connecting pin of a module to a terminal of a printed circuit board in testing the module and an elastic body for supporting the contact pin.
    Type: Application
    Filed: February 16, 2001
    Publication date: June 28, 2001
    Applicant: WOOYOUNG Co. Ltd.
    Inventor: Sang Hun Lee
  • Publication number: 20010005143
    Abstract: The invention relates to a configuration for the measurement of internal voltages in a DUT (2), in which a comparator (3) is provided in each DUT (2) and compares the internal voltage (Vint) to be measured with an externally supplied reference voltage (Vref).
    Type: Application
    Filed: December 18, 2000
    Publication date: June 28, 2001
    Inventors: Peter Beer, Carsten Ohlhoff
  • Publication number: 20010005144
    Abstract: The configuration allows for testing a multiplicity of semiconductor chips with respect to critical parameters on the wafer level. Each of the semiconductor chips on a semiconductor wafer is additionally provided with at least one option pad. The option pad allows access for a test program to the chip for separating out the semiconductor chips which do not correspond to predetermined requirements for critical parameters.
    Type: Application
    Filed: December 26, 2000
    Publication date: June 28, 2001
    Inventors: Robert Feurle, Dominique Savignac
  • Publication number: 20010005145
    Abstract: A system for testing a microelectronic circuit includes a test bed for mounting a microelectronic circuit, and a signal source for applying a signal to a microelectronic circuit mounted on the test bed. The system additionally includes a test probe for wirelessly receiving electromagnetic response signals from the microelectronic circuit mounted on the test bed. In a preferred form, the electromagnetic response signals are radio-frequency signals. The test system additionally includes a computer connected to be test probe for analyzing the electromagnetic response signals. An integrated circuit for testing on the test system has a test circuit portion that emits electromagnetic radiation in response to a predetermined signal applied to the test circuit.
    Type: Application
    Filed: January 16, 2001
    Publication date: June 28, 2001
    Inventors: Stanley A. White, Kenneth S. Walley, James W. Johnston, P. Michael Henderson, Kelly H. Hale, Warner B. Andrews, Jonathan I. Siann
  • Publication number: 20010005146
    Abstract: A signal transmission system includes a first circuit block having a first output circuit for producing a first signal, a plurality of second circuit blocks each including a first receiving circuit for receiving the first signal, and transmission lines connected between the first circuit block and the second circuit blocks, wherein the first circuit block further includes a second output circuit for producing a second signal, and wherein each of the second circuit blocks further includes a second receiving circuit for receiving the second signal, the first receiving circuit latching the first signal in synchronism with the second signal, removing the unsuccessfulness in the signal transmission and reception due to the propagation delay of signals between circuits.
    Type: Application
    Filed: February 7, 2001
    Publication date: June 28, 2001
    Inventors: Toshitsugu Takekuma, Akira Yamagiwa, Takashi Moriyama, Ryoichi Kurihara
  • Publication number: 20010005147
    Abstract: A semiconductor circuit is composed of an N-channel transistor, a driving circuit, and a charge pump. The N-channel transistor includes a gate and a drain. The drain is provided with a power supply potential. The driving circuit sets a gate potential at the gate to a first potential in response to an input signal. The charge pump raises the gate potential to a second potential higher than the first potential in response to the input signal.
    Type: Application
    Filed: December 27, 2000
    Publication date: June 28, 2001
    Applicant: NEC CORP
    Inventor: Tetsuya Ootsuki
  • Publication number: 20010005148
    Abstract: A semiconductor integrated circuit including a logic circuit is disclosed, in which the decoder area can be reduced and which has an effect of reduction of the whole chip size. Among the MOS FETs included in the logic circuit, those other than a MOS FET for supplying electric charges via an output terminal have threshold voltage values lower than the threshold voltage value of the MOS FET for supplying electric charges. The direction of the gate width of each MOS FET is perpendicular to the direction along which word lines extend in the memory cell areas, and all of the MOS FETs are aligned in a direction perpendicular to the direction along which the word lines extend.
    Type: Application
    Filed: December 19, 2000
    Publication date: June 28, 2001
    Applicant: NEC Corporation
    Inventors: Susumu Takano, Hiroyuki Takahashi, Minoru Nizaka, Tomohiro Kitano
  • Publication number: 20010005149
    Abstract: A read-only sequence controller has a master circuit mounted on a housing and having a first presettable counter for producing an instruction pulse, and a slave circuit having a second presettable counter for setting a cycle, and a pules the generating circuit for producing a plurality of pulses at the cycle in response to the instruction pulse from the master circuit. An EPROM is provided for storing a machine operating program data and for producing a program data in response to the pulses fed from the slave circuit. There is provided a plurality of output relays operated in accordance with the program data fed from the EPROM, and a plurality of terminal connected to the relays. The output terminals are arranged in two rows at one of sides of the housing.
    Type: Application
    Filed: November 30, 2000
    Publication date: June 28, 2001
    Inventor: Yoshikazu Kuze
  • Publication number: 20010005150
    Abstract: This invention features, in part, a latch type sense amplifier which can prevent a mis-operation and increase operation speed by performing a sensing operation twice in one read cycle. There is also provided a method for operating a sense amplifier.
    Type: Application
    Filed: December 26, 2000
    Publication date: June 28, 2001
    Inventor: In Hwan Eum
  • Publication number: 20010005151
    Abstract: Semiconductor circuitry comprises a transistor pair (11, 12) consists of a transistor having a base electrode to which a first signal is applied, and another transistor having a base electrode to which a signal having a phase opposite to that of the first signal is applied, the collector electrodes of those transistors being connected to each other and the emitter electrodes of the transistors being connected to each other, a third transistor (13) connected between a common emitter of the transistor pair and a ground potential and having a base electrode to which a second signal is applied, an output load (51) connected between a common collector of the transistor pair and a power supply (Vcc), and an output circuit for furnishing a third signal from the common collector of the transistor pair, thereby suppressing generation of any even-order higher harmonic of a local oscillation signal when the semiconductor circuitry operates from a low voltage.
    Type: Application
    Filed: February 23, 2001
    Publication date: June 28, 2001
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Noriharu Suematsu, Masayoshi Ono, Tadashi Takagi
  • Publication number: 20010005152
    Abstract: In the initial stage of the operation of turning off a semiconductor device, the impedance of a carrier pull out circuit remains low for rapidly pulling out the stored carriers from the control electrode of the device. When the turn-off transition of the device proceeds and becomes close to its completion, the impedance of the carrier pull out circuit is shifted to a higher level for retarding the carrier pull out speed. A detector is provided for detecting a control current developed by pulling out the carriers. When the current measured by the detector drops down to below a predetermined level, it is judged that the turn-off transition is approaching to its end. This permits the turn-off transition to be smoothly finished and can thus prevent unwanted oscillation of the control electrode voltage.
    Type: Application
    Filed: December 26, 2000
    Publication date: June 28, 2001
    Applicant: NISSAN MOTOR CO., LTD.
    Inventors: Toshiro Karaki, Kraisorn Throngnumchai
  • Publication number: 20010005153
    Abstract: A semiconductor integrated circuit comprises therein a plurality of logic circuits synchronously designed to operate in synchronization with a clock signal, a first power supply wire for supplying a high-potential side power supply voltage from a first input terminal to each logic circuit, a second power supply wire for supplying the high-potential side power supply voltage from a second input terminal to each logic circuit and a third power supply wire for supplying the high-potential side power supply voltage from a third input terminal to each logic circuit. The logic circuit (DFF circuit) includes two stages of latch circuits and a clock signal inversion circuit. Only the clock signal inversion circuit is connected with the first power supply wire, while the second power supply wire is connected with the remaining latch circuits.
    Type: Application
    Filed: December 26, 2000
    Publication date: June 28, 2001
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Yoshitaka Ueda, Isao Ogura
  • Publication number: 20010005154
    Abstract: A self compensating phase detector. Using two identical phase detectors introducing one of the phase detectors and a controlled variable phase shifter in a negative feedback loop shifts one clock signal enough such that the shifted signal compensates for existing static phase error. This self-compensation improves the accuracy of the phase difference measurement by significantly reducing the effect of static phase error. Moreover, this reduction remains true in spite of variations in process, temperature and voltage. Thus, inherent immunity of the invention to environmental conditions results in fewer failing parts during fabrication. Additionally, because the design is self-adjusting to environmental changes, design ease is significantly improved.
    Type: Application
    Filed: February 13, 2001
    Publication date: June 28, 2001
    Inventor: Luke A. Johnson
  • Publication number: 20010005155
    Abstract: This invention relates to an electrical device for generating a multi-rate pseudo random noise (PN) sequence comprising sequence generation means adapted to output a plurality of sequence values on the basis of a step control signal (St), said device further comprising selection means adapted to select one of said plurality of sequence values on the basis of a select value (Mt), and step control means adapted to provide said step control signal (St).
    Type: Application
    Filed: December 20, 2000
    Publication date: June 28, 2001
    Inventor: Ben Smeets
  • Publication number: 20010005156
    Abstract: A data extracting circuit extracts data much more accurately at a much higher response speed. A clock transfer section propagates an input clock signal through unit delay devices thereof. An edge detecting section locates an edge of the clock signal, which edge is being propagated through the clock transfer section, for a time represented by a given edge of an input data signal. In response to an edge detection signal indicating the clock signal edge located, a clock selecting section selects one of outputs of the delay devices, and presents the output as a clock input to a latch.
    Type: Application
    Filed: December 21, 2000
    Publication date: June 28, 2001
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Shiro Dosho
  • Publication number: 20010005157
    Abstract: A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer.
    Type: Application
    Filed: February 12, 2001
    Publication date: June 28, 2001
    Applicant: Fujitsu Limited
    Inventors: Masao Taguchi, Hiroyoshi Tomita, Yasurou Matsuzaki
  • Publication number: 20010005158
    Abstract: A variable delay circuit comprises: a delay compensation unit, which has a plurality of referential delay units that include different numbers of first variable delay elements, the delay amount of which varies based on a control signal, the delay compensation unit generates each of a plurality of the control signals, which are provided to the first variable delay elements, according to a number of the first variable delay elements; and a delay unit which generates the desired delay amount by controlling a plurality of second variable delay elements, which have a same characteristic with the first variable delay elements, by the plurality of control signals.
    Type: Application
    Filed: January 30, 2001
    Publication date: June 28, 2001
    Inventor: Toshiyuki Okayasu
  • Publication number: 20010005159
    Abstract: A voltage generation circuit comprises a capacitor, an n-channel MOS transistor, a p-channel MOS transistor and the like, while the n-channel transistor has a source terminal connected to a node and a drain terminal employed as an output terminal for a negative voltage, the p-channel MOS transistor has a source terminal connected to the aforementioned node and a drain terminal employed as a ground terminal, gate terminals of the n-channel MOS transistor and the p-channel MOS transistor are connected in common, and clock signals inverted in phase to each other are applied to the common node and a first terminal of the capacitor.
    Type: Application
    Filed: December 26, 2000
    Publication date: June 28, 2001
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventor: Shoichiro Matsumoto
  • Publication number: 20010005160
    Abstract: A reference voltage generation circuit includes: a load unit having one end thereof connected to a higher voltage power supply line; an enhancement type n-channel MIS transistor having a drain thereof connected to the other end of the load unit, and a source thereof connected to a lower voltage power supply line; and a source follower circuit using a MIS transistor as a driving element, the source follower circuit having an input end thereof connected to the drain of the n-channel MIS transistor and having an output end thereof connected to a gate of the n-channel MIS transistor. A reference voltage is obtained at the drain of the n-channel MIS transistor. By the constitution, it is possible to obtain a stable reference voltage, and to incorporate the reference voltage generation circuit into an integrated circuit produced by integrating MIS transistors, without introducing an increase in production processes. It is also possible to reduce a consumed current of the reference voltage generation circuit.
    Type: Application
    Filed: December 22, 2000
    Publication date: June 28, 2001
    Applicant: Fujitsu Limited
    Inventor: Masao Taguchi
  • Publication number: 20010005161
    Abstract: A reference voltage source circuit includes a reference voltage generation circuit that inputs external power voltage and produces a first reference voltage with a first temperature characteristic, and a level shifter circuit that produces a second reference voltage with the first temperature characteristic from the first reference voltage and outputs the second reference voltage as a reference voltage. For example, the reference voltage generation circuit may use a circuit configuration that is configurable to produce reference voltage in first and second ranges with respective positive and negative temperature characteristics, and the reference voltage generation circuit is configured to produce the first reference voltage in the first range with a positive temperature characteristic. The level shifter circuit may be operative to provide a voltage drop between the first and second reference voltages such that the second reference voltage is in the second range. Related methods are also discussed.
    Type: Application
    Filed: December 20, 2000
    Publication date: June 28, 2001
    Inventor: Jeon Baek Yeong
  • Publication number: 20010005162
    Abstract: A filter system includes a low pass filter, a first summer circuit, a second low pass filter and a second summer circuit. The first low pass filter includes an input, an output, a storage means, a switching means and a control means. An input signal is placed on the input. An output signal is generated on the output. The storage means provides storage of a signal sample over time. The switching means, when closed, electrically couples the input to the first end of the storage means. The switching means, when open electrically isolates the input from the first end of the storage means. The control means controls the switching means. The control means generates a switching control signal. The switching control signal has a sampling frequency. A maximum cutoff frequency of the low pass filter is dependent on a value of a capacitance provided by the storage means, the sampling frequency, and a pulse width of the switching control signal.
    Type: Application
    Filed: December 18, 2000
    Publication date: June 28, 2001
    Inventor: Rob McCullough
  • Publication number: 20010005163
    Abstract: A semiconductor integrated circuit comprises an amplifier circuit including a current output amplifier, a load resistor having one end connected to an output terminal of the current output amplifier and a voltage control circuit having an input terminal connected to the one end of the load resistor and an output terminal connected to an other end of the load resistor. The input terminal of the amplifier circuit serves as an input terminal of the current output amplifier, and the output terminals of the amplifier circuit serve as the individual ends of the load resistor.
    Type: Application
    Filed: December 19, 2000
    Publication date: June 28, 2001
    Applicant: Semiconductor Technology Academic Research Center
    Inventors: Kazuyuki Wada, Shigetaka Takagi, Nobuo Fujii
  • Publication number: 20010005164
    Abstract: An oscillating clock frequency of a VFO (variable frequency oscillator) is controlled, using the results of addition of an output from a constant multiplier and an output from an accumulator, which is a result of accumulation of outputs from another constant multiplier, based on a phase error signal by setting the output from an enable-provided latch to 0 during a frequency pull-in operation. A control signal generating portion outputs a pulse at the Hi level as a control signal when completion of frequency pull-in is detected. The latch stores the output from the constant multiplier at the time when the control signal is supplied. Thus, a phase pull-in operation is started in the state where a latch output representing a frequency correction component is obtained. During the phase pull-in operation, the VFO is controlled using the result of addition of an output from the multiplier, an output from the accumulator and an output from the latch.
    Type: Application
    Filed: December 12, 2000
    Publication date: June 28, 2001
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kouji Okamoto
  • Publication number: 20010005165
    Abstract: A laminate tile pole piece for an MRI, a method and a mold for manufacturing laminate tile metal pole pieces for an MRI. Each laminate tile has a trapezoidal or annular sector shape. The trapezoidal shape allows the tiles to be attached side by side to form a multiple concentric annular array pole piece without using oddly shaped edge filler tiles needed to fill a circular pole piece with square tiles. The pole piece is made by placing a plurality of tiles into a mold and filling the mold with an adhesive substance to bind the plurality of tiles into a unitary tile body. The unitary tile body is then removed from the mold and attached to a pole piece base to form the pole piece. The mold cavity surface preferably has a non-uniform contour. The bottom surface of the unitary tile body forms a substantially inverse contour of the mold cavity surface contour.
    Type: Application
    Filed: December 18, 2000
    Publication date: June 28, 2001
    Inventors: Evangelos T. Laskaris, William D. Barber, Johannes M. van Oort, Bulent Aksel, Paul S. Thompson, Michele D. Ogle
  • Publication number: 20010005166
    Abstract: This invention relates to the resin encapsulation of solenoids to achieve water resistance at pressure depth. When a compatible and bondable resin is used to form a solenoid bobbin, to insulate the lead-in wires and to encapsulate the solenoid, the resulting encapsulation is effective in resisting water penetration. The formation of bonds between the encapsulation and the solenoid bobbin flanges and insulated lead-in wires allows the encapsulated solenoid to resist water penetration and to operate efficiently in underwater environments.
    Type: Application
    Filed: February 20, 2001
    Publication date: June 28, 2001
    Inventor: Olivier P. Coulombier
  • Publication number: 20010005167
    Abstract: An electronic part in which insulating tape is adhered to lead terminals which extend from an electronic part unit so that a pitch between the terminals can remain stable and constant. The insulating tape is adhered to portions of the lead terminals in a vicinity of the unit from both sides such that the tape is placed with the terminals therebetween.
    Type: Application
    Filed: July 7, 1997
    Publication date: June 28, 2001
    Inventors: TOSHIKAZU NAKAMURA, TAKASHI SHIKAMA
  • Publication number: 20010005168
    Abstract: The installation for the remote monitoring of a park of heterogeneous industrial production apparatuses (18, 22, 26) comprises, for each apparatus (18, 22, 26), means (20A, 20B, 24A, 24B, 32A, 32B) for reading informations relating to the operation of the apparatus. These informations reading means are connected to means (48, 50, 52, 54) for the remote monitoring of the apparatus by communication means 40 associated with the apparatus (18, 22, 26) and adapted for the communication of the data from the apparatus to the remote monitoring means. All the communication means (40) comprise analog means for the structuration of the data in accordance with a unified structure independent of the type of the apparatus and of the read informations. The remote monitoring means comprise at least one monitoring station (48, 50, 52, 54) to the communication means (40) of all of the apparatuses. The or each station comprises means for exploiting the unified structure informations read from one or more apparatuses.
    Type: Application
    Filed: January 25, 2001
    Publication date: June 28, 2001
    Inventors: Laurent Ferenczi, Frederic Barth
  • Publication number: 20010005169
    Abstract: Plural security units are coupled to plural control units through a communication line including transmission and response lines. Each control unit detects data collision on the transmission line to avoid the data collision. Re-transmission interval is independently assigned to each control unit. If the command to or from a security unit in charge of this control unit is received, the control unit rewrites the conditional data of the security unit in accordance with the detected command. The control (security) unit further includes a transmission (response) line monitoring portion, so that bi-directional communication is provided in addition of the response (transmission) line monitoring portion. Address data is classified to provide all unit communication, a group communication, and independent communications.
    Type: Application
    Filed: December 27, 2000
    Publication date: June 28, 2001
    Inventors: Kazuhisa Tsuzuki, Motohiro Misawa, Tooru Toyoda