Abstract: A blended composition for water conservation measures applied to save water at both on-land and open water sites is disclosed as combining with a higher fatty alcohol constituent, alternatively either a slaked lime constituent or, in substitution therefore, an acidified gypsum constituent containing sulfuric acid. The inorganic constituents provide ionic compounds which when contacted by water release certain ions diffusing faster than others, whence a charge-procuring mechanism causing individual particulate aggregations of the composition to repel one another results. An amorphous and unemulsified form for the higher fatty alcohol is suggested as important to mitigation of risks of impairing water infiltration into treated soil.

Abstract: Carbon fiber-filled, thermoplastic resin compositions having improved electrical properties at a given level of carbon fibers are formed from thermoplastic resin and carbon fibers associated into bundles with a binder. The thermoplastic resin and the binder are selected to be incompatible such that the adhesion of the fiber to the resin is poor. An exemplary composition is formed from a thermoplastic polymer selected from among polystyrene, high impact polystyrene, polycarbonate, polybutylene terephthalate, polyethylene terephthalate, polyphenylene ether, polyether imide and blends thereof; and carbon fibers associated into bundles with a polyamide terpolymer binder. The bundles are dispersed within the thermoplastic polymer. The compositions can be used for injection molding of articles for use as components in applications requiring static dissipation and/or EMI shielding. Such articles include electronic devices, dust handling equipment and notebook computer enclosures.

Abstract: An electrochemichromic solution containing novel viologen salts as cathodic materials for the redox pair.

Abstract: A balancing hoist, includes a housing having a chamber accessible from outside. Received in the housing is a piston which is movable by gas pressure in a longitudinal direction and rotates a threaded spindle which projects into the chamber of the housing and carries a nut that securely fixed to the housing. Mounted in fixed rotative engagement to the spindle and movable longitudinally along the spindle is a cable drum on which a load-carrying cable is wound. At least one pawl is provided and configured for rotation in opposition to an elastic restraining force from a radially inward idle position to a radially outward brake position as a result of centrifugal forces, when a rotation speed of the cable drum exceeds a predetermined level, thereby impacting upon a fixed stopper which projects radially inwardly from the housing and slowing down the rotation of the cable drum until it is at rest.

Abstract: A non-volatile memory cell comprises a first well region of a first conductivity type within a second well region of a second conductivity type in a substrate. At least one impurity region of an opposite conductivity type to said first conductivity type is formed in the first well as is a well tap region of said first conductivity type. An isolation gate is formed on the surface of the substrate between said at least one impurity region and said well tap region.

Abstract: With increasing integration density of integrated circuits, the packing density in test regions (kerf structures) located between the integrated circuits cannot be increased substantially, since the majority of the available area is occupied by contact areas. The invention is therefore directed toward a test structure region on a wafer having contact areas for applying voltages and test components between the contact areas. The test structure includes at least two test components that are arranged between two adjacent contact areas. The test components are each connected to the adjacent contact areas so that a voltage can be applied to the test components via the contact areas.

Abstract: The present invention relates to minimizing a leakage current in a floating island portion formed in a thin film transistor. More specifically, the present invention is directed to a thin film transistor including: a source electrode 14 and a drain electrode 15 disposed above an insulating substrate 11 at a predetermined interval; an s-Si film 16 disposed in relation to the source electrode 14 and drain electrode 15; a gate insulating film 17 overlapping the a-Si film 16; and a gate electrode 18 overlapping the gate insulating film 17, in which the a-Si film 16 is disposed between the source electrode 14 and the drain electrode 15 and has a floating island portion 20 above which or beneath which the gate electrode 18 is not formed, and boron ions are implanted into this portion to form a boron-ion-implanted region 19.

Abstract: Substrates suitable to manufacture and products of a thin film semiconductor device are provided, by at first preparing a manufacturing substrate having a characteristic capable of enduring a process for forming a thin film transistor and a product substrate having a characteristic suitable to direct mounting of the thin film transistor in a preparatory step, then applying a bonding step to bond the manufacturing substrate to the product substrate for supporting the product substrate at the back, successively applying a formation step to form at least a thin film transistor to the surface of the product substrate in a state reinforced with the manufacturing substrate and, finally, applying a separation step to separate the manufacturing substrate after use from the product substrate.

Abstract: On a transparent electrically insulating substrate, formed are a scanning line, and a gate electrode of a switching element, further formed are a gate insulating film, a semiconductor layer, an n+-Si layer to be formed into a source electrode and a drain electrode. After the patterning of the foregoing structure, the dielectric film is formed, and the portion corresponding to the contact hole is removed by etching, and photosensitive resin is applied to form the interlayer insulating film. Then, the transparent electrode is extended from the pixel electrode over the switching element, whereon a conversion layer and a gold layer for use in electrode are vapor-deposited. In this structure, an increase in capacitor between the pixel electrode and the signal line can be suppressed by the interlayer insulating film, and the transparent electrode functions as a top gate and release excessive electric charge.

Abstract: In order to obtain a thin-film transistor having high characteristics using a metal element for accelerating the crystallization of silicon, a nickel element is selectively added to the surface of an amorphous silicon film (103) in regions (101) and (102) and regions (108) to (110), and a heat treatment is carried out to grow crystals (horizontal growth) in directions parallel to the substrate as indicated by arrows (104) to (107). At this point, the regions (108) to (110) having a width of 5 &mgr;m or less serve as stopper regions so that horizontal growth starting from the regions (101) and (102) stops there. In this way, the horizontal growth regions can be formed with high controllability. Then a circuit such as a shift register can be constructed with a region having the same crystal growth form.

Abstract: An electro-optical device includes a TFT, a data line, a scanning line, and a pixel electrode, which are provided above a substrate, a semiconductor layer which constitutes the TFT being connected to the pixel electrode through a relay film. A light-shielding conductive film provided between the data line and the relay film is electrically connected to a capacitor electrode which consists of the same film as the scanning line provided between the relay film and the semiconductor layer at a constant potential, thereby forming a storage capacitor between the films. Therefore, in an electro-optical device of a type in which a light-shielding film against incident light is provided above pixel switching TFT, and a light-shielding film against returned light is provided below the TFT, the pixel aperture ratio can be increased, and the storage capacitor can be enlarged.

Abstract: A repairable integrated thin film transistor matrix substrate includes an insulated substrate, and a plurality of parallel gate bus lines and a plurality of accumulated capacitance bus lines formed on the insulated substrate. Each of the accumulated capacitance bus lines extend parallel to and between a pair of the gate bus lines, and has a plurality of auxiliary capacitance electrodes which extend from it. A first insulated film is provided on the gate and accumulated capacitance bus lines and the auxiliary capacitance electrodes. A plurality of operating films are formed on the first insulated film, and on each of the operating films, a corresponding thin film transistors are provided. At least two of the thin film transistors are electrically connected to each of the gate bus lines. Also included is a plurality of parallel drain bus lines which are provided substantially perpendicular to the gate and the accumulated capacitance bus lines on the first insulated film.

Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.

Abstract: A novel use of a solid state light detector with a low impedance substrate is described. Light that enters the substrate after traversing the antireflective layer creates an electron-hole pair. The electrons are collected in a crystalline epitaxial layer that spans the space charge region, or depletion layer. A high electric field accelerates free electrons inside the depletion region. The electrons collide with the lattice to free more holes and electrons resulting from the presence of a n-p junction, or diode. The diode is formed by placing the crystalline layer which has positive doping in close proximity with the electrodes which have negative doping. The continual generation of charge carriers results in avalanche multiplication with a large multiplication coefficient. During the avalanche process, electrons can be collected enabling light detection. A resistive layer is used to quench, or stop, the avalanche process.

Abstract: A steplike offset between a memory cell array region and a peripheral circuit region, which is caused by a capacitor C, is reduced by an insulating film having a thickness substantially equal to the height of the capacitor C. Wiring or interconnection grooves are defined in the neighborhood of the surface of an insulating film whose surface is flattened by a CMP method. Further, connecting holes are defined in lower portions of the bottom faces of the interconnection grooves respectively. Second layer interconnections containing copper are formed within the interconnection grooves, and connecting portions containing copper are formed within the connecting holes. The second layer interconnections and first layer interconnections are connected to each other by the connecting portions whose lengths are shortened. The second layer interconnections and the connecting portions are integrally formed by a damascene method using the CMP method.

Abstract: A transducer module for transmitting and/or receiving light has at least one optical semiconductor which is electrically connected to contacts which are provided on a bottom side of a baseplate. The at least one optical semiconductor is provided such that the light can be transmitted in a transmitting direction away from a top side of the baseplate, and that the light can be received in a receiving direction toward the top side of the baseplate. The contacts are provided through the use of conductor tracks which are electrically insulated from the baseplate and are constructed on a printed circuit board substrate. A method for producing a transducer module is also provided.

Abstract: A multi-layered gate for use in a CMOS or CCD imager formed with a second gate at least partially overlapping it. The multi-layered gate is a complete gate stack having an insulating layer, a conductive layer, an optional silicide layer, and a second insulating layer, and has a second gate formed adjacent to it which has a second conductive layer that extends at least partially over the surface of the multi-layered gate. The multi-layered gate has improved insulation, thereby resulting in fewer shorts between the conductive layers of the two gates. Also disclosed are processes for forming the multi-layered gate and the overlapping gate.

Abstract: There is provided a semiconductor device having a ferroelectric capacitor formed on a semiconductor substrate covered with an insulator film, wherein the ferroelectric capacitor comprises: a bottom electrode formed on the insulator film; a ferroelectric film formed on the bottom electrode; and a top electrode formed on the ferroelectric film. The ferroelectric film has a stacked structure of either of two-layer-ferroelectric film or three-layer-ferroelectric film. The upper ferroelectric film is metallized and prevents hydrogen from diffusing in lower ferroelectric layer. Crystal grains of the stacked ferroelectric films are preferably different.

Abstract: A magnetic memory element has a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer disposed between these ferromagnetic layers. The non-magnetic layer has an electrical characteristic that is changeable depending on an external magnetic field applied to the non-magnetic layer.

Abstract: It is an object of the present invention to provide a ferroelectric capacitor which maintains high ferroelecticity. A silicon oxide layer 2, a lower electrode 12, a ferroelectric layer 8 and an upper electrode 10 are formed on a silicon substrate 2. The lower electrode 12 is formed by an alloy layer made of iridium and platinum. The alloy layer of the lower electrode 12 can be formed under appropriate lattice constant correspond with a kind and composition of the ferroelectric layer 8. So that, a ferroelectric layer having excellent ferroelectricity can be obtained. Also, it is possible to prevent vacancy of oxygen in the ferroelectric layer 8.

Abstract: A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to isolation, to source and to word line. This multi-self-aligned structure, which provides the maximum shrinkage of the cell that is possible, is also disclosed. The multi-self-alignment is accomplished by first defining the floating gate at the same time the trench isolation is formed, and then self-aligning the source to the floating gate by using a nitride layer as a hard mask in place of the traditional polyoxide, and finally forming a polysilicon spacer to align the word line to the floating gate. Furthermore, a thin floating gate is used to form a thin and sharp poly tip through the use of a “smiling effect” to advantage.

Abstract: A semiconductor device and its method of fabrication are provided. The semiconductor device includes a substrate, a patterning stop region, an insulating overlayer, a container region within the insulating overlayer, a charge storage lamina or conductive layer over an interior surface of the container region; a contact region defined by the charge storage lamina or conductive layer; and an electrical contact in the contact region, wherein respective portions of the electrical contact and the charge storage lamina or conductive layer occupy collectively substantially all of the container region. A bit line terminal is coupled to the charge storage lamina through a switching structure.

Abstract: A memory cell for an EEPROM memory is fabricated to provide increased oxide thickness at the edge of the tunnel oxide and under the edges of the polysilicon capacitor plate in order to improve the dielectric integrity of the capacitor structure. In one embodiment using a silicided polysilicon process, the oxide is made thicker at the edge of the tunnel oxide by reoxidizing the silicon at the corner of the polysilicon capacitor plate and the underlying substrate surface by exposing the device to a short duration oxidation step after having deposited a 200 Å to 500 Å thick porous oxide over the device to protect the silicide from excessive exposure to the oxidizing ambient. In another embodiment the tunnel oxide is grown in a window in the gate oxide layer, which is about four times thicker than the tunnel oxide, so that the gate oxide completely surrounds the tunnel oxide, and the polysilicon capacitor plate extends beyond the edge of the tunnel oxide terminating at a point above the gate oxide.

Abstract: A column transistor of a sense amplifier includes an orthogonal matrix of a plurality of sets of four active regions, bit lines and local data lines running perpendicular to each other, with each active region having two bit lines and one local data line connected thereto. Further, the gate electrode is provided with a bent portion, the bent portion positioned over the active region, thereby increasing the effective width of the transistor, which in turn reduces a number of contacts of the column transistor and increases channel width, thereby permitting the column transistors to be arranged in a smaller area and increasing the area available within a cell for forming the sense amplifier. The reduced size of the column transistors also allows increases in design and manufacturing tolerances, particularly in formation of contacts, which is favorable for high density device packing and enhancing the operational performance of the resulting device.

Abstract: A power trench MOS-gated transistor is constructed with a buried gate to source dielectric inside a gate trench region. In the innovative device, a thick oxide (grown or deposited) is used to define the height of the trench walls. A body region is initially formed by selective epitaxial growth and etch back. Source regions are formed also by selective epitaxial growth. The body is finally formed by selective epitaxial growth and etch back. The oxide is removed from the trench, the trench walls are oxidized to form a gate oxide, and doped polysilicon fills the trench to form a gate. By the formation of the source region using the spacer etch, this process simplifies the fabrication of power trench gated devices, and provides for increased contact surface area without increasing device size.

Abstract: A transistor of the integrated MOS type with a high threshold voltage and low multiplication coefficient is formed in a chip that includes a substrate and defining an active area delimited by field oxide regions. The active area partially houses a tub having the same type of conductivity as the substrate and a greater doping level. In particular, the tub occupies a first half of the active area, while a second half of the active area is formed directly by the substrate. A gate region is present above the substrate and is isolated from the substrate by means of a gate oxide layer. The gate region is arranged partially above the second half of the active area and partially above the tub. The transistor also comprises a source region, which is formed in the tub on a first side of the gate region, and a drain region, which is arranged in the second half of the active area, on a second side of the gate region.

Abstract: A semiconductor structure which includes a raised source and a raised drain. The structure also includes a gate located between the source and drains. The gate defines a first gap between the gate and the source and a second gap between the gate and the drain.

Abstract: A method and apparatus of hermetically passivating a semiconductor device includes sealing a lid directly onto a semiconductor substrate. An active device is formed on the surface of the substrate and is surrounded by a substantially planar lid sealing region, which in turn is surrounded by bonding pads. A first layer of solderable material is formed on the lid sealing region. A lid is provided which has a second layer of solderable material in a configuration corresponding to the first layer. A solder is provided between the first layer and second layer of solderable materials. In the preferred embodiment, the solder is formed over the second layer. Heat is provided to hermetically join the lid to the semiconductor device without requiring a conventional package. Preferably the first and second layers are sandwiches of conventionally known solderable materials which can be processed using conventional semiconductor techniques.

Abstract: An isolation structure which protrudes above the semiconductor surface and sidewall spacers which smooth the topography over said isolation structure.

Abstract: A resistive structure integrated in a semiconductor substrate and having a suitably doped polysilicon region that is completely surrounded by a dielectric region so that the resistive structure is isolated electrically from other components jointly integrated in the semiconductor substrate.

Abstract: A trench is formed in an n+ type substrate in a vertical direction from a main surface of the substrate, and a p type layer is deposited in the trench to have a recess portion. An n+ type layer is embedded in the recess portion. Accordingly, the p type layer is formed, as a resistive element, into a U-shape with ends that are ended on the main surface of the substrate. The resistive element has a resistance length corresponding to a path of the U-shape.

Abstract: A bipolar transistor is constructed by a semiconductor substrate having a recessed and rounded surface, a collector region formed in the semiconductor substrate, a base region formed in the semiconductor substrate in contact with the collector region and having a configuration along the recessed and rounded surface, an emitter region formed between the recessed and round surface and the base region, and a graft base region formed in the semiconductor substrate in contact with the base region at an outer portion of the recessed and rounded surface.

Abstract: A process for pattern forming during semiconductor manufacturing comprises the steps of forming a resist pattern on a substrate, then a metallic layer, of aluminum for example, is applied to the complete surface of the substrate and the resist pattern, by spattering or the like. Next a heating step is carried out. The heating step is accomplished by immersing the resist pattern in a solvent heated in the vicinity of a boiling point thereof, for effecting expansion of the resist pattern. Then the resist pattern is removed along with undesired remnants of the metallic layer which are adhered to the resist pattern.

Abstract: A semiconductor device equipped with the dual damascene structure that is provided, which suppresses the propagation delay of signals effectively without using any complicated processes.

Abstract: A planar slice (1) of semiconductor substrate material of a first conductivity type is provided on one face with a first region (13a) of a second conductivity type having a higher dopant concentration than that of the substrate and on the opposite face a second region (13b) of said second conductivity type having a higher dopant concentration than that of the substrate. Each of the faces has had removed from part of it a depth of material which increases gradually as the outer edge is approached so that the junction between each of the regions (13a, 13b) and the substrate is exposed along a path following the shape of the perimeter of the slice but so that the removal of material ceases at a distance outwardly beyond the exposure of the junction to leave a rim (11) of the original planar faces of the slice at its perimeter.

Abstract: A housing accommodating a semiconductor chip is set out. The housing and chip may be used for sending and/or receiving radiation. Popular applications of the housing may be in light emitting diodes. The housing includes a conductor strip that is punched into two electrically isolated portions. The housing further includes a cavity extending inwards from the top of the housing. The conductor portions include respective areas that are exposed at the bottom of the cavity. The semiconductor chip is bonded to one of the exposed areas and a wire bonds the chip to the second exposed area. The conductor portions also terminate in exposed electrodes, which allow for electrical connection of the chip with external devices. A window is formed in the cavity and the walls of the housing that form the cavity may be made of a reflective material. The electrodes remain unexposed to the window but for any residual areas about the chip and bonding wire within the first and second exposed areas.

Abstract: A substrate for a semiconductor device is provided, which prevents a semiconductor element or IC chip mounted thereon from being broken or damaged electrostatically in a fabrication process sequence or a semiconductor device.

Abstract: A circuitized substrate having plated through-holes wherein the plated through-holes are tented with a polyimide material is provided along with the process for fabricating such.

Abstract: A vertically mountable semiconductor device including at least one bond pad disposed on an edge thereof. The bond pad includes a conductive bump disposed thereon. The semiconductor device may also include a protective overcoat layer. The present invention also includes a method of fabricating the semiconductor device, including forming disconnected notches in a semiconductor wafer, redirecting circuit traces into each of the notches, and singulating the semiconductor wafer along the notches to form bond pads on the edges of the resultant semiconductor devices. A method of attaching the semiconductor device to a carrier substrate includes orienting the semiconductor device such that the bond pad is aligned with a corresponding terminal of the carrier substrate, and establishing an electrical connection between the bond pad and the terminal.

Abstract: An information card includes a ground plate that is connected to a ground conductor portion of a printed substrate and is integral with an external panel. Plural contacts are provided with the ground plate, and are exposed at the upper side out of windows provided in the external panel. Lead terminals are extended from the ground plate and are integral therewith, and the tips of the lead terminals are soldered to the ground conductor portion of the printed substrate.

Abstract: A first electronic device, a second electronic device which generates less heat than the first electric device, and an electrode are connected by a heat leveling plate formed of an electrically conductive material having high thermal conductivity. A heat radiation plate is provided below an insulated substrate to which the first and second electronic devices are mounted. The second electronic device is cooled by a heat radiation path which extends through the insulated substrate and the heat radiation plate and a heat radiation path which extends through the second electronic device and the electrode to the heat radiation plate. The first and the second electronic device have substantially the same temperature due to heat radiation through the heat leveling plate. As a result, cooling effect of the electronic devices can be enhanced.

Abstract: A packaged semiconductor chip including the chip, and a package element such as a heat sink is made by connecting flexible leads between contacts on the chip and terminals on a dielectric element such as a sheet or plate and moving the sheet or plate away from the chip, and injecting a liquid material to form a compliant layer filling the space between the package element and the dielectric element, and surrounding the leads. The dielectric element and package element extend outwardly beyond the edges of the chip, and physically protect the chip. The assembly may be handled and mounted by conventional surface mounting techniques. The assembly may include additional circuit elements such as capacitors used in conjunction with the chip.

Abstract: The present invention provides a hybrid chip package that utilizes a high-speed BGA structure and a plurality of flexible and reliable QFP leads. More specifically, the QFP leads are attached to a peripheral region of a substrate to surround the attached BGA structure and replace solder bumps of a conventional BGA structure that would typically flack or crack during operational cycles to create an electrical open between the conventional BGA package and the attached printed circuit board.

Abstract: Metal and insulator interconnect structures are described incorporating one or more layers of fluorinated dielectric insulation, one or more conductive wiring levels interconnected by vias and capping and/or liner materials to physically isolate the wiring levels and vias from the fluorinated dielectric such as fluorinated diamond like carbon which has a low dielectric constant. The invention overcomes the problem that can arise when fluorine in the fluorinated dielectric insulation reacts with other materials in the interconnect structure to produce unwanted fluorine-containing compounds that can interfere with the structure's mechanical integrity or interconnect function.

Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

Abstract: A wiring structure in a semiconductor device includes a substrate; a first conductive layer on the substrate; a second conductive layer covering a portion of the first conductive layer, wherein another portion of the first conductive layer is not covered by the second conductive layer; an insulation layer on the first and second conductive layer; a penetrating part passing through the insulation layer from the uncovered portion of the first conductive layer; and a third conductive layer on the insulation layer, the third conductive layer connecting the penetrating part.

Abstract: An object of the present invention is to provide a solid-state image pickup apparatus capable of reducing man-hours for bonding, improving bonding quality, and being readily integrated into peripheral devices, and a manufacturing method thereof. The solid-state image pickup apparatus of the present invention includes a transparent substrate having a projecting electrode connection electrode terminal, and a solid-state image pickup device in which each first projecting electrode corresponding to the projecting electrode connection electrode terminal is formed on each electric signal I/O terminal, the transparent substrate and the solid-state image pickup device being bonded by face-down packaging. The projecting electrode connection electrode terminal and each first projecting electrode are connected by ultrasonic bonding. On electrode terminals of the transparent substrate are respectively formed second projecting electrodes.

Abstract: An input-output circuit cell includes an input-output circuit formed on a semiconductor chip and having a signal terminal and an electric source terminal and a plurality of input-output bumps connected to the signal and electric-source terminals of the input-output circuit through wirings respectively, the plurality of input-output bumps being made to correspond to the input-output circuit and arranged at a center in a plane of projection of the input-output circuit. Accordingly, the input-output circuit is disposed in an arbitrary position on the semiconductor chip.

Abstract: An bonding pad structure has a passivation layer over a copper layer having a pad window to expose a portion of the copper layer, a barrier layer conformal to a profile of the pad window, and an aluminum pad located in the pad window. The metal layer can be an aluminum, aluminum alloy or aluminum dominated layer for providing a better adhesion property between the copper layer and the bonding wire.

Abstract: The present invention aims at an improvement in temperature-cycle resistance after packaging in semiconductor devices and also an improvement in moisture-absorbed reflow resistance, and provides an adhesive having a storage elastic modulus at 25° C. of from 10 to 2,000 MPa and a storage elastic modulus at 260° C. of from 3 to 50 MPa as measured with a dynamic viscoelastic spectrometer, and also a double-sided adhesive film, a semiconductor device and a semiconductor chip mounting substrate which make use of the adhesive, and their production process.