With Contact With An Immiscible Liquid (e.g., Lec) Patents (Class 117/17)
  • Patent number: 11346016
    Abstract: A method of growing a doped monocrystalline ingot using a crystal growing system is provided. The crystal growing system includes a growth chamber, a dopant feeding device, and a feed tube. The method includes preparing a melt of semiconductor or solar-grade material in a crucible disposed within the growth chamber, introducing a solid dopant into the feed tube with the dopant feeding device, melting the solid dopant within the feed tube to a form a liquid dopant, introducing the liquid dopant into the melt below a surface of the melt, and growing a monocrystalline ingot from the melt by contacting the melt with a seed crystal and pulling the seed crystal away from the melt.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: May 31, 2022
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Stephan Haringer, Marco D'Angella, Mauro Diodà
  • Patent number: 9809900
    Abstract: A growth chamber or a Czochralski crystal growth station has one or more re-sealable caps that are inserted into the chamber body. An O-ring seals the cap within its mating portion of the chamber body. The re-sealable caps facilitate re-use of the chamber body for a future crystal growth cycle.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: November 7, 2017
    Assignee: Siemens Medical Solutions USA, Inc.
    Inventors: Mark S. Andreaco, Troy Marlar, Brant Quinton
  • Patent number: 9719187
    Abstract: A method for producing the growth of a semiconductor material, in particular of type II-VI, uses a melt of the semiconductor placed in a sealed bulb under vacuum or under controlled atmosphere, the bulb being subjected to a sufficient temperature gradient for first maintaining the melt in the liquid state, then causing its progressive crystallization from the surface towards the bottom. The method further comprises an element capable of floating on the surface of the melt, and equipped with a substantially central bore, intended for receiving a seed crystal for permitting the nucleation leading to the preparation of a seed crystal, and also supporting the seed crystal above the melt while maintaining it in contact with the melt in order to permit the continued crystallization from the seed crystal by lowering the temperature gradient.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: August 1, 2017
    Assignee: SOCIETE FRANCAISE DE DETECTEURS INFRAROUGES-SOFRADIR
    Inventor: Sylvain Paltrier
  • Patent number: 9362268
    Abstract: In a high-frequency circuit, it is necessary to provide galvanic blocking between active elements such as transistors and between an active element and an external terminal, and thus MIM capacitors or the like are used frequently. A MIM capacitor coupled to an external terminal is easily affected by static electricity from outside and causes a problem of electro-static breakdown or the like. In a MIM capacitor formed over a semi-insulating compound semiconductor substrate, a first electrode thereof is coupled to an external pad and to the semi-insulating compound semiconductor substrate, and a second electrode thereof is coupled to the semi-insulating compound semiconductor substrate.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: June 7, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Atsushi Kurokawa, Shinya Osakabe
  • Patent number: 9133050
    Abstract: Glass bodies and methods of making glass bodies and more particularly glass bodies, for example, microlenses and arrays of microlenses and methods of making the same are described. Cordierite powder is vitrified to form a glass body or glass bodies for instance a microlens or microlenses.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: September 15, 2015
    Assignee: CORNING INCORPORATED
    Inventors: Vitor Marino Schneider, Changyi Lai
  • Patent number: 9023152
    Abstract: A solution-stirring top-seeded solution-growth method for forming CLBO of the type where water is added to a precursor mixture, where heavy water is substituted for the water.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: May 5, 2015
    Assignee: KLA-Tencor Corporation
    Inventor: Vladimir L. Dribinski
  • Patent number: 8926749
    Abstract: A method for recharging a crucible with polycrystalline silicon comprises adding flowable chips to a crucible used in a Czochralski-type process. Flowable chips are polycrystalline silicon particles made from polycrystalline silicon prepared by a chemical vapor deposition process, and flowable chips have a controlled particle size distribution, generally nonspherical morphology, low levels of bulk impurities, and low levels of surface impurities. Flowable chips can be added to the crucible using conventional feeder equipment, such as vibration feeder systems and canister feeder systems.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: January 6, 2015
    Assignee: Hemlock Semi Conductor
    Inventors: Arvid Neil Arvidson, Terence Lee Horstman, Michael John Molnar, Chris Tim Schmidt, Roger Dale Spencer, Jr.
  • Patent number: 8758505
    Abstract: A method for manufacturing a silicon wafer includes a step of annealing a silicon wafer which is sliced from a silicon single crystal ingot, thereby forming a DZ layer in a first surface and in a second surface of the silicon wafer and a step of removing either a portion of the DZ layer in the first surface or a portion of the DZ layer in the second surface.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: June 24, 2014
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Toshiaki Ono, Wataru Sugimura, Masataka Hourai
  • Patent number: 8741059
    Abstract: According to the present invention, there is provided a single-crystal manufacturing apparatus based on Czochralski method, comprising at least: a main chamber configured to accommodate hot zone components including a crucible; and a pull chamber configured to accommodate and take out a single crystal pulled from a raw material melt contained in the crucible, wherein the apparatus further comprises: a cooling pipe which is arranged above the crucible and in which a cooling medium is circulated; and a moving mechanism that moves up and down the cooling pipe, and the hot zone components are cooled down by utilizing the moving mechanism to move down the cooling pipe toward the crucible after growth of the single crystal, and a method for manufacturing a single crystal is also provided.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: June 3, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Takao Abe
  • Patent number: 8696813
    Abstract: Leakage of silicon melt is monitored and touch of a seed crystal at the silicon melt is detected, and in addition, reinforcement of a vitreous silica crucible to be endurable during pulling for a long time and decrease of impurity concentration of a silicon single crystal can be expected. A method for manufacturing a silicon single crystal is provided.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: April 15, 2014
    Assignee: Japan Super Quartz Corporation
    Inventors: Masanori Fukui, Hideki Watanabe, Nobumitsu Takase
  • Patent number: 8398765
    Abstract: A system for growing silicon crystals that facilitates controlling a shape of a melt-solid interface is described. The crystal growing system includes a heated crucible including a semiconductor melt from which a monocrystalline ingot is grown according to a Czochralski process. The ingot is grown on a seed crystal pulled from the melt. The method includes applying an unbalanced cusped magnetic field to the melt, and rotating the ingot and the crucible in the same direction while the ingot is being pulled from the melt.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: March 19, 2013
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Hariprasad Sreedharamurthy, Milind Kulkarni, Richard G. Schrenker, Joseph C. Holzer, Harold W. Korb
  • Patent number: 8361222
    Abstract: In the production of GaN through the flux method, deposition of miscellaneous crystals on the nitrogen-face of a GaN self-standing substrate and waste of raw materials are prevented. Four arrangements of crucibles and a GaN self-standing substrate are exemplified. In FIG. 1A, a nitrogen-face of a self-standing substrate comes into close contact with a sloped flat inner wall of a crucible. In FIG. 1B, a nitrogen-face of a self-standing substrate comes into close contact with a horizontally facing flat inner wall of a crucible, and the substrate is fixed by means of a jig. In FIG. 1C, a jig is provided on a flat bottom of a crucible, and two GaN self-standing substrates are fixed by means of the jig so that the nitrogen-faces of the substrates come into close contact with each other. In FIG. 1D, a jig is provided on a flat bottom of a crucible, and a GaN self-standing substrate is fixed on the jig so that the nitrogen-face of the substrate is covered with the jig.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: January 29, 2013
    Assignees: Toyoda Gosei Co., Ltd., NGK Insulators, Ltd.
    Inventors: Shiro Yamazaki, Seiji Nagai, Takayuki Sato, Katsuhiro Imai, Makoto Iwai, Takatomo Sasaki, Yusuke Mori, Fumio Kawamura
  • Patent number: 8293008
    Abstract: The present invention relates to a large-sized and high-quality bismuth-zinc-borate (Bi.sub.2 ZnB.sub.2 O.sub.7) single crystal, preparation methods and applications thereof. The crystal has cross-sectional dimensions greater than one centimeter, a nonlinear optical effect of about 3-4 times that of KH.sub.2 PO.sub.4 (KDP), and an optical transmission wavelength range of 330-3300 nm. The crystal can be grown from a compound melt by a Czochralski method, a Kyropoulos method or a Bridgman method with the raw material being the synthetic compound Bi.sub.2 ZnB.sub.2 O.sub.7. Alternatively, the crystal may be grown from a high-temperature solution method by using Bi.sub.2 O.sub.3 as a flux. The crystal may be applied in nonlinear optical devices such as frequency doubling generators, frequency upconverters or downconverters, and optical parametric oscillators.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: October 23, 2012
    Assignee: Xingjiang Technical Institute of Physics & Chemistry, Chinese Academy of Sciences
    Inventors: Shilie Pan, Feng Li, Xueling Hou
  • Patent number: 8246744
    Abstract: By specifying an initial oxygen concentration in a silicon single crystal and a concentration of thermal donors produced according to a thermal history from 400° C. to 550° C. that the silicon single crystal undergoes during crystal growth, a nucleation rate of oxygen precipitates produced in the silicon single crystal while the silicon single crystal is subjected to a heat treatment is determined. Further, by specifying the heat treatment condition of the silicon single crystal, an oxygen precipitate density and an amount of precipitated oxygen under a given heat treatment condition are predicted by calculation.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: August 21, 2012
    Assignee: Komatsu Denshi Kinzoku Kabushiki Kaisha
    Inventors: Kozo Nakamura, Junsuke Tomioka, Tetsuro Akagi, Shiro Yoshino
  • Patent number: 8236104
    Abstract: A single-crystal manufacturing apparatus comprising at least: a main chamber configured to accommodate a crucible; a pulling chamber continuously provided above the main chamber, the pulling chamber into which a grown single crystal is pulled and accommodated; a gas inlet provided in the pulling chamber; a gas flow-guide cylinder downwardly extending from a ceiling of the main chamber; and a heat-insulating ring upwardly extending from a lower end portion of the gas flow-guide cylinder with a diameter of the heat-insulating ring increased so as to surround an outside of the gas flow-guide cylinder, wherein at least one window is provided in a region between 50 and 200 mm from a lower end of the gas flow-guide cylinder, and an opening area of the window accounts for 50% or more of a surface area of the region between 50 and 200 mm from the lower end of the gas flow-guide cylinder.
    Type: Grant
    Filed: May 8, 2009
    Date of Patent: August 7, 2012
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Satoshi Soeta, Toshifumi Fujii
  • Patent number: 8114218
    Abstract: A single crystal pull apparatus has a multilayer crucible wherein the crucible has an outer crucible, an insertable layer intimately fitted thereon, and a wire frame positioned between the insertable layer and an inner crucible. The insertable layer, wire frame and inner crucible are preferably composed of platinum. Furthermore the insertable layers have thin walls and the frame has a small diameter such that they can be easily reshaped after any deformation occurring as a result of the single crystal growth process.
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: February 14, 2012
    Assignee: Siemens Medical Solutions USA, Inc.
    Inventors: Olexy V. Radkevich, Keith Ritter
  • Patent number: 7875116
    Abstract: A method in which SSDs are reliably reduced while reducing void defects other than the SSDs on a wafer surface, which is essential for an annealed wafer, and ensuring that BMDs serving as gettering source in a bulk are generated, in order to stabilize the quality of the annealed wafer. Considering that annealing a silicon wafer leads to an increase of density (quantity) of deposits associated with oxygen and nitrogen and forming a core of the SSDs, SSDs are decreased by reducing the density (quantity) of the deposits associated with oxygen and nitrogen by controlling three parameters of oxygen concentration, nitrogen concentration and cooling concentration during the process of pulling and growing the silicon single crystal 6 before annealing. Alternatively, SSD is reduced by polishing after annealing.
    Type: Grant
    Filed: February 14, 2006
    Date of Patent: January 25, 2011
    Assignee: Sumco Techxiv Corporation
    Inventors: Shinya Sadohara, Ryota Suewaka, Shiro Yoshino, Kozo Nakamura, Yutaka Shiraishi, Syunji Nonaka
  • Patent number: 7708831
    Abstract: A method for producing a ZnO single crystal by a liquid phase growth technique, comprising the steps of: mixing and melting ZnO as a solute and PbF2 and PbO as solvents; and putting a seed crystal or substrate into direct contact with the obtained melted solution, thereby growing a ZnO single crystal on the seed crystal or substrate.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: May 4, 2010
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Hideyuki Sekiwa, Jun Kobayashi, Miyuki Miyamoto
  • Patent number: 7648576
    Abstract: After cleaning the front and back sides of a silicon wafer with a liquid SC-1 and liquid SC-2, the front and back sides of the silicon wafer are cleaned with an HF solution to be water-repellent surfaces. Following that, an epitaxial layer of silicon is formed on the front side. Consequently, there can be reduced stacking faults after formation of the epitaxial layer and occurrence of cloud on the back side. Alternatively, the front and back sides of a silicon wafer are cleaned with the liquid SC-1 and liquid SC-2, and then the back side of the silicon wafer is cleaned with an HF solution to be a water-repellent surface while the front side is cleaned with purified water to be a hydrophilic surf ace. Following that, an epitaxial layer of silicon is formed on the front side. Consequently, there can be reduced mounds on the front side and occurrence of cloud on the back side.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: January 19, 2010
    Assignee: SUMCO Corporation
    Inventors: Yasuo Fukuda, Makoto Takemura, Koichi Okuda
  • Patent number: 7537657
    Abstract: A process for producing a single-crystal silicon wafer, comprises the following steps: producing a layer on the front surface of the silicon wafer by epitaxial deposition or production of a layer whose electrical resistance differs from the electrical resistance of the remainder of the silicon wafer on the front surface of the silicon wafer, or production of an external getter layer on the back surface of the silicon wafer, and heat treating the silicon wafer at a temperature which is selected to be such that an inequality (1) [ Oi ] < [ Oi ] eq ? ( T ) ? exp ? 2 ? ? SiO ? ? 2 ? ? rkT is satisfied, where [Oi] is an oxygen concentration in the silicon wafer, [Oi]eq(T) is a limit solubility of oxygen in silicon at a temperature T, ?SiO2 is the surface energy of silicon dioxide, ? is a volume of a precipitated oxygen atom, r is a mean COP and k the Boltzmann constant, with the silicon wafer, during the heat treatment, at least part of the time being exposed to an oxygen-con
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: May 26, 2009
    Assignee: Siltronic AG
    Inventors: Christoph Seuring, Robert Hoelzl, Reinhold Wahlich, Wilfried Von Ammon
  • Patent number: 7442251
    Abstract: This method for producing silicon single crystals includes: growing a silicon single crystal by the Czochralski method while cooling at least part of the silicon single crystal under growth with a cooling member which circumferentially surrounds the silicon single crystal and has an inner contour that is coaxial with a pull axis, wherein an ambient gas in which the silicon single crystal is grown includes a hydrogen-atom-containing substance in gaseous form. This silicon single crystal is produced by the above method.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: October 28, 2008
    Assignee: Sumco Corporation
    Inventors: Shuichi Inami, Hiroki Murakami, Nobumitsu Takase, Ken Hamada, Tsuyoshi Nakamura
  • Patent number: 7318916
    Abstract: A semiconductive GaAs wafer has a diameter of 4 inches or more, and an in-wafer plane dislocation density of 30,000/cm2 or more and 100,000/cm2 or less. A semiconductive GaAs wafer is made by growing a GaAs single crystal under a temperature gradient of 20° C./cm or more and 150° C./cm or less formed in the crystal so that the semiconductive GaAs wafer has an in-wafer plane dislocation density of 30,000/cm2 or more and 100,000/cm2 or less.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: January 15, 2008
    Assignee: Hitachi Cable, Ltd.
    Inventors: Shinji Yabuki, Michinori Wachi, Kouji Daihou
  • Patent number: 7235863
    Abstract: A process for producing a single-crystal silicon wafer, comprises the following steps: producing a layer on the front surface of the silicon wafer by epitaxial deposition or production of a layer whose electrical resistance differs from the electrical resistance of the remainder of the silicon wafer on the front surface of the silicon wafer, or production of an external getter layer on the back surface of the silicon wafer, and heat treating the silicon wafer at a temperature which is selected to be such that an inequality (1) [ O ? ? i ] < [ O ? ? i ] eq ? ( T ) ? exp ? ? 2 ? ? SiO ? 2 ? ? r ? ? k ? ? T is satisfied, where [Oi] is an oxygen concentration in the silicon wafer, [Oi]eq(T) is a limit solubility of oxygen in silicon at a temperature T, ?SiO2 is the surface energy of silicon dioxide, ? is a volume of a precipitated oxygen atom, r is a mean COP radius and k the Boltzmann constant, with the silicon wafer, during the heat treatment, at least pa
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: June 26, 2007
    Assignee: Siltronic AG
    Inventors: Christoph Seuring, Robert Hölzl, Reinhold Wahlich, Wilfried Von Ammon
  • Patent number: 7229494
    Abstract: A method for producing a compound semiconductor single crystal by a liquid encapsulated Czochralski method, including containing a semiconductor raw material and an encapsulating material in a raw material melt-containing portion having a first crucible having a bottom and a cylindrical shape and a second crucible disposed within the first crucible and having a communication hole communicating with the first crucible in a bottom portion thereof; melting the raw material by heating the raw material melt-containing portion; and growing a crystal by making a seed crystal contact with a surface of the raw material melt in a state covered with the encapsulating material and by pulling up the seed crystal. A heater temperature is controlled so that a diameter of a growing crystal becomes approximately equal to an inner diameter of the second crucible, and the crystal is grown by maintaining a surface of the growing crystal in a state covered with the encapsulating material until termination of crystal growth.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: June 12, 2007
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Toshiaki Asahi, Kenji Sato, Atsutoshi Arakawa
  • Patent number: 7195669
    Abstract: A silicon single crystal rod (24) is pulled from a silicon melt (13) made molten by a heater (17), and a change in diameter of the silicon single crystal rod every predetermined time is fed back to a pulling speed of the silicon single crystal rod and a temperature of the heater, thereby controlling a diameter of the silicon single crystal rod. A PID control in which a PID constant is changed on a plurality of stages is applied to a method which controls the pulling speed of the silicon single crystal rod so that the silicon single crystal rod has a target diameter and a method which controls a heater temperature so that the silicon single crystal rod has the target temperature. A set pulling speed for the silicon single crystal rod is set so that V/G becomes constant, and an actual pulling speed is accurately controlled so as to match with the set pulling speed, thereby suppressing a fluctuation in diameter of the single crystal rod.
    Type: Grant
    Filed: July 7, 2003
    Date of Patent: March 27, 2007
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Daisuke Wakabayashi, Masao Saito, Satoshi Sato, Jun Furukawa, Kounosuke Kitamura
  • Patent number: 7122082
    Abstract: A silicon wafer wherein stacking fault (SF) nuclei are distributed throughout the entire in-plane direction, and the density of the stacking fault nuclei is set to a range of between 0.5×108 cm?3 and 1×1011 cm?3.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: October 17, 2006
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Takaaki Shiota, Yoshinobu Nakada
  • Patent number: 6849119
    Abstract: A process for heat-treating a single crystal silicon wafer to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step. The wafer has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the wafer is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The wafer is then cooled from the temperature of said heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a wafer having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the wafer.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: February 1, 2005
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Robert J. Falster, Marco Cornara, Daniela Gambaro, Massimiliano Olmo
  • Patent number: 6800132
    Abstract: A method for producing a silicon ingot through pulling up a silicon single crystal according to the Czochralski method, wherein the silicon single crystal is pulled up while being doped with nitrogen in such a condition as to form a part having a nitrogen content of 5×1013 atoms/cm3 to 1×1015 atoms/cm3. A silicon wafer having a nitrogen content of 5×1013 atoms/cm3 to 1×1015 atoms/cm3 which is suitable for being treated with heat in a non-oxidizing atmosphere is manufactured of an ingot produced by using the method. The method can be used for producing a silicon wafer being doped with nitrogen and having satisfactory characteristics for use in a semiconductor device.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: October 5, 2004
    Assignee: Komatsu Denshi Sinzoku Kabushiki
    Inventors: Satoshi Komiya, Shiro Yoshino, Masayoshi Danbata, Kouichirou Hayashida
  • Patent number: 6752976
    Abstract: By using an InP single crystal substrate of the present invention in which the oxygen atom concentration is within the range of 1×1017 to 1×1018 atoms/cm3 for vapor phase epitaxial growth such as the MOCVD method, the occurrence of protrusions referred to as hillocks on the surface of the epitaxial layer formed on the substrate can be reduced, thereby allowing the providing of an InP single crystal substrate able to accommodate reduced thickness, multi-layering and enhanced function of the epitaxial layer.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: June 22, 2004
    Assignee: Showa Denko K.K.
    Inventor: Koji Iwasaki
  • Patent number: 6312517
    Abstract: A method of lowering the resistivity of resultant silicon crystal from a Czochralski crystal growing process by adding arsenic dopant to the melt in multiple stages.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: November 6, 2001
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Mohsen Banan, Milind Kulkarni, Charles Whitmer, II
  • Patent number: 6019841
    Abstract: The invention is an improved method and apparatus for growing crystals that incorporates an isolation valve between the growth and injection chambers to allow the growth chamber to be maintained at operating temperature and pressure while decoupling the injector chamber in order to make changes necessary to restart or advance the process. Separate heating elements in the injector assembly or chamber provide related heating control. Upper and lower load cells and programmable signal amplifiers are configured to weigh and output the dynamic weight range of the loss or gain of process materials of the growth chamber crucible and the injector assembly, and are connected by electrical slip rings or wireless means to a computer control system.
    Type: Grant
    Filed: March 24, 1998
    Date of Patent: February 1, 2000
    Assignee: G.T. Equuipment Technologies Inc.
    Inventors: Ijaz H. Jafri, Mohan Chandra, Rick C. White, Kedar P. Gupta, Robert B. Farmer, Bernard D. Jones, David F. Bliss
  • Patent number: 5986288
    Abstract: An epitaxial wafer for a light-emitting diode includes an n-type GaP single-crystal substrate, and at least an n-type semiconductor epitaxial layer and a p-type semiconductor epitaxial layer formed on the substrate. The substrate has a boron concentration of not more than 1.times.10.sup.17 cm.sup.-3. A light-emitting diode is fabricated using the epitaxial wafer thus formed provided with electrodes.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: November 16, 1999
    Assignee: Showa Denko K.K.
    Inventor: Koichi Hasegawa
  • Patent number: 5814148
    Abstract: A process for preparing a molten silicon melt from polycrystalline silicon for use in producing single crystal silicon by the Czochralski method is disclosed. Granular and chunk polycrystalline silicon are loaded into a Czochralski crucible as a mixed charge. Preferably, the granular polycrystalline silicon is loaded onto the bottom, mounded toward the centerline of the crucible, and not contacting the upper portion of the wall of the crucible. The chunk polycrystalline silicon is loaded onto the granular polycrystalline silicon. The granular polycrystalline silicon and chunk polycrystalline silicon are melted to form a silicon melt, preferably by heating the polycrystalline silicon from the bottom up such that a substantial portion of the granular polycrystalline silicon is melted before a substantial portion of the chunk polycrystalline silicon is melted.
    Type: Grant
    Filed: February 1, 1996
    Date of Patent: September 29, 1998
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Kyong-Min Kim, Leon A. Allen
  • Patent number: 5733805
    Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements inthe wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4.times.10.sup.-5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1.times.10.sup.16 cm.sup.-3, whereby the characteristics of semiconductor elements whose parent matrial is the GaAs single crystal can be made uniform.
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: March 31, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihisa Fujisaki, Yukio Takano, Tsutomu Ishiba
  • Patent number: 5567505
    Abstract: Means for applying a plastic finishing layer to the surface of a composite article comprising an extruded plastic-based solid body reinforced by one or more bundles of reinforcing fibers, these bundles being affixed to its surface, comprising a ring (1), the entry diameter (2) of which is greater than its exit diameter (3), the internal surface (4) of the said ring furthermore providing a decreasing variation in the internal diameter between its entry and its exit; method of applying a finishing layer, in which method these means are used, and coated composite article.
    Type: Grant
    Filed: August 14, 1995
    Date of Patent: October 22, 1996
    Assignee: Solvay (Soci et e Anonyme)
    Inventors: Claude Dehennau, Serge Dupont
  • Patent number: 5524571
    Abstract: Herein disclosed are apparatuses for manufacturing compound semiconductor polycrystals comprising a pressure vessel, an upper shaft, a container for a first component fixed to the upper shaft, a heater around the container, a lower shaft, a susceptor and a crucible for charging a second component, a heater for the crucible and a communicating pipe for spatially connecting the container and the crucible optionally provided with a porous member at the lower extremity and/or a cylindrical member for confining a space over a part of the melt surface contained in the crucible from the remaining inner space of the vessel, the apparatuses permitting the substantial reduction of the reaction time and an improvement of the yield of the polycrystals due to the presence of the porous member and/or the cylindrical member separating the inner space of the vessel into two portions.
    Type: Grant
    Filed: February 9, 1990
    Date of Patent: June 11, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Akihisa Kawasaki, Toshihiro Kotani
  • Patent number: 5515810
    Abstract: To manufacture a low-carbon concentration GaAs wafer required for devices such as hall sensors, FETs, HEMTs etc. at a high production yield without deteriorating the semi-insulation characteristics thereof, a method of manufacturing a semi-insulation GaAs monocrystal by controlling carbon concentration during crystal growth by a simple method is disclosed. The method of manufacturing a semi-insulation GaAs monocrystal in accordance with liquid encapsulated Czochralski method, comprises the steps of: preparing a crucible (5) formed with a crucible body (6) and a small chamber (8) communicating with a lower part of the crucible body and a carbon heater (4) processed to reduce surface blow holes thereof; putting a melted GaAs liquid and a sealing compound B.sub.2 O.sub.3 in the crucible housed in an airtight vessel in such a way that the sealing compound B.sub.2 O.sub.
    Type: Grant
    Filed: March 22, 1995
    Date of Patent: May 14, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Youji Yamashita
  • Patent number: 5487354
    Abstract: A method for pulling a silicon single crystal has the single crystal being pulled at a speed defined as maximum pulling speed in the vertical direction with respect to a silicon melt held in a crucible. The value of the maximum pulling speed is approximately proportional to the axial temperature gradient in the growing single crystal.
    Type: Grant
    Filed: December 5, 1994
    Date of Patent: January 30, 1996
    Assignee: Wacker-Chemitronic Gesellschaft fuer Eletronik-Grundstoffe mbH
    Inventors: Wilfried von Ammon, Erich Dornberger, Hans Oelkrug, Peter Gerlach, Franz Segieth
  • Patent number: 5477806
    Abstract: A solid layer is melted from the upper part thereof by the heat of a heater while the contact area between a molten liquid layer and an inner wall of a crucible is adjusted in a Double Layered CZ method, so that the eluting amount of oxygen from the crucible to the molten liquid layer is controlled. Accordingly, silicon single crystals of the low concentration of oxygen are produced.
    Type: Grant
    Filed: March 21, 1994
    Date of Patent: December 26, 1995
    Assignee: Sumitomo Sitix Corporation
    Inventors: Yoshihiro Akashi, Setsuo Okamoto, Kaoru Kuramochi, Takayuki Kubo
  • Patent number: 5431125
    Abstract: Twin-free (100) InP crystals of large dimensions and having flat crowns are produced by combining the magnetic liquid encapsulated Kyropoulos (MLEK) process and the magnetic liquid encapsulated Czochralski (MLEC) process. Observation of the flat crown by high intensity light ensures twin-free growth in the magnetic environment.
    Type: Grant
    Filed: June 14, 1991
    Date of Patent: July 11, 1995
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Stephen Bachowski, David F. Bliss, Robert M. Hilton
  • Patent number: 5429067
    Abstract: A Czochralski method using radiation intercepting members (1, 9) is used for manufacturing a single crystal such as compound semiconductors with a high production yield using a material having a low thermal conductivity or with a small temperature gradient in the pulling direction. In this method, a coracle (6) having an opening is provided in a melt contained in a crucible (3). A first member (1) is positioned on the coracle (6) to intercept heat radiation from the melt. A second member (9) supported by a crystal pulling shaft (8) is positioned on the first member (1) to cover an opening formed at the center of the first member (1). Seeding is performed while heat loss is limited by intercepting the radiation with the first and the second members. After the seeding, a shoulder portion of a single crystal is formed while heat loss is still limited while intercepting the radiation with the members (1, 9). A cylindrical body of the single crystal is pulled by the shaft (8) which also lifts the members (1, 9 ).
    Type: Grant
    Filed: January 14, 1994
    Date of Patent: July 4, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masami Tatsumi, Shin-ichi Sawada
  • Patent number: 5415125
    Abstract: A method of forming a semiconductor boule comprises the steps of providing a chamber having a crucible therein; introducing a first material and a second material into the crucible, the second material overlying the first material; heating the crucible to melt the first and second materials for substantially continuously covering the first material with the second material during the melting of the first and second materials; cooling the melt to grow a directly synthesized boule; and separating the grown boule from the crucible. In another embodiment, the method comprises steps of providing a chamber having a crucible therein; charging a first and a second material for forming the boule and a liquid encapsulant into the crucible, the volume of the intergranular space of charged first material being smaller than the volume of the molten second material; heating the crucible to melt the first and second materials; cooling the molten materials to grow the boule; and separating the grown boule from the crucible.
    Type: Grant
    Filed: November 19, 1992
    Date of Patent: May 16, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiromoto Fujita, Johji Nishio
  • Patent number: 5408951
    Abstract: In an improved Czochralski process for growing silicon crystals, wherein a single-crystal silicon seed is pulled from a molten silicon source to grow the crystal therefrom, a pre-oxidized arsenic dopant is added to the molten silicon source to alter an electrical property of the grown crystal. The pre-oxidized arsenic dopant includes granular particles of metallic arsenic having a surface film of arsenic oxide, the surface film having a thickness of ten microns to one millimeter. After doping, the molten silicon source is moved from the grown crystal, and an applied temperature is increased to burn excess pre-oxidized dopant.
    Type: Grant
    Filed: July 21, 1993
    Date of Patent: April 25, 1995
    Assignee: MEMC Electronic Materials, Inc.
    Inventor: Akiteru Tamida
  • Patent number: 5394830
    Abstract: Apparatus and method are provided for growing improved quality long and large single crystals in a liquid encapsulated Czochralski (LEC) process, in which a separate cooling circuit is provided for the upper portion of a vessel which cools that portion independently of any cooling means for the lower portion of the vessel, and in which the gas flow pattern can desirably be controlled such that the gas flow is predominantly downward adjacent the vessel wall, and predominantly upward near the center of the vessel, where the crystal is being pulled from the melt.
    Type: Grant
    Filed: August 27, 1993
    Date of Patent: March 7, 1995
    Assignee: General Electric Company
    Inventor: Farzin H. Azad
  • Patent number: 5334365
    Abstract: A flux process is disclosed for producing a single orthorhombic crystal of Cs.sub.1-x M.sub.x TiOAsO.sub.4 (where M is Na, K, Rb, and/or Tl and x is from 0 to 0.4) wherein the dimension of the crystal along each axis is at least about 2 mm, and wherein the product at the dimensions along the three axes is at least about 15 mm.sup.3. The process involves preparing a homogeneous melt containing the components for forming said crystal and a flux comprising oxides of Cs and As at a temperature no higher than the decomposition temperature of said orthorhombic crystal, the mole fraction of M relative to the total Cs+M in the melt being within the range of from 0 to about 0.2; introducing a seed crystal for said single crystal in the melt; activating the controlled crystallization on the seed crystal; and continuing the crystallization until formation of the single crystal is completed. Single crystals of Cs.sub.1-x M.sub.x TiOAsO.sub.4 (including crystals at least about 5 mm.times.5 mm 5 mm) are also disclosed.
    Type: Grant
    Filed: May 26, 1992
    Date of Patent: August 2, 1994
    Assignee: E. I. Du Pont de Nemours and Company
    Inventor: Lap K. Cheng
  • Patent number: 5326423
    Abstract: Doped crystalline compositions (e.g., single domain crystals) of MTiOAsO.sub.4 (wherein M is K, Rb and/or Cs) are disclosed which contain at least about 10 ppm total of Fe, Sc and/or In dopant. Also disclosed is a flux process which is characterized by adding said dopant to a melt containing the components for forming MTiOAsO.sub.4, in an amount effective to provide a doped single domain crystal of MTiOAsO.sub.4 containing at least 10 ppm of said dopant.
    Type: Grant
    Filed: September 30, 1992
    Date of Patent: July 5, 1994
    Assignee: E. I. Du Pont de Nemours and Company
    Inventors: Albert A. Ballman, Lap K. Cheng