Abstract: It is to provide a method for producing a silicon epitaxial wafer, which can prevent fine unevenness from occurring on a rear main surface of a silicon epitaxial wafer and which suppresses the haze level of the whole rear main surface to 50 ppm or less. A method for producing a silicon epitaxial wafer, includes: a hydrogen heat treatment step of arranging within a reactor a susceptor capable of mounting a silicon single crystal substrate and subjecting the silicon single crystal substrate mounted on the susceptor to heat treatment in a hydrogen atmosphere, and a vapor phase epitaxy step of epitaxially growing a silicon epitaxial layer after the hydrogen heat treatment step, wherein the silicon single crystal substrate is separated from the susceptor during the hydrogen heat treatment step, and the silicon single crystal substrate is mounted on the susceptor during the vapor phase epitaxy step.

Abstract: A method is provided for growing thin oxide films on the surface of a substrate by alternatively reacting the surface of the substrate with a metal source material and an oxygen source material. The oxygen source material is preferably a metal alkoxide. The metal source material may be a metal halide, hydride, alkoxide, alkyl, a cyclopentadienyl compound, or a diketonate.

Abstract: The method of making a GaN single crystal substrate comprises a mask layer forming step of forming on a GaAs substrate 2 a mask layer 8 having a plurality of opening windows 10 disposed separate from each other; and an epitaxial layer growing step of growing on the mask layer 8 an epitaxial layer 12 made of GaN.

Abstract: A method and system for forming a variable thickness seed layer on a substrate for a subsequent metal electrochemical plating process, where the seed layer thickness profile improves uniformity of the electroplated metal layer compared to when using a constant thickness seed layer. The method includes providing a substrate in a process chamber containing a showerhead, with the center of the substrate generally aligned with an inner gas delivery zone of the showerhead and the edge of the substrate generally aligned with an outer gas delivery zone of the showerhead. The method further includes depositing a seed layer on the substrate by exposing the substrate to a first gas containing a metal-containing precursor flowed through the inner gas delivery zone, and exposing the substrate to a second gas flowed through the outer gas delivery zone, whereby the seed layer is deposited with a thickness at the edge of the substrate that is less than the thickness at the center of the substrate.

Abstract: A plasma processing method includes providing a substrate in a processing chamber, the substrate having a surface, and generating a plasma in the processing chamber. The plasma provides at least two regions that exhibit different plasma densities. The method includes exposing at least some of the surface to both of the at least two regions. Exposing the surface to both of the at least two regions may include rotating the plasma and may cyclically expose the surface to the plasma density differences. Exposing to both of the at least two regions may modify a composition and/or structure of the surface. The plasma may include a plasmoid characterized by a steady state plasma wave providing multiple plasma density lobes uniformly distributed about an axis of symmetry and providing plasma between the lobes exhibiting lower plasma densities. Depositing the layer can include ALD and exposure may remove an ALD precursor ligand.

Abstract: A crystal substrate and a crystal film of a III-V compound of the nitride system which are manufactured easily and have few dislocations as well as a method of manufacturing a crystal and a method of manufacturing a device with the use thereof are disclosed. On a basal body, formed in order are a base crystal layer of, for example, gallium nitride (GaN), a first mask pattern of, for example, silicon dioxide (SiO2), an intermediate crystal layer of, for example, gallium nitride, a second mask pattern of, for example, silicon dioxide, and a top crystal layer of, for example, gallium nitride. The first and second mask patterns have stripes arranged at least in one direction at unequally spaced intervals. The stripes are different in pitch from pattern to pattern. Thus, the mask patterns at least partly overlie one another in the direction of the thickness of the crystal layers.

Abstract: A method for producing a nitride semiconductor crystal comprising steps (a), (b) and (c), which steps follow in sequence as follows: a step (a) for forming fine crystal particles made of a nitride semiconductor on a substrate; a step (b) for forming a nitride semiconductor island structure having a plurality of facets inclined relative to a surface of the substrate using the fine crystal particles as nuclei; and a step (c) for causing the nitride semiconductor island structure to grow in a direction parallel with a surface of the substrate to merge a plurality of the nitride semiconductor island structures with each other, thereby forming a nitride semiconductor crystal layer having a flat surface; the steps (a)-(c) being continuously conducted in the same growing apparatus.

Abstract: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging between 100 and 300 nm, preferably between 200 and 250 nm, and whereof crystal lattice parameter is less than the crystal lattice parameter of the gallium nitride or of the mixed gallium nitride with another metal, is inserted in the coating of gallium nitride or mixed gallium nitride with another metal. The invention also concerns the method for preparing said coating. The invention further concerns electronic and optoelectronic devices comprising said coating.

Abstract: A method of forming a phosphorus- and/or boron-containing silica layer, such as a PSG, BSG, or BPSG layer, on a substrate, such as a semiconductor substrate or substrate assembly.

Abstract: A susceptor (10) supporting a semiconductor substrate (W) in a vapor phase growth, wherein a pocket (11) is formed on an upper surface of the susceptor to arrange the semiconductor substrate (W) inside thereof. The pocket (11) has a two-stage structure having an upper stage pocket (11a) for supporting an outer peripheral edge portion of the semiconductor substrate (W) and a lower stage pocket (11b) formed on a lower stage of a center side from the upper stage pocket (11a). A hole (12) penetrated to a rear surface of the susceptor and opened in the vapor phase growth is formed in the lower stage pocket (11b).

Abstract: A method of making a multilayer article includes depositing a first material on the surface of a metal substrate to form a seed layer of the first material, the first material being deposited under reducing conditions relative to the metal substrate, and then epitaxially depositing a second material on a surface of the seed layer, wherein the second material is deposited from a solution-based precursor under second conditions that are more oxidizing than the reducing conditions used in the deposition of the first material.

Abstract: Nanostructures (18) and methods for production thereof by phase separation during metal organic vapor-phase epitaxy (MOVPE). An embodiment of one of the methods may comprise providing a growth surface in a reaction chamber and introducing a first mixture of precursor materials into the reaction chamber to form a buffer layer (12) thereon. A second mixture of precursor materials may be provided into the reaction chamber to form an active region (14) on the buffer layer (12), wherein the nanostructure (18) is embedded in a matrix (16) in the active region (14). Additional steps are also disclosed for preparing the nanostructure (18) product for various applications.

Abstract: New designs of electron devices such as scanning probes and field emitters based on tip structures are proposed. The tips are prepared from whiskers that are grown from the vapor phase by the vapor-liquid-solid technology. Some new designs for preparation of field-emitters and of probes for magnetic, electrostatic, morphological, etc, investigations based on the specific technology are proposed. New designs for preparation of multilever probes are proposed, too.

Abstract: The invention relates to a device and to a method for depositing especially crystalline layers from the gas phase onto especially crystalline substrates. The device comprises a heated reaction chamber with a substrate support that receives at least one substrate; one or more heated sources where a gaseous halide is formed by chemical reaction of a halogen, especially HCl, fed to the source together with a substrate gas, and a metal, for example GA, In, Al associated with the source, which is transported through a gas inlet section to a substrate supported by the substrate support; and a hydride supply for supplying a hydride, especially NH3, AsH3 or PH3 into the reaction chamber. A plurality of rotationally driven substrate supports is disposed in an annular arrangement on a substrate support carrier, the sources being disposed in the center of said substrate carrier.

Abstract: This invention relates to a method for depositing III-V semiconductor layers on a non III-V substrate especially a sapphire, silicon or silicon oxide substrate, or another substrate containing silicon. According to said method, a III-V layer, especially a buffer layer, is deposited on the substrate or on a III-V germination layer, in a process chamber of a reactor containing gaseous starting materials. In order to reduce the defect density of the overgrowth, a masking layer consisting of essentially amorphous material is deposited directly on the III-V germination layer or directly on the substrate, said masking layer partially covering of approximately partially covering the germination layer. The masking layer can be a quasi-monolayer and can consist of various materials.

Abstract: Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.

Abstract: A silicon-based wafer support tower particularly useful for batch-mode thermal chemical vapor deposition. The surfaces of the silicon tower are bead blasted to introduce sub-surface damage, which produces pits and cracks in the surface, which anchor subsequently deposited layer of, for example, silicon nitride, thereby inhibiting peeling of the nitride film. The surface roughness may be in the range of 250 to 2500 ?m. Wafer support portions of the tower are preferably composed of virgin polysilicon. The invention can be applied to other silicon parts in a deposition or other substrate processing reactor, such as tubular sleeves and reactor walls. Tubular silicon members are advantageously formed by extrusion from a silicon melt.

Abstract: A method of producing a p doped wide bandgap semiconductor including growing a semiconductor in the presence of an element apt acting as a surfactant at a growth surface of the semiconductor and inhibiting formation of vacancies, and doping the semiconductor with a selected p dopant.

Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).

Abstract: A process for closing hollow-core defects, called micropipes, during growth by CVD of a SiC crystal on a SiC single crystal substrate having hollow-core defects, and a crystal obtained according to the process, by contacting the SiC crystal with a source gas adjusted to a C/Si atom ratio range in which the crystal growth rate is determined by the carbon atom supply limitation, then epitaxially growing and laminating a plurality of SiC crystal layers, wherein hollow-core defects in the SiC single crystal substrate dissociate into a plurality of dislocations given by small Burghers vector in order not to propagate to the crystal surface. In addition, the present invention provides a fabrication process of a SiC crystal, wherein a first SiC crystal is made as a buffer layer, and a further SiC crystal is layered thereon using a source gas adjusted to be higher than that of the C/Si ratio when forming the buffer layer, whereby a desired film property is conferred.

Abstract: A film (carbon and/or diamond) for a field emitter device, which may be utilized within a computer display, is produced by a process utilizing etching of a substrate and then depositing the film. The etching step creates nucleation sites on the substrate for the film deposition process. With this process patterning of the emitting film is avoided. A field emitter device can be manufactured with such a film.

Abstract: Methods of crystal growth for semiconductor materials, such as nitride semiconductors, and methods of manufacturing semiconductor devices are provided. The method of crystal growth includes forming a number of island crystal regions during a first crystal growth phase and continuing growth of the island crystal regions during a second crystal growth phase while bonding of boundaries of the island crystal regions occurs. The second crystal growth phase can include a crystal growth rate that is higher than the crystal growth rate of the first crystal growth phase and/or a temperature that is lower than the first crystal growth phase. This can reduce the density of dislocations, thereby improving the performance and service life of a semiconductor device which is formed on a nitride semiconductor made in accordance with an embodiment of the present invention.

Abstract: A method of crystallizing amorphous silicon is used for manufacturing an array substrate having thin film transistors, pixel electrodes and an alignment key. The method includes forming an amorphous silicon layer over a substrate, forming an alignment key in the amorphous silicon layer, preparing a mask including pattern portions and an alignment key pattern, disposing the mask over the substrate having the amorphous silicon layer, wherein the alignment key pattern is aligned with the alignment key, and applying a first shot of a laser beam to in the amorphous silicon layer to form first polycrystalline silicon areas corresponding to the pattern portions of the mask.

Abstract: A method is for making a semiconductor device by forming a superlattice that, in turn, includes a plurality of stacked groups of layers. The method may also include forming regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions so that the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise occur. The superlattice may also have a common energy band structure therein.

Abstract: A CVD method deposits conformal metal layers on small features of a substrate surface. The method includes three principal operations: depositing a thin conformal layer of precursor over some or all of the substrate surface; oxidizing the precursor to convert it to a conformal layer of metal oxide; and reducing some or all of the metal oxide to convert it to a conformal layer of the metal itself. The conformal layer of precursor may form a “monolayer” on the substrate surface. Examples of metals for deposition include copper, cobalt, ruthenium, indium, and rhodium.

Abstract: A device substrate is provided having: a Si(111) substrate; a buffer layer formed by epitaxial growth on the Si(111) substrate 11, and containing at least one of a rare earth metal oxide and an alkali earth metal oxide; and a semiconductor material layer formed by epitaxial growth on the buffer layer, and containing at least one of a group II–VI semiconductor material having a wurtzite structure and a group III–V semiconductor material having a wurtzite structure. The buffer layer preferably comprises a hexagonal crystal structure oriented in the (001) plane or a cubic crystal structure oriented in the (111) plane, and the semiconductor material layer preferably comprises a hexagonal crystal structure oriented in the (001) plane.

Abstract: In a semiconductor element comprising microcrystalline semiconductor, a semiconductor junction is provided within a microcrystal grain. Further, in a semiconductor element comprising microcrystalline semiconductor, microcrystal grains of different grain diameters are provided as a mixture to form a semiconductor layer. Thereby, discontinuity of a semiconductor junction is lessened to thereby improve the characteristics, durability, and heat resisting properties of a semiconductor element. Distortion in a semiconductor layer is also reduced.

Abstract: A metallic surfactant, e.g., Sb, Bi, As, or atomic hydrogen is used to grow a high quality, relaxed, relatively thin SiGe buffer having a very smooth surface and a very low threading dislocation density, on which high-quality films are epitaxially grown for various applications.

Abstract: A nitride-based semiconductor element having superior mass productivity and excellent element characteristics is obtained. This nitride-based semiconductor element comprises a substrate comprising a surface having projection portions, a mask layer formed to be in contact with only the projection portions of the surface of the substrate, a first nitride-based semiconductor layer formed on recess portions of the substrate and the mask layer and a nitride-based semiconductor element layer, formed on the first nitride-based semiconductor layer, having an element region. Thus, the first nitride-based semiconductor layer having low dislocation density is readily formed on the projection portions of the substrate and the mask layer through the mask layer serving for selective growth.

Abstract: A single crystal M*N article, which may be made by a process including the steps of: providing a substrate of material having a crystalline surface which is epitaxially compatible with M*N; depositing a layer of single crystal M*N over the surface of the substrate; and removing the substrate from the layer of single crystal M*N, e.g., with an etching agent which is applied to the substrate to remove same, to yield the layer of single crystal M*N as said single crystal M*N article. The bulk single crystal M*N article is suitable for use as a substrate for the fabrication of microelectronic structures thereon, to produce microelectronic devices comprising bulk single crystal M*N substrates, or precursor structures thereof.

Abstract: A seed layer as a laminate of a GaN layer (second seed layer) and an AlN buffer layer (first seed layer) is formed on a sapphire substrate. A front surface thereof is etched in the form of stripes with a stripe width (seed width) of about 5 ?m, a wing width of about 15 ?m and a depth of about 0.5 ?m. As a result, mesa portions each shaped like nearly a rectangle in sectional view are formed. Non-etched portions each having the seed multilayer as its flat top portion are arranged at arrangement intervals of L?20 ?m. Part of the sapphire substrate is exposed in trough portions of wings. The ratio S/W of the seed width to the wing width is preferably selected to be in a range of from about ? to about ?. Then, a semiconductor crystal A is grown to obtain a thickness of not smaller than 50 ?m. The semiconductor crystal is separated from the starting substrate to thereby obtain a high-quality single crystal independent of the starting substrate.

Abstract: A method of forming a free-standing (Al, Ga, In)N article, by the steps including: providing an expitaxially compatible sacrificial template; depositing single crystal (Al, Ga, In)N material on the template to form a composite sacrificial template/(Al, Ga, In)N article including an interface between the sacrificial template and the (Al, Ga, In)N material; and interfacially modifying the composite sacrificial template/(Al, Ga, In)N article to part the sacrificial template from the (Al, Ga, In)N material and yield the free-standing (Al, Ga, In)N article. The free-standing (Al, Ga, In)N article produced by such method is of superior morphological character, and suitable for use as a substrate, e.g., for fabrication of microelectronic and/or optoelectronic devices and device precursor structures.

Abstract: A precursor and method for filling a feature in a substrate. The method generally includes depositing a barrier layer, the barrier layer being formed from pentakis(dimethylamido)tantalum having less than about 5 ppm of chlorine. The method additionally may include depositing a seed layer over the barrier layer and depositing a conductive layer over the seed layer. The precursor generally includes pentakis(dimethylamido)tantalum having less than about 5 ppm of chlorine. The precursor is generated in a canister having a surrounding heating element configured to reduce formation of impurities.

Abstract: The present invention deals with the generation of sharp single crystal diamond tips and the arrays of these tips, and their fabrication technology. The invention combines the deposition of synthetic diamond films with reactive etching processes. Upon the diamond orientation prepared and reactive etching environment with considerable directivity of ions, single crystal diamond tips with different apical angles can be fabricated. Very sharp diamond tips with an apical angle of no more than about 28° and a tip radius smaller than 50 nm are fabricated on pyramidal-shaped [001]-textured diamond films by subsequent reactive etching., The technology is based on selective etching of sp2- and sp3- hybridized carbons by the activated constituents of an etching environment, in particular based on atomic hydrogen, in a way similar to ion bombardment, which contributes to overall etching and local conversion of diamond to graphitic phase promoting further etching with chemically activated species.

Abstract: High quality epitaxial layers of monocrystalline perovskite materials (18) can be grown overlying monocrystalline substrates (12) such as gallium arsenide wafers by forming a metal template layer (16) on the monocrystalline substrate. The structure includes a metal-containing layer (16) to mitigate unwanted oxidation of underlying layers and a low-temperature seed layer (19) that prevents degradation of an epitaxial layer (14) during growth of the perovskite layer (18).

Abstract: In the preferred embodiment of this invention a method is described to convert patterned SOI regions into patterned SGOI (silicon-germanium on oxide) by the SiGe/SOI thermal mixing process to further enhance performance of the logic circuit in an embedded DRAM. The SGOI region acts as a template for subsequent Si growth such that the Si is strained, and electron and holes in the Si have higher mobility.

Abstract: In a semiconductor manufacturing system for manufacturing compound semiconductor by MOCVD, a lead-in member is provided for guiding feed gas supplied from a feed gas supply unit onto the surface of a semiconductor substrate disposed in a reactor, a main body of the lead-in member is constituted as a hollow member to form a feed gas guide passage for conducting the feed gas in an prescribed direction and is formed with multiple orifices, and the feed gas in the feed gas guide passage is jetted from the orifices in a direction perpendicular to the prescribed direction so that the semiconductor substrate is bathed in a feed gas flow of uniform amount jetted from the lead-in member in this manner. Furthermore, a pressure differential produced between the inner side and outer side of the nozzle member enables the feed gas jetted from the nozzle member to flow over the whole surface of the substrate at a uniform flow rate.

Abstract: In a method for growing a GaN based compound semiconductor on a front surface of a substrate to obtain the GaN based compound semiconductor crystal in one body, because the gas for reducing and decomposing the substrate is supplied to the rear surface of the substrate and a heat treatment is carried out in a gas atmosphere in which the nitrogen partial pressure is not less than a predetermined value, in order to remove the substrate, it can be prevented that cracks are caused in the crystal, or fracture or warp is caused by causing strain of the GaN based compound semiconductor crystal in a cooling step.

Abstract: Methods are disclosed that provide for structures and techniques for the fabrication of ordered arrangements of crystallographically determined nanometer scale steps on single crystal substrates, particularly SiC. The ordered nanometer scale step structures are produced on the top surfaces of mesas by a combination of growth and etching processes. These structures, sometimes referred to herein as artifacts, are to enable step-height calibration, particularly suitable for scanning probe microscopes and profilometers, from less than one nanometer (nm) to greater than 10 nm, with substantially no atomic scale roughness of the plateaus on either side of each step.

Abstract: A deposition mask capable of relaxing nonuniformity of the thickness of a deposit formed on a substrate and reducing the width of a non-opening part of a mask layer by reducing the thickness of the mask layer is obtained. This deposition mask comprises a mask layer formed by a single silicon thin film and a mask pattern, formed on the mask layer, including a mask opening having an opening width increased toward a deposition source. The mask layer formed by a silicon thin film can be reduced in thickness due to small deflection caused by its own weight. Thus, the width of the non-opening part of the mask layer can be reduced, whereby the width of a part formed with no deposit can be reduced.

Abstract: The present invention relates to oxides on suitable substrates, as converted from nitride precursors.

Abstract: The invention relates to a device and method for depositing one or more layers onto at least one substrate placed inside a reaction chamber. The layers are deposited while using a liquid or solid starting material for one of the reaction gases utilized, which are fed via a gas admission unit to the reaction chamber where they condense or epitaxially grow on the substrate. The gas admission unit comprises a multitude of buffer volumes in which the reaction gasses enter separate of one another, and exit through closely arranged outlet openings while also being spatially separate of one another. The temperature of reaction gases is moderated while passing through the gas admission unit.

Abstract: To plasma-process a substrate having a large area uniformly at a high process speed to form a deposition film with uniform thickness and quality and favorable characteristics. A first high frequency power (with a frequency f1 and a power P1) and a second high frequency power (with a frequency f2 and a power P2) supplied to an electrode from a first high frequency power supply and a second high frequency power supply, respectively, are set so that the frequencies are equal to or higher than 10 MHz and equal to or lower than 250 MHz, a ratio of the frequency f2 to the frequency f1 (f2/f1) is equal to or higher than 0.1 and equal to or lower than 0.9, and a ratio of the power P2 to a total power (P1+P2) is equal to or higher than 0.1 and equal to or lower than 0.9. The frequency f2 is changed during processing the substrate.

Abstract: Selected micro- and nanoscale, 1-dimensional and 2-dimensional periodic and random structures generated on silicon and other substrates are expected to perform as compliant, thin films for gettering defects and for accommodating lattice and thermal expansion mismatches during heteroepitaxial growth thereon, thereby leading to relatively defect-free, heteroepitaxial films of chosen thicknesses. The as-grown epilayers or completed electronic and optoelectronic devices can be bonded to a second substrate such as glass, or plastic following separation thereof from the substrate on which they were formed using preferential etching of a readily detachable, nanoporous silicon or silicon dioxide layer introduced between the generated structures and the substrate.

Abstract: Method for producing substrates charged with materials, including placing the substrate into an evacuated vacuum container. The substrate is exposed to a reactive gas which is adsorbed on the surface. The surface with the adsorbed reactive gas is exposed to a low-energy plasma discharge with ion energy EI0 on the surface of the substrate of 0<EI0≦20 eV; and an electron energy Eeo of 0 eV<Eeo≦100 eV. The adsorbed reactive gas is allowed to react at least with the cooperation of plasma-generated ions and electrons.

Abstract: A method for growing a single crystal GaN film at least 2 microns thick on a Si substrate is disclosed. The method includes growing a prelayer, a buffer layer including AlN on the Si substrate and a plurality of GaN layers and AlN layers deposited alternatively on the top of the AlN buffer layer. By controlling the deposition conditions and timings of the plurality of GaN layers and AlN layers, the single crystal GaN film can be grown thicker than 2 microns without cracks or pits.

Abstract: A CVD method for growing MgO on a Si(100) substrate coated with a cubic SiC buffer layer provides a single-crystalline MgO film having improved quality.

Abstract: A micro three-dimensional structure capable of producing a micro three-dimensional structure (micrometer-to nanometer-order outer shape) having a complicated structure, a production method therefor and production device therefor are provided. In the production method for the micro three-dimensional structure, performed are the step of irradiating a focused ion beam (4) to a sample (1) while supplying a material gas (3) to form a first-layer deposit (5), the step of releasing secondary electrons (6) from the first-layer deposit (5) hit by ions to allow the secondary electrons (6) to form a terrace (7) on the first-layer deposit (5), a step of deflecting the focused ion beam (4) in a desired direction of the terrace (7) based on a set amount from a focal position controlling apparatus, a step of forming a second-layer deposit (8) in a deflected position on the terrace (7) based on the deflection amount, and a step of repeating the above steps to form a set micro three-dimensional structure.

Abstract: A process of fabricating a CMOS device comprised with super-steep retrograde (SSR), twin well regions, has been developed. The process features the use of two, selective epitaxial growth (SEG), procedures, with the first SEG procedure resulting in the growth of bottom silicon shapes in the PMOS, as well as in the NMOS region of the CMOS device. After implantation of the ions needed for the twin well regions, into the bottom silicon shapes, a second SEG procedure is employed resulting in growth of top silicon shapes on the underlying, implanted bottom silicon shapes. An anneal procedure then distributes the implanted ions resulting in an SSR N well region in the composite silicon shape located in the PMOS region, and resulting in an SSR P well region in the composite silicon shape located in the NMOS region of the CMOS device.

Abstract: A method for fabricating a Group III nitride semiconductor substrate according to the present invention includes the steps of: (a) preparing a substrate; (b) forming, on the substrate, a first semiconductor layer composed of a Group III nitride semiconductor; (c) forming, on the first semiconductor layer, a heat diffusion suppressing layer lower in thermal conductivity than the first semiconductor layer; (d) forming, on the heat diffusion suppressing layer, a second semiconductor layer composed of a Group III nitride semiconductor; and (e) irradiating the first semiconductor layer through the substrate with a light beam transmitted by the substrate and absorbed by the first semiconductor layer to decompose the first semiconductor layer.