Patterned strained silicon for high performance circuits
In the preferred embodiment of this invention a method is described to convert patterned SOI regions into patterned SGOI (silicon-germanium on oxide) by the SiGe/SOI thermal mixing process to further enhance performance of the logic circuit in an embedded DRAM. The SGOI region acts as a template for subsequent Si growth such that the Si is strained, and electron and holes in the Si have higher mobility.
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The field of the invention is that of integrated circuit processing to create patterned SiGe on Oxide (SGOI) regions with high relaxation (>50%) for manufacturing high performance logic circuits including embedded DRAMs.
BACKGROUND OF THE INVENTIONIt has been shown that strained Si has higher n and p carrier mobilities than unstrained Si. Increased carrier mobilities lead to higher performance in CMOS circuits such as microprocessors. One way to create strained-Si is to grow a thin single crystal Si layer on a relaxed single crystal substrate that has a higher in-plane lattice parameter than that of the Si. One such relaxed substrate is Si—Ge.
For embedded memory applications, it is desirable to create patterned SOI regions. High performance CMOS integrated circuits are made on the SOI regions, whereas the dynamic memory (DRAM) circuits are made on the bulk-Si regions. Details of forming patterned SOI regions are described by Davari et al. in U.S. Pat. No. 6,333,532.
In the semiconductor industry, there has recently been a high-level of activity using strained Si-based heterostructures to achieve high mobility structures for CMOS applications. Traditionally, the prior art method to implement this has been to grow strained Si layers on thick (on the order of from about 1 to about 5 micrometers) relaxed SiGe buffer layers.
Despite the high channel electron mobilities reported for prior art heterostructures; the use of thick SiGe buffer layers has several noticeable disadvantages associated therewith. First, thick SiGe buffer layers are not typically easy to integrate with existing Si-based CMOS technology. Second, the defect densities, including threading dislocations and misfit dislocations, are from about 105 to about 108 defects/cm2 which are still too high for realistic VSLI (very large scale integration) applications. Thirdly, the nature of the prior art structure precludes selective growth of the SiGe buffer layer so that circuits employing devices with strained Si, unstrained Si and SiGe materials are difficult, and in some instances, nearly impossible to integrate.
In order to produce relaxed SiGe material on a Si substrate, prior art methods typically grow a uniform, graded or stepped, SiGe layer to beyond the metastable critical thickness (i.e., the thickness beyond which dislocations form to relieve stress) and allow misfit dislocations to form, with the associated threading dislocations (TDs), through the SiGe buffer layer. Various buffer structures have been used to try to modulate the formation of misfit dislocations in the structures and thereby to decrease the TD density.
Another prior art approach, such as described in U.S. Pat. Nos. 5,461,243 and 5,759,898, both to Ek, et al., provides a structure with a strained and defect free semiconductor layer wherein a new strain relieve mechanism operates so that the SiGe buffer layer relaxes without the generation of TDs within the SiGe layer.
Neither the conventional approaches, nor the alternative approaches described in the Ek, et al. patents provide a solution that substantially satisfies the material demands for device applications, i.e., sufficiently low TD density, substantially little or no misfit dislocation density and control over where the TD defects will be formed. As such, there is a continued need for developing a new and improved method of forming relaxed SiGe-on-insulator substrate materials which are thermodynamically stable against defect production.
SUMMARY OF THE INVENTIONThe invention relates to a method of forming both compressive and tensile Si in pre-determined locations.
A feature of the invention is the formation of tensile-stressed silicon by epitaxial growth over a layer of SiGe alloy.
A feature of the invention is the formation of compressively stressed silicon by epitaxial growth over porous silicon.
Method to Form Tensile Strain-Si
As shown in
A subsequent high-temperature annealing and/or oxidation of the structure diffusively mixes the Ge throughout the layers above the insulator. In this example, as shown in
Referring to
In the next step, a layer of silicon 50 is formed (
Because the SiGe alloy crystal has a larger lattice constant than Si (the magnitude depending on the Ge content), the high-temperature annealing also allows the homogenized SiGe layer to expand or “relax” thereby increasing its lattice constant with respect to that of pure Si. This increased lattice constant makes it possible to grow Si under tensile strain by epitaxial growth onto the surface of the relaxed SiGe alloy. The enhanced charge carrier transport properties within the strained Si makes this an attractive material in which to fabricate high-performance CMOS integrated circuits.
In another embodiment of this invention, a modified process is used as shown in FIG. 2. In this and other embodiments, elements with the same reference numeral is shown in
As shown in
Thermal mixing is conducted in a similar manner as described above for the preferred embodiment of
Deposition of silicon as in the embodiment of FIG. 1 and patterning of the deposited layers results in the structure shown in
In yet another embodiment of this invention, shown in
STI regions are created such that patterned SOI regions with SiGe layers are created (
Layer 40 is stripped and the STI members 70 are planarized, leaving the structure shown in
In all embodiments described above, the final step is to grow a thin Si layer 50 over the SGOI region such that it has tensile strain (
Method to Form Compressively Strained Si
Referring to
The process starts with the same patterned substrate of
The p+ region 82 is converted into porous-Si via anodic etching to form islands 83, as shown in
As shown in
Additional embodiments for compressively and tensile strained Si are included in
While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be practiced in various versions within the spirit and scope of the following claims.
Claims
1. A method of forming regions of strained silicon in a wafer with a set of compressive regions comprising a layer of silicon under compressive stress and a set of tensile regions comprising a layer of silicon under tensile stress comprising the steps of:
- providing a silicon wafer containing a set of buried oxide regions and a set of silicon device regions, a first subset of which are disposed over said set of buried oxide regions;
- introducing Ge into said first subset;
- forming a set of porous areas of silicon in a second subset of said device regions separate from said first subset;
- forming a layer of strained silicon above at least said device regions, thereby forming said set of tensile regions over said first subset and forming said set of compressive regions over said second subset.
2. A method according to claim 1, in which said step of introducing Ge is effected by:
- forming a layer of SiGe on said wafer; and
- mixing Ge from said SiGe into said device regions by heating said wafer.
3. A method according to claim 2, in which said layer of silicon is formed uniformly across said first subset and intervening areas and after said steps of forming porous silicon and said step of mixing Ge.
4. A method according to claim 2, in which said second subset is formed by anodic etching.
5. A method according to claim 4, further comprising an implant of a selected ion species in second subset before said step of anodic etching.
6. A method according to claim 5, in which said layer of silicon is formed uniformly across said first subset and intervening areas and after said steps of forming porous silicon and said step of mixing Ge.
7. A method according to claim 2, further comprising a step of forming a set of STI members defining said set of device islands.
8. A method according to claim 7, in which said step of forming STI members is performed before said step of mixing Ge.
9. A method according to claim 1, in which said second subset is formed by anodic etching.
10. A method according to claim 9, further comprising an implant of a selected ion species in second subset before said step of anodic etching.
11. A method according to claim 10, in which said layer of silicon is formed uniformly across said first subset and intervening areas and after said steps of forming porous silicon and said step of introducing Ge.
12. A method according to claim 1, in which said layer of silicon is formed uniformly across said first subset and intervening areas and after said steps of forming porous silicon and said step of introducing Ge.
13. A method according to claim 1, further comprising a step of forming a set of STI members defining said set of device islands.
14. A method according to claim 13, in which said step of forming STI members is performed before said step of mixing Ge.
15. A method according to claim 14, in which said step of forming a layer of silicon comprises forming a self-aligned layer of epitaxial silicon over said device regions.
16. A method according to claim 13, in which said step of forming a layer of silicon comprises forming a self-aligned layer of epitaxial silicon over said device regions.
17. A method of forming regions of strained silicon in a wafer with a set of compressive regions comprising a layer of silicon under compressive stress and a set of tensile regions comprising a layer of silicon under tensile stress comprising the steps of:
- providing a silicon on insulator wafer containing a uniform buried oxide region and a set of silicon device regions, a first subset of which are disposed over said set of buried oxide regions;
- introducing Ge into said first subset;
- forming a set of porous areas of silicon in a second subset of said device regions separate from said first subset;
- forming a layer of Si above at least said device regions, thereby forming said set of tensile regions over said first subset and forming said set of compressive regions over said second subset.
18. A method according to claim 17, in which said step of introducing Ge is effected by:
- forming a layer of SiGe on said wafer; and
- mixing Ge from said SiGe into said device regions by heating said wafer.
19. A method according to claim 18, in which said second subset is formed by anodic etching.
20. A method according to claim 19, further comprising an implant of a selected ion species in second subset before said step of anodic etching.
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Type: Grant
Filed: Jan 2, 2003
Date of Patent: Apr 12, 2005
Patent Publication Number: 20040132267
Assignee: International Business Machines Corporation (Armonk, NY)
Inventors: Devendra K. Sadana (Pleasantville, NY), Stephen W. Bedell (Wappingers Falls, NY), Tze-Chiang Chen (Yorktown Heights, NY), Kwang Su Choe (Mt. Kisco, NY), Keith E. Fogel (Mohegan Lake, NY)
Primary Examiner: M. Wilczewski
Attorney: Eric W. Petraske
Application Number: 10/336,147