Gallium Arsenide Containing (e.g., Gaalas, Gaas) {c30b 29/42} Patents (Class 117/954)
  • Patent number: 8771560
    Abstract: In a process for manufacturing doped semiconductor single crystal comprises solidifying in a crucible, the amount of dopant is added into the semiconductor melt after the beginning of the crystal growth onto the seed crystal, or after at least partial solidification of the semiconductor single crystal in a conical or tapered portion of the crucible. Dopant may be partially added in advance into the crucible, with the remainder added into the semiconductor melt as described. Type III-V semiconductor single crystals or wafers having a diameter of at least about 100 mm, can be prepared having an electrical conductivity of at least about 250 Siemens/cm, and/or an electric resistivity of at most about 4×10?3 ?cm, and/or a significantly improved ratio of hall mobility to charge carrier concentration.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: July 8, 2014
    Assignee: Freiberger Compound Materials GmbH
    Inventors: Ulrich Kretzer, Stefan Eichler, Thomas Bünger
  • Patent number: 8658449
    Abstract: A method of manufacturing a semiconductor layer with which inactivation of impurity is able to be inhibited by a simple method, a semiconductor layer in which inactivation of impurity is inhibited, a method of manufacturing a laser diode with which inactivation of impurity is able to be inhibited by a simple method, and a laser diode including a semiconductor layer in which inactivation of impurity is inhibited are provided. In the method of manufacturing a semiconductor layer, after a semiconductor layer is formed by epitaxial growth with the use of AsH3, supply of AsH3 is stopped without separately supplying new gas when process temperature is 500 deg C. or more.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: February 25, 2014
    Assignee: Sony Corporation
    Inventors: Naoki Jogan, Takahiro Arakida
  • Patent number: 8231728
    Abstract: An epitaxial growth method forming a semiconductor thin film including a heterojunction of a group III-V compound semiconductor by means of molecular beam epitaxy. The method is configured to include: a first step of irradiating a molecular beam of at least one of group III elements and a molecular beam of a first group V element to form a first compound semiconductor layer; a second step of stopping the irradiation of the molecular beam of the group III element and the molecular beam of the first group V element to halt growth until an amount of the first group V element supplied is reduced to 1/10 or less of a supply of the first group V element in the first step; and a third step of irradiating a molecular beam of at least one of the group III elements and a molecular beam of a second group V element to form a second compound semiconductor layer, which is different from the first compound semiconductor, on the first compound semiconductor layer.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: July 31, 2012
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Misao Takakusaki, Susumu Kanai
  • Patent number: 7804019
    Abstract: A substrate is provided including a growth surface that is offcut relative to a plane defined by a crystallographic orientation of the substrate at an offcut angle of about 5 degrees to about 45 degrees. A thermoelectric film is epitaxially grown on the growth surface. A crystallographic orientation of the thermoelectric film may be tilted about 5 degrees to about 30 degrees relative to the growth surface. The growth surface of the substrate may also be patterned to define a plurality of mesas protruding therefrom prior to epitaxial growth of the thermoelectric film. Related methods and thermoelectric devices are also discussed.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: September 28, 2010
    Assignee: Nextreme Thermal Solutions, Inc.
    Inventors: Jonathan Pierce, Robert P. Vaudo
  • Patent number: 7591895
    Abstract: A method and an apparatus for producing crystals wherein crystal quality can be kept and a crystal composition is uniformed from a growth early stage to a growth last stage are provided. In an apparatus for producing crystals wherein the crystals 13 are grown from a liquefying raw material 12 in a crucible retained in a furnace and slowly cooling the raw material 12 in the crucible 11 from below upward, the apparatus comprises a raw material supply apparatus 18 which supplies a resupply raw material, and a reflection plate 20 placed above the crucible 11, which liquefies the resupply raw material 19 supplied from the raw material supply apparatus 18 and drops it as a liquid into the crucible.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: September 22, 2009
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Masahiro Sasaura, Hiroki Kohda, Kazuo Fujiura, Takashi Kobayashi, Tadayuki Imai, Takashi Kurihara
  • Patent number: 7115167
    Abstract: The invention provides a method of growing an (In, Ga)N multiplayer structure by molecular beam epitaxy. Each GaN or InGaN layer in the multilayer structure is grown at a substrate temperature of at least 650° C., and this provides improved material quality. Ammonia gas is used as the source of nitrogen for the growth process. Ammonia and gallium are supplied to the growth chamber at substantially constant rates, and the supply rate of indium to the growth chamber is varied to select the desired composition for the layer being grown. This allows the structure to be grown at a substantially constant growth rate. The substrate temperature is preferably kept constant during the growth process, to avoid the need to interrupt the growth process to vary the substrate temperature between the growth of one layer and the growth of another layer.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: October 3, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Stewart Edward Hooper, Jennifer Mary Barnes, Valerie Bousquet, Jonathan Heffernan
  • Patent number: 7048798
    Abstract: A method of producing a silicon carbide single crystal in which a sublimation raw material 40 is accommodated at the side of vessel body 12 in a graphite crucible 10, placing a seed crystal of a silicon carbide single crystal at the side of cover body 11 of the graphite crucible 10, the sublimation raw material 40 is sublimated by a first induction heating coil 21 placed at the side of sublimation raw material 40, a re-crystallization atmosphere is form by a second induction heating coil 20 placed at the side of cover body 11 so that the sublimation raw material 40 sublimated by the first induction heating coil 21 is re-crystallizable only in the vicinity of the seed crystal of a silicon carbide single crystal, and the sublimation raw material 40 is re-crystallized on the seed crystal of a silicon carbide single crystal, and a silicon carbide single crystal 60 is grown while keeping the whole surface of its growth surface in convex shape through the all growth processes.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: May 23, 2006
    Assignee: Bridgestone Corporation
    Inventors: Takayuki Maruyama, Shigeki Endo
  • Patent number: 6958093
    Abstract: A method of forming a free-standing (Al, Ga, In)N article, by the steps including: providing an expitaxially compatible sacrificial template; depositing single crystal (Al, Ga, In)N material on the template to form a composite sacrificial template/(Al, Ga, In)N article including an interface between the sacrificial template and the (Al, Ga, In)N material; and interfacially modifying the composite sacrificial template/(Al, Ga, In)N article to part the sacrificial template from the (Al, Ga, In)N material and yield the free-standing (Al, Ga, In)N article. The free-standing (Al, Ga, In)N article produced by such method is of superior morphological character, and suitable for use as a substrate, e.g., for fabrication of microelectronic and/or optoelectronic devices and device precursor structures.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: October 25, 2005
    Assignee: Cree, Inc.
    Inventors: Robert P. Vaudo, George R. Brandes, Michael A. Tischler, Michael K. Kelly
  • Patent number: 6955858
    Abstract: Transition metal doped II–V nitride material films exhibit ferromagnetic properties at or above room temperature. A III–V nitride material film may be doped with a transition metal film in-situ during metal-organic chemical vapor deposition and/or by solid-state diffusion processes. Doping of the III–V nitride material films may proceed in the absence of hydrogen and/or in the presence of nitrogen. In some embodiments, transition metal-doped III–V nitride material films comprise carbon concentrations of at least 1017 atoms per cubic centimeter.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: October 18, 2005
    Assignee: North Carolina State University
    Inventors: Nadia A. ElMasry, Salah M. Bedair, Meredith L. Reed, Hans Stadelmaier
  • Patent number: 6949140
    Abstract: A group-III nitride crystal growth method, comprising the steps of: a) preparing a mixed molten liquid of an alkaline metal and a material at least comprising a group-III metal; b) growing a group-III nitride crystal of the group-III metal and nitrogen from the mixed molten liquid and a material at least comprising nitrogen; and c) setting a predetermined crystal growth condition according to a zone defined by a pressure and a temperature in said step b).
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: September 27, 2005
    Assignee: Ricoh Company, Ltd.
    Inventors: Seiji Sarayama, Hirokazu Iwata, Masahiko Shimada, Hisanori Yamane, Masato Aoki
  • Patent number: 6911079
    Abstract: The resistivity of a p-doped III-V or a p-doped II-VI semiconductor material is reduced. The reduction of resistivity of the p-type III-V or a II-VI semiconductor material is achieved by applying an electric field to the semiconductor material. III-V nitride-based light emitting diodes are prepared.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: June 28, 2005
    Assignee: Kopin Corporation
    Inventors: Peter Rice, Schang-Jing Hon, Alexander Wang, Kevin O'Connor
  • Patent number: 6808740
    Abstract: A magnetoresistance effect film includes a substrate, a plurality of ferromagnetic particles disposed on the substrate, a nonmagnetic film deposited on the substrate and covering the plurality of ferromagnetic particles, and a pair of electrodes arranged on the nonmagnetic film, in which the resistance across the pair of electrodes is changed by applying a magnetic field. The magnetoresistance effect film is manufactured by vapor-depositing ferromagnetic particle starting material on a substrate at a temperature not exceeding 300° C., the starting material being vapor-deposited in an amount enough to cover the substrate surface to a thickness ranging from 0.5 to 15 nm, and, after formation of ferromagnetic particles on the substrate, vapor-depositing at a temperature not exceeding room temperature a nonmagnetic film over the ferromagnetic particles, the nonmagnetic film having a thickness ranging from 1 to 100 nm, and providing a pair of electrodes each at a predetermined position on the nonmagnetic film.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: October 26, 2004
    Assignees: National Institute of Advanced Industrial Science and Technology, Hiroyuki Akinaga
    Inventors: Hiroyuki Akinaga, Masaharu Oshima, Masaki Mizuguchi
  • Patent number: 6780244
    Abstract: A large semiconductor crystal is produced by charging a raw material into a crucible in a reactor tube, sealing the reactor tube with a flange on an open end of the tube, pressurizing the interior of the tube to an elevated pressure with an inert gas, heating the tube with an externally arranged heater to melt the raw material to form a raw material melt in the crucible, and solidifying the raw material melt to grow the semiconductor crystal. A second raw material such as a group V element can be introduced as a vapor from a reservoir into the melt in the crucible to form a compound semiconductor material. The flange is sealed to the tube by an elastic seal member, of which the temperature is maintained below 400° C. throughout the process, to protect its elastic sealing properties.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: August 24, 2004
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tomohiro Kawase, Katsushi Hashio, Shin-ichi Sawada, Masami Tatsumi
  • Patent number: 6692837
    Abstract: A semi-insulating InP substrate in which a Ru-doped semi-insulating semiconductor layer is formed on the surface is provided, wherein the Ru-doped semi-insulating semiconductor layer has a complete semi-insulating property. The semiconductor optical device is fabricated by forming the Ru-doped semi-insulating semiconductor layer on a Fe-doped semi-insulating InP substrate, and forming a semiconductor crystal layer to which a p-type impurity is doped.
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: February 17, 2004
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Ryuzo Iga, Matsuyuki Ogasawara, Susumu Kondo, Yasuhiro Kondo
  • Patent number: 6673149
    Abstract: A method for the production of a crack-free epitiaxial film having a thickness greater than that which can be achieved by continuous epitaxial crystal growth. This epitaxial film can be used as is in a device, used as a substrate platform for further epitaxy, or separated from the initial substrate material and used as a free-standing substrate platform. The method utilizes a defect-rich initial layer that absorbs epitaxially derived stresses and another layer, which is not defect-rich, which planarizes the crystal growth front, if necessary and provides high quality epitaxial region near the surface.
    Type: Grant
    Filed: September 6, 2000
    Date of Patent: January 6, 2004
    Assignees: Matsushita Electric Industrial Co., LTD, CBL Technologies, Inc.
    Inventors: Glenn S. Solomon, David J. Miller, Tetsuzo Ueda
  • Patent number: 6613162
    Abstract: The present application discloses a method for preparing a homogeneous ternary or quaternary alloy from a quaternary melt. The method includes providing a family of phase diagrams for the quaternary melt which shows (i) composition/temperature data, (ii) tie lines connecting equilibrium liquid and solid compositions, and (iii) isotherms representing boundaries of a miscibility gap. Based on the family of phase diagrams, a quaternary melt composition and an alloy growth temperature is selected. A quaternary melt having the selected quaternary melt composition is provided and a ternary or quaternary alloy is grown from the quaternary melt at the selected alloy growth temperature. A method for making homogeneous ternary or quaternary alloy from a ternary or quaternary melt is also disclosed, as are homogeneous quaternary single-crystal alloys which are substantially free from crystal defects and which have the formula AxB1−xCyD1−y, x and y being the same or different and in the range of 0.001 to 0.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: September 2, 2003
    Assignee: Rensselaer Polytechnic Institute
    Inventors: Partha S. Dutta, Thomas R. Miller
  • Patent number: 6572700
    Abstract: An apparatus and method of providing a large semiconductor crystal at a low cost are provided. The apparatus of producing a semiconductor crystal includes a reactor tube having an open end at least one end side, formed of any one material selected from the group consisting of silicon carbide, silicon nitride, aluminum nitride, and aluminum oxide, or of a composite material with any one material selected from the group consisting of silicon carbide, silicon nitride, aluminum nitride, boron nitride, aluminum oxide, magnesium oxide, mullite, and carbon as a base, and having an oxidation-proof or airtight film formed on the surface of the base, a kanthal heater arranged around the reactor tube in the atmosphere, a flange attached at the open end to seal the reactor tube, and a crucible mounted in the reactor tube to store material of a semiconductor crystal. The material stored in the crucible is heated and melted to form material melt. The material melt is solidified to grow a semiconductor crystal.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: June 3, 2003
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tomohiro Kawase, Katsushi Hashio, Shin-ichi Sawada, Masami Tatsumi
  • Patent number: 6482672
    Abstract: A method for growing InxGa1−xAs epitaxial layer on a lattice mismatched InP substrate calls for depositing by organo-metallic vapor phase epitaxy, or other epitaxial layer growth technique, a plurality of discreet layers of InAsyP1−y over an InP substrate. These layers provide a buffer. Each succeeding buffer layer has a distinct composition which produces less than a critical amount of lattice mismatch relative to the preceding layer. An InxGa1−xAs epitaxial layer is grown over the buffer wherein 0.53≦x≦0.76. A resulting InGaAs structure comprises an InP substrate with at least one InAsP buffer layer sandwiched between the substrate and the InGaAs epitaxial layer. The buffer layer has a critical lattice mismatch of less than 1.3% relative to the substrate. Additional buffer layers will likewise have a lattice mismatch of no more than 1.3% relative to the preceding layer.
    Type: Grant
    Filed: November 5, 1998
    Date of Patent: November 19, 2002
    Assignee: Essential Research, Inc.
    Inventors: Richard W. Hoffman, David M. Wilt
  • Patent number: 6440212
    Abstract: A process of making thermoelectric coolers by direct printing of n- and p-type semiconductor materials suitable for making thermoelectric coolers is disclosed. Micro Jet Printing of arrays on n and p-type materials belong to conductive site pads on non-conductive substrate and crystalization of these materials in the preferred direction as they cool produces thermoelectric cooler components without the need for sawing and machining operations. A non-conductive top substrate having conductive bonding pads is secured to the tops of the columns n and p-type semiconductor materials thereby forming an electrical and physical bond to make a thermoelectric cooler package.
    Type: Grant
    Filed: February 27, 2001
    Date of Patent: August 27, 2002
    Assignee: MicroFab Technologies, Inc.
    Inventor: Donald J. Hayes
  • Patent number: 6358316
    Abstract: In a method for producing a semiconductor device, a compound semiconductor cap layer including no aluminum is grown on a compound semiconductor layer including aluminum, a mask pattern insulating film is formed on a part of the compound semiconductor cap layer, the compound semiconductor wafer with the insulating mask pattern is immersed in an ammonium sulfide solution, the compound semiconductor wafer is selectively etched away using a chlorine containing gas in a reaction chamber, and a groove formed in the etching process is filled with a compound semiconductor layer grown in the reaction chamber by MOCVD. Therefore, a regrowth interface on which no impurity is segregated is attained, improving the quality of the regrown crystal layer.
    Type: Grant
    Filed: August 9, 1995
    Date of Patent: March 19, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hirotaka Kizuki, Norio Hayafuji, Tatsuya Kimura
  • Patent number: 6294018
    Abstract: The specification describes a lithographic technique in which alignment marks are defined in a first semiconductor layer and the alignment marks are then covered with a protective SiO2 layer. After subsequent semiconductor layer growth steps, which selectively deposit on the former semiconductor layer but not on the protective layer, the alignment marks remain undistorted and visible to the exposure tool for subsequent processing.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: September 25, 2001
    Assignee: Lucent Technologies
    Inventors: Robert Alan Hamm, Rose Fasano Kopf, Christopher James Pinzone, Robert William Ryan, Alaric Tate
  • Publication number: 20010023022
    Abstract: A high quality Group III-V compound semiconductor wafer is provided which is free from precipitation of a Group V element on its surface. In the group III-V compound semiconductor wafer of the present invention, the number of acid material atoms per 1 cm2 is at most 5×1012.
    Type: Application
    Filed: February 8, 2001
    Publication date: September 20, 2001
    Inventors: Takayuki Nishiura, Hideki Miyajima
  • Patent number: 6287478
    Abstract: An optical dome or window formed of a composition which is transmissive to infrared frequencies in the range of from about 1 micron to about 14 microns and which is relatively opaque to substantially all frequencies above about 14 microns consisting essentially of a compound taken from the class consisting of group III-V compounds doped with an element taken from the class consisting of shallow donors and having less than about 1×107 atoms/cc impurities and having less than about 1×1015 parts carbon. The shallow donors are Se, Te and S, preferably Se, with the Se concentration from 5×1015 atoms/cc to 2×1016 atoms/cc. The group III-V compound is preferably GaAs or GaP.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: September 11, 2001
    Assignee: Raytheon Company
    Inventor: Paul Klocek
  • Patent number: 6277297
    Abstract: An optical dome or window formed of a composition which is transmissive to infrared frequencies in the range of from about 1 micron to about 14 microns and which is relatively opaque to substantially all frequencies above about 14 microns consisting essentially of a compound taken from the class consisting of group III-V compounds doped with an element taken from the class consisting of shallow donors and having less than about 1×107 atoms/cc impurities and having less than about 1×1015 parts carbon. The shallow donors are Se, Te and S, preferably Se, with the Se concentration from 5×1015 atoms/cc to 2×1016 atoms/cc. The group III-V compound is preferably GaAs or GaP.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 21, 2001
    Assignee: Raytheon Company
    Inventor: Paul Klocek
  • Patent number: 6273949
    Abstract: A method for fabricating gallium arsenide (GaAs) based structure groups with inverted crystallographic orientation to form wavelength converters that utilizes germanium as a crystallographic neutral template layer deposited on a GaAs substrate. A crystallographic inverted gallium arsenide layer is grown on top of the template layer. In a selective trench etching process areas of the substrate are exposed again for a consecutive collective deposition of GaAs.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: August 14, 2001
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Loren A. Eyres, Martin M. Fejer, Christopher B. Ebert, James S. Harris
  • Patent number: 6254677
    Abstract: An apparatus for and method of producing a large semiconductor crystal at a low cost are provided. The apparatus for producing a semiconductor crystal includes a reactor (1) having an open end at both ends thereof, that is formed of any material selected from the group consisting of silicon carbide, silicon nitride, aluminum nitride, and aluminum oxide, or of a composite material including a base material selected from the group consisting of silicon carbide, silicon nitride, aluminum nitride, boron nitride, aluminum oxide, magnesium oxide, mullite, and carbon as a base, and including an oxidation-proof or airtight film formed on the surface of the base. The apparatus further includes a resistance heater (3) arranged around the reactor (1) in the atmosphere, a flange (9) attached at the open end to seal the reactor (1), and a crucible (2) mounted in the reactor (1) to store material of a semiconductor crystal. The material stored in the crucible (2) is heated and melted to form a material melt (60).
    Type: Grant
    Filed: December 21, 1998
    Date of Patent: July 3, 2001
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Katsushi Hashio, Shin-ichi Sawada, Masami Tatsumi
  • Patent number: 6238482
    Abstract: A method of making a wafer is provided. A first semiconductor film is formed onto a semiconductor substrate. An epitaxial film is formed onto an epitaxial wafer. The epitaxial wafer is placed with the epitaxial film on the first semiconductor film. The epitaxial film is debonded from the EPI wafer. The epitaxial film is bonded to the first semiconductor film.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: May 29, 2001
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Kramadhati V. Ravi
  • Patent number: 6231668
    Abstract: A method for manufacturing and calibrating a scale in the nanometer range for technical devices which are used for the high-resolution or ultrahigh-resolution imaging of structures, and such a scale. To construct the scale, at least two different crystalline or amorphous materials are used, which, when imaged, are easily distinguished from one another by their contrast. These material layers are deposited using a suitable material deposition method as a heterolayer sequence onto a substrate material. The produced heterolayer sequence is characterized experimentally using an analysis method that is sensitive to the individual layer thicknesses of the heterolayer sequence. The data obtained from the analysis method are evaluated and recorded. The layer structure is exposed by splitting open the heterolayer sequence in the deposition direction.
    Type: Grant
    Filed: February 6, 1997
    Date of Patent: May 15, 2001
    Assignee: Deutsche Telekom AG
    Inventors: Rainer Loesch, Hartmut Hillmer, Winfried Schlapp, Armin Poecker, Walter Betz, Rainer Goebel
  • Patent number: 6184144
    Abstract: New methods for growing threading dislocation free heteroepitaxy are proposed and investigated theoretically. The first method contains four key steps: Stranski-Krastanov island formation, strain relaxation by defect nucleation, in-situ defect removal, and island coalescence. The central idea is that the defects are utilized to relax the lattice strain, and as soon as the strain is relaxed, the dislocation segments are removed that will propagate to the surface of the film. As a result, the heteroepitaxial film is expected to be relaxed but be free of harmful threading dislocations regardless of the degree of lattice mismatch. In the second method, single crystal islands or patches are grown initially which are a few hundred nanometers or less in diameter. The patches serve as nucleation sites for growth of single crystal heteroepitaxial layers. Because of the very small patch size, the stress (normal stress and shear stress) due to lattice mismatch will be reduced significantly.
    Type: Grant
    Filed: October 6, 1998
    Date of Patent: February 6, 2001
    Assignee: Cornell Research Foundation, Inc.
    Inventor: Yu-Hwa Lo
  • Patent number: 6180269
    Abstract: A GaAs single crystal substrate and an epitaxial wafer using the same suppress the generation of slips during growth of the epitaxial layer, and improve the breakdown withstanding characteristic of devices fabricated on such substrates. The GaAs single crystal substrate has a mean dislocation density in plane of at most 2×104 cm−2, a carbon concentration of 2.5 to 20.0×1015 cm−3, a boron concentration of 2.0 to 20.0×1016 cm−3, an impurity concentration other than carbon and boron of at most 1×1017 cm−3, an EL2 concentration of 5.0 to 10.0×1015 cm−3, resistivity of 1.0 to 5.0×108 &OHgr;·cm and a mean residual strain measured by photoelastic analysis of at most 1.0×10−5.
    Type: Grant
    Filed: June 16, 1999
    Date of Patent: January 30, 2001
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshiaki Hagi, Ryusuke Nakai
  • Patent number: 6179912
    Abstract: Provided is a system and continuous flow process for producing monodisperse semiconductor nanocrystals comprising reservoirs for the starting materials, a mixing path in which the starting materials are mixed, a first reactor in which the mixture of starting materials is mixed with a coordinating solvent and in which nucleation of particles occurs, a second reactor in which controlled growth of the nanocrystals occurs, and a growth termination path in which the growth of the nanocrystals is halted.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: January 30, 2001
    Assignee: BioCrystal Ltd.
    Inventors: Emilio Barbera-Guillem, Marlin O. Thurston
  • Patent number: 6146457
    Abstract: A method for producing thick, high quality GaN substrates uses an epitaxially deposited film is used as a substrate material for further device or epitaxial processing. The film is deposited using an epitaxial technique on a thin substrate called the disposable substrate. The deposited film is thick enough so that upon cooling the thermal mismatched strain is relieved through cracking of the lower disposable substrate and not the newly deposited epitaxy. The epitaxial film now becomes a platform for either further epitaxial deposition or device processing.
    Type: Grant
    Filed: July 2, 1998
    Date of Patent: November 14, 2000
    Assignee: CBL Technologies, Inc.
    Inventor: Glenn S. Solomon
  • Patent number: 6106613
    Abstract: In a semiconductor substrate comprising a silicon substrate having a porous region, and a semiconductor layer provided on the porous region, the semiconductor layer comprises a single-crystal compound and is formed on the surface of the porous region with its pores having been sealed at the surface. This substrate can be produced by a process comprising the steps of heat-treating the silicon substrate 11 having a porous region, to seal pores at the surface of the porous region 13, and forming a single-crystal compound-semiconductor layer 14 by heteroepitaxial growth on the porous region having the pores sealed by the heat treatment.Single-crystal compound semiconductor films with less crystal defects can be formed on large-area silicon substrates in a high productivity, a high uniformity, a high controllability and a great economical advantage.
    Type: Grant
    Filed: March 12, 1998
    Date of Patent: August 22, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuhiko Sato, Takao Yonehara
  • Patent number: 6099640
    Abstract: A method of promoting evaporation of excess indium from a surface of an indium containing compound semiconductor single crystal layer during a discontinuation of a molecular beam epitaxial growth. Substantial supply of all elements for the indium containing compound semiconductor single crystal layer are stopped at least until a substrate temperature rises to a predetermined temperature of not less than an indium re-evaporation initiation temperature.
    Type: Grant
    Filed: September 3, 1998
    Date of Patent: August 8, 2000
    Assignee: NEC Corporation
    Inventor: Hitoshi Negishi
  • Patent number: 6071337
    Abstract: A method and apparatus for producing crystals by the Czochralski method whereby the thermal history during crystal growth according to the CZ method can be controlled with ease and accuracy. The apparatus comprises a crucible for receiving a raw material, a heater for heating and melting the raw material, and a heat insulating cylinder disposed so as to surround the crucible and the heater, wherein a portion of the heat insulating cylinder that is located above an upper end of the heater is so configured that its inner diameter is larger than the outer diameter of the heater at its lower end, and that its inner diameter at its upper end is equal to or less than the inner diameter of the heater while its outer diameter is equal to or greater than the outer diameter of the heater. This apparatus is used to produce crystals and to control the temperature distribution inside the crystal producing apparatus or the thermal history of crystals.
    Type: Grant
    Filed: August 14, 1998
    Date of Patent: June 6, 2000
    Assignee: Shin-Etsu Handotai Co., Ltd
    Inventors: Masahiro Sakurada, Yuichi Miyahara, Tomohiko Ohta
  • Patent number: 6066204
    Abstract: An apparatus and method is disclosed for providing vapor-phase epitaxial growth on a substrate using a Metal Organic Chemical Vapor Deposition (MOCVD) process. The process is performed in a reactive chamber pressurized to greater than one atmosphere. The reactant gases to be deposited on the substrate are also pressurized to the equivalent pressure, and then introduced into the reactor chamber. By performing the MOCVD process at a pressure greater than one atmosphere, a reduced amount of reactant gas is required to complete the deposition process.
    Type: Grant
    Filed: January 8, 1997
    Date of Patent: May 23, 2000
    Assignee: Bandwidth Semiconductor, LLC
    Inventor: Victor E. Haven
  • Patent number: 6048397
    Abstract: A GaAsP epitaxial wafer 10 which has a GaAs.sub.1-x P.sub.x (0.45<x<1) constant nitrogen concentration layer 6 formed by doping a constant composition layer with nitrogen wherein the constant nitrogen concentration layer 6 has the following upper and lower limits of nitrogen concentration:Upper limit: N=(6.25x-1.125).times.10.sup.18 cm.sup.-3Lower limit: N=(5x-1.5).times.10.sup.18 cm.sup.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: April 11, 2000
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masahisa Endo, Masataka Watanabe, Tsuneyuki Kaise, deceased
  • Patent number: 6036771
    Abstract: In a method of manufacturing an optical semiconductor device having a semiconductor substrate, an optical waveguide formed by a semiconductor layer is formed on the semiconductor substrate by the use of the selective metal-organic vapor phase epitaxy including source materials. The source materials are intermittently supplied in the selective metal-organic vapor phase epitaxy.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: March 14, 2000
    Assignee: NEC Corporation
    Inventor: Yasutaka Sakata
  • Patent number: 6019840
    Abstract: A reduced temperature low pressure metal organic chemical vapor deposition process for the production of semi-insulating deep level impurity undoped Group III-V phosphorous containing epitaxial layers. The present invention achieves production of semi-insulating layers at reduced growth temperatures in the approximate range of 490.degree. C. to 530.degree. C. Semi-insulating resistivities on the order of 10.sup.6 ohm-cm to 10.sup.9 ohm-cm are obtained according to the present process without resort to use of extrinsic dopants such as the transition metals typically used in conventional processes to obtain semi-insulating phosphorous containing layers, and without post processing annealing.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: February 1, 2000
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Quesnell J. Hartmann, Gregory E. Stillman
  • Patent number: 6010638
    Abstract: A composition of matter comprising a bulk material of uniform composition having first and second spaced apart surface regions and a dopant in the bulk material of progressively increasing concentration in a direction from the first to said second surface regions providing an interface intermediate the first and second surface regions wherein the portion of the bulk material on one side of the interface is electrically conductive and the portion of the bulk material on the other side of the interface is relatively electrically insulative. The bulk material is one of Ge, Si, group II-VI compounds and group III-V compounds and preferably GaAs or GaP. The dopant is a shallow donor for the bulk material involved and for GaAs and GaP is Se, Te or S. The ratio of the resistivity of the portion of the bulk material on one side of the interface to the portion of the bulk material on the other side of the interface is at least about 1:10.sup.7.
    Type: Grant
    Filed: November 17, 1992
    Date of Patent: January 4, 2000
    Assignee: Raytheon Company
    Inventor: Paul Klocek
  • Patent number: 5951754
    Abstract: A method of fabricating a semiconductor quantum box uniform in size and free from processing damages comprising the steps of adsorbing elements classified in VI family of the periodic table onto the surface of a single or multi-quantum well structure composed of semiconductors; growing crystallites of a semiconductor or a metal by liquid-drop epitaxy; applying chemical etching to the single or multi-quantum well structure with the use of the crystallites as a mask, thereby removing areas of the single or multi-quantum well structure where the crystallites haven't grown on the surface; removing the crystallites used as mask by chemical etching; and filling a semiconductor into the areas of the single or multi-quantum well structure removed in the afore step.
    Type: Grant
    Filed: September 18, 1997
    Date of Patent: September 14, 1999
    Assignee: National Research Institute for Metals
    Inventors: Nobuyuki Koguchi, Keiko Ishige, Katsuyuki Watanabe, Chea Deak Lee
  • Patent number: 5919305
    Abstract: A concept and process is disclosed by which an epitaxially deposited film is removed from its substrate at elevated temperatures to inhibit thermal mismatch strain induced defect generation in the epitaxial layer. The process occurs by gas phase reactions of an intermediate layer purposely deposited to react with a component in the gas stream during or after epitaxial growth. While the concept of an intermediate layer has been used extensively to improve the crystal quality of the epitaxial layer this is not the purpose of this interlayer. Although this interlayer may aid in nucleation of the epitaxial layer, the objective is to separate the epitaxial material on top of the interlayer from the substrate below the interlayer at or near the growth temperature to reduce the effects of the thermal mismatch between the substrate and epitaxial layers. An application is an addition to the above invention. A thick epitaxially deposited film can now be removed from its substrate at elevated temperatures.
    Type: Grant
    Filed: July 2, 1998
    Date of Patent: July 6, 1999
    Assignee: CBL Technologies, Inc.
    Inventor: Glenn S. Solomon
  • Patent number: 5888294
    Abstract: An improved epitaxial growth rate varying method for a side surface of a semiconductor pattern capable of controlling a growth rate of a side surface of a semiconductor pattern by controlling the amount of CCl.sub.4 gas supplied when forming an epitaxial layer on a patterned GaAs substrate in a metalorganic chemical deposition method, thus fabricating a desired quantum wire, and which is characterized by controlling a side-surface growth rate of an epitaxial layer in accordance with the CCl.sub.4 doping gas flow rate while an epitaxial layer is formed on a patterned GaAs substrate in a metalorganic chemical deposition method and in achieving a desired substantial flatness.
    Type: Grant
    Filed: March 1, 1996
    Date of Patent: March 30, 1999
    Assignee: Korea Institute of Science and Technology
    Inventors: Suk-Ki Min, Moo Sung Kim, Yong Kim
  • Patent number: 5865888
    Abstract: A semiconductor device epitaxial layer lateral growth rate control method using CBr.sub.4 gas involves regulating an epitaxial layer lateral growth rate in accordance with the CBr.sub.4 amount doped into the epitaxial layer during the epitaxial layer growth occurring on a patterned GaAs substrate by means of a metalorganic chemical vapor deposition (MOCVD) process. The lateral growth rate may be regulated by varying the growth temperature and the V/III doping ratio.
    Type: Grant
    Filed: July 22, 1996
    Date of Patent: February 2, 1999
    Assignee: Korea Institute of Science and Technology
    Inventors: Suk-Ki Min, Moo sung Kim, Seong-Il Kim
  • Patent number: 5853477
    Abstract: There is disclosed a method of producing, in large volumes and at low cost, Ta, Nb, Zr and Hf carbide, nitride or carbonitride whiskers, preferably submicron, having excellent reinforcing properties, suitable as reinforcement in a wide range of materials, including metals, intermetallics, plastics, ceramics and metallic bonded hard material. Oxides of Ta, Nb, Zr and Hf or alkali compounds thereof in an amount to satisfy the stoichiometric requirements of the desired carbide or nitride are mixed with the carbon source along with an alkali and/or alkali earth metal halogenide as a volatilization agent for the metal and a catalyst for the whisker growth such as Ni and/or Co. The reactant powders are blended in some typical manner using a high speed blender so as to intimately mix them. Finally, the starting material is subjected to nitriding, carbonizing or carbonitriding heat treatments in order to produce the desired whiskers.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: December 29, 1998
    Assignees: Sandvik AB, Advanced Industrial Materials
    Inventors: R. Tom Coyle, Magnus Ekelund, Mats Nygren, Mats Johnsson
  • Patent number: 5827365
    Abstract: A vapor phase growth process for the fabrication of a thin film form of compound semiconductor of elements of Groups III-V, using a halogen element-free hydride and a halogen element-free organic metal as the source materials for growth, is characterized in that a halide gas and/or a halogen gas that are free from the mother elements of the compound to be grown are added to the reaction atmosphere while the compound is growing. A trace amount(s) of the halide and/or halogen gas(es) that are free from the mother elements of the compound to be grown, such as HCl, is added to the reaction atmosphere while the compound is growing, thereby making it possible to flatten the heterojunction interface or effect the growth of high-quality crystals without deposition of polycrystals on a mask over a wide range.
    Type: Grant
    Filed: January 23, 1995
    Date of Patent: October 27, 1998
    Assignee: Mitsubishi Kasei Corporation
    Inventors: Kenji Shimoyama, Hideki Gotoh
  • Patent number: 5824151
    Abstract: The method of forming a III-V group compound semiconductor crystalline layer on a semiconductor crystal containing at least V-group compound, includes the steps of: performing the crystal growth of the III-V compound semiconductor crystalline layer; and supplying an n-type dopant and a material compound containing a V-group element onto the semiconductor crystal without causing the crystal growth of the III-V compound semiconductor crystalline layer.
    Type: Grant
    Filed: May 21, 1997
    Date of Patent: October 20, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Nobuhiro Ohkubo
  • Patent number: 5759264
    Abstract: A method for a vapor-phase growth of a GaAs.sub.1-x P.sub.x epitaxial layer having a uniform thickness is disclosed. This method allows the GaAs.sub.1-x P.sub.x epitaxial layer (wherein x stands for an alloy composition satisfying the expression, 0.ltoreq.x.ltoreq.1) to be formed on a plurality of semiconductor single crystal substrates 1 by setting the semiconductor single crystal substrates 1 in place on a wafer holder 16 disposed inside a vapor-phase growth apparatus 30 in an amount of not less than 70% as the covering ratio of the total surface area of the substrates to the surface area of the wafer holder 16.
    Type: Grant
    Filed: March 21, 1996
    Date of Patent: June 2, 1998
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masataka Watanabe, Tsuneyuki Kaise, Masayuki Shinohara, Masahisa Endo
  • Patent number: 5759266
    Abstract: In a method for growing a CdTe layer on a clean surface of a Si substrate, the clean surface of the Si substrate is subjected to an irradiation of As at a temperature in the range of about 650.degree. C. to about 800.degree. C. so that Si atoms on terrace of the clean surface are replaced by As atoms, followed by carrying out a molecular beam epitaxy to grow a CdTe layer on the surface. It is preferable that the clean surface is subjected to an irradiation of Cd in addition to the irradiation of As.
    Type: Grant
    Filed: October 3, 1995
    Date of Patent: June 2, 1998
    Assignee: NEC Corporation
    Inventor: Masaya Kawano
  • Patent number: 5738721
    Abstract: A chemical composition consists essentially ((t-amyl)GaS).sub.4. The chemical composition can be employed as a liquid precursor for metal organic chemical vapor deposition to thereby form a cubic-phase passivating/buffer film, such as gallium sulphide.
    Type: Grant
    Filed: April 6, 1995
    Date of Patent: April 14, 1998
    Assignees: President and Fellows of Harvard College, Triquint Semiconductor, Inc.
    Inventors: Andrew R. Barron, Michael B. Power, Andrew N. MacInnes