Abstract: Atomic layer deposition is used to provide a solid film on a plurality of disc shaped substrates. The substrates are entered spaced apart in a boat, in a furnace and heated to deposition temperature. In the furnace the substrate is exposed to alternating and sequential pulses of at least two mutually reactive reactants, in such way that the deposition temperature is high enough to prevent condensation of the at least two reactants on the surface but not high enough to result in significant thermal decomposition of each of the at least two reactants individually.

Abstract: The present invention is related to a method of crystallizing an amorphous silicon layer and a crystallizing apparatus thereof which crystallize an amorphous silicon layer using plasma. The present invention includes the steps of depositing an inducing substance for silicon crystallization on an amorphous silicon layer by plasma exposure, and carrying out annealing on the amorphous silicon layer to the amorphous silicon layer. The present invention includes a chamber having an inner space, a substrate support in the chamber wherein the substrate support supports a substrate, a plasma generating means in the chamber wherein the plasma generating means produces plasma inside the chamber, and a heater at the substrate support wherein the heater supplies the substrate with heat.

Abstract: A method of forming a three-dimensional (3D) complete photonic bandgap crystal by crystal modification is disclosed. The 3D crystal includes a first periodic array of unit cells formed from first voids connected by imaginary bonds. The first periodic array forms an incomplete bandgap. The first voids may be formed in any one of a number of shapes, including spherical. The 3D crystal further includes a second periodic array of second voids. The second voids are arranged along the imaginary bonds so as to modify each unit cell. The modification of the unit cells is designed to form a complete photonic bandgap.

Abstract: A substrate is positioned within a deposition chamber. Trimethylsilane is flowed to the chamber and a first inert gas is flowed to the chamber under conditions effective to chemisorb a first species monolayer comprising silicon onto the substrate. The first inert gas is flowed at a first rate. After forming the first species monolayer, an oxidant is flowed to the chamber and a second inert gas is flowed to the chamber under conditions effective to react the oxidant with the chemisorbed first species and form a monolayer comprising silicon dioxide on the substrate. The second inert gas flowing is at a second rate which is less than the first rate. The a) trimethylsilane and first inert gas flowing and the b) oxidant and second inert gas flowing are successively repeated effective to form a silicon dioxide comprising layer on the substrate. Other implementations and aspects are contemplated.

Abstract: A method of growing a thin film onto a substrate placed in a reaction chamber according to the ALD method by subjecting the substrate to alternate and successive surface reactions. The method includes providing a first reactant source and providing an inactive gas source. A first reactant is fed from the first reactant source in the form of repeated alternating pulses to a reaction chamber via a first conduit. The first reactant is allowed to react with the surface of the substrate in the reaction chamber. Inactive gas is fed from the inactive gas source into the first conduit via a second conduit that is connected to the first conduit at a first connection point so as to create a gas phase barrier between the repeated alternating pulses of the first reactant entering the reaction chamber. The inactive gas is withdrawn from said first conduit via a third conduit connected to the first conduit at a second connection point.

Abstract: An amorphous silicon pattern is formed first. A first region, a second region, at least one first pointed region adjacent to the second region and having a second height, at least one fourth region between the first region and each first pointed region are included in the amorphous silicon pattern. Each fourth region has a fourth height smaller than the second height. A laser crystallization process is performed to form a first single crystal silicon grain in each fourth region.

Abstract: A CVD method deposits conformal metal layers on small features of a substrate surface. The method includes three principal operations: depositing a thin conformal layer of precursor over some or all of the substrate surface; oxidizing the precursor to convert it to a conformal layer of metal oxide; and reducing some or all of the metal oxide to convert it to a conformal layer of the metal itself. The conformal layer of precursor may form a “monolayer” on the substrate surface. Examples of metals for deposition include copper, cobalt, ruthenium, indium, and rhodium.

Abstract: A device substrate is provided having: a Si(111) substrate; a buffer layer formed by epitaxial growth on the Si(111) substrate 11, and containing at least one of a rare earth metal oxide and an alkali earth metal oxide; and a semiconductor material layer formed by epitaxial growth on the buffer layer, and containing at least one of a group II–VI semiconductor material having a wurtzite structure and a group III–V semiconductor material having a wurtzite structure. The buffer layer preferably comprises a hexagonal crystal structure oriented in the (001) plane or a cubic crystal structure oriented in the (111) plane, and the semiconductor material layer preferably comprises a hexagonal crystal structure oriented in the (001) plane.

Abstract: A reaction prevention layer is formed to prevent Si from reacting with a gallium nitride group semiconductor (semiconductor crystal A) which is deposited after the reaction prevention layer is formed. By forming a reaction prevention layer comprising a material whose melting point or thermal stability is higher than that of a gallium nitride group semiconductor, e.g., AlN, on a sacrifice layer, a reaction part is not formed in the semiconductor substrate deposited on the reaction prevention layer when the gallium nitride group semiconductor is grown by crystal growth for a long time. In short, owing to the effect that the reaction prevention layer prevents silicon (Si) from diffusing, the reaction part is generated only in the sacrifice layer and it is never formed at the upper portion of the reaction prevention layer even by growing the semiconductor crystal A at a high temperature for a long time.

Abstract: In a semiconductor element comprising microcrystalline semiconductor, a semiconductor junction is provided within a microcrystal grain. Further, in a semiconductor element comprising microcrystalline semiconductor, microcrystal grains of different grain diameters are provided as a mixture to form a semiconductor layer. Thereby, discontinuity of a semiconductor junction is lessened to thereby improve the characteristics, durability, and heat resisting properties of a semiconductor element. Distortion in a semiconductor layer is also reduced.

Abstract: At the time of selective growth of an active layer on a substrate, crystal is previously grown in an active layer non-growth region, and the active layer is grown in an active layer selective growth region. With this configuration, a source supplied to the non-growth region is incorporated in the deposited crystal from the initial stage of growth, so that the supplied amount of the source to the active layer selective growth region is kept nearly at a constant value over the entire period of growth of the active layer, to eliminate degradation of characteristics of the device due to a variation in growth rate of the active layer. In particular, the selective growth method is effective in fabrication of a semiconductor light emitting device including a cladding layer, a guide layer, and an active layer, each of which is formed by selective growth, wherein the active layer has multiple quantum wells.

Abstract: A seed layer as a laminate of a GaN layer (second seed layer) and an AlN buffer layer (first seed layer) is formed on a sapphire substrate. A front surface thereof is etched in the form of stripes with a stripe width (seed width) of about 5 ?m, a wing width of about 15 ?m and a depth of about 0.5 ?m. As a result, mesa portions each shaped like nearly a rectangle in sectional view are formed. Non-etched portions each having the seed multilayer as its flat top portion are arranged at arrangement intervals of L?20 ?m. Part of the sapphire substrate is exposed in trough portions of wings. The ratio S/W of the seed width to the wing width is preferably selected to be in a range of from about ? to about ?. Then, a semiconductor crystal A is grown to obtain a thickness of not smaller than 50 ?m. The semiconductor crystal is separated from the starting substrate to thereby obtain a high-quality single crystal independent of the starting substrate.

Abstract: A method of forming a free-standing (Al, Ga, In)N article, by the steps including: providing an expitaxially compatible sacrificial template; depositing single crystal (Al, Ga, In)N material on the template to form a composite sacrificial template/(Al, Ga, In)N article including an interface between the sacrificial template and the (Al, Ga, In)N material; and interfacially modifying the composite sacrificial template/(Al, Ga, In)N article to part the sacrificial template from the (Al, Ga, In)N material and yield the free-standing (Al, Ga, In)N article. The free-standing (Al, Ga, In)N article produced by such method is of superior morphological character, and suitable for use as a substrate, e.g., for fabrication of microelectronic and/or optoelectronic devices and device precursor structures.

Abstract: The invention relates to a method for improving the efficiency of epitaxially grown quantum dot semiconductor components having at least one quantum dot layer. The efficiency of semiconductor components containing an active medium consisting of quantum dots is often significantly below the theoretically possible values. The inventive method enables the efficiency of the relevant component to be clearly increased without substantially changing the growth parameters of the various epitaxial layers. In order to improve the efficiency of the component, the crystal is morphologically changed when the growth of the component is interrupted at the point in the overall process at which the quantum dots of a layer have just been covered. The growth front is smoothed at the same time, leading to, for example, a reduction in waveguide loss as the thickness of the waveguide is more homogeneous if the relevant component has one such waveguide.

Abstract: A method for forming a double density wordline. A semiconductor substrate having a poly layer, a first insulating layer, a first dummy poly layer, and a second insulating layer is provided. The second insulating layer and the first dummy poly layer separated by an opening are a first wordline mask and a second wordline mask respectively. A spacer is formed on a sidewall of the opening, and the opening is filled with a second dummy poly layer. The spacer, the second insulating layer, and the exposed first insulating layer are removed to form a third wordline mask, the third wordline is composed of the second dummy poly layer and the unexposed first insulating layer. The poly layer is etched to form a first wordline, a second wordline, and a third wordline using the first wordline mask, the second wordline mask, and the third wordline mask as etching masks.

Abstract: A photonic crystal manufacturing method exposes two or more silver halide particle layers that contain silver halide particles which have different spectral sensitivity characteristics for each of the silver halide particle layers to light having wavelengths corresponding to the respective different spectral sensitivity characteristics, and then develops the exposed silver halide particle layers to form therein a periodic structure with an aggregate of developed silver. Photonic crystals can be manufactured with relative ease in a relatively short period of time. This method assures continued high accuracy.

Abstract: The present invention is a tunneling magnetoresistive (TMR) stack configured to operate in a current-perpendicular-to-plane (CPP) mode, wherein a sense current flows substantially perpendicular to a longitudinal plane of the barrier layer. The TMR stack has a plurality of layers including a barrier layer. The barrier layer may made of titanium and may be oxidized with an aggressive oxidation method, such as with UV illumination, for a predetermined time period. The barrier layer may be formed on a first ferromagnetic layer before oxidation, and then a second ferromagnetic layer may be formed on the oxidized barrier layer. The TMR stack exhibits an increased magnetoresistive (MR) ratio, a lower RA product, a higher breakdown voltage of the TMR stack, and greater thermal stability.

Abstract: Provided is a nitride semiconductor device with high reliability and high flexibility in design and manufacture of the device. The nitride semiconductor device comprises a seed crystal portion (11) formed on a sapphire substrate (10) and having a mask (12) on one side surface thereof, and a GaN layer (15) grown on the sapphire substrate (10) and the seed crystal portion (11) through epitaxial lateral overgrowth. The GaN layer (15) is grown only from an exposed side surface of the seed crystal portion (11) which is not covered with the mask (12), so the lateral growth of the GaN layer (15) is asymmetrically carried out. Thereby, a meeting portion (32) is formed in the vicinity of a boundary between the seed crystal portion (11) and the mask (12) in a thickness direction of the GaN layer (15).

Abstract: The present invention deals with the generation of sharp single crystal diamond tips and the arrays of these tips, and their fabrication technology. The invention combines the deposition of synthetic diamond films with reactive etching processes. Upon the diamond orientation prepared and reactive etching environment with considerable directivity of ions, single crystal diamond tips with different apical angles can be fabricated. Very sharp diamond tips with an apical angle of no more than about 28° and a tip radius smaller than 50 nm are fabricated on pyramidal-shaped [001]-textured diamond films by subsequent reactive etching., The technology is based on selective etching of sp2- and sp3- hybridized carbons by the activated constituents of an etching environment, in particular based on atomic hydrogen, in a way similar to ion bombardment, which contributes to overall etching and local conversion of diamond to graphitic phase promoting further etching with chemically activated species.

Abstract: A method of producing a semiconductor device which removes catalyst elements from a silicon-containing semiconductor film while maintaining the advantage of low temperature process is provided. The method comprises the steps of: forming an amorphous semiconductor film containing silicon on a glass substrate to crystallize it by using a catalyst element; selectively introducing into the amorphous semiconductor film an impurity belonging to Group 15 to form gettering regions and regions to be gettered; and causing the catalyst element in the silicon film to move to the gettering regions by heat treatment. Through the gettering process, the crystalline silicon film can be obtained in which the concentration of nickel contained therein is sufficiently reduced.

Abstract: A p-type InGaAlN layer, an InGaAlN active layer, and an n-type InGaAlN layer each having a composition represented by (AlxGa1-x)yIn1-yN (0?x?1, 0?y?1) are formed on a sapphire substrate. In the as-grown state, Mg is bonded to hydrogen atoms in the p-type InGaAlN layer. Then, the back surface of the sapphire substrate is irradiated with a laser beam in a nitrogen atmosphere. The resistance of the p-type InGaAlN layer is reduced by removing hydrogen therefrom with irradiation with a weak laser beam. During the irradiation with the laser beam, the diffusion of a dopant in a multilayer portion is suppressed such that a dopant profile retains sharpness. It is also possible to separate the sapphire substrate from the multilayer portion by subsequently using an intense laser beam for irradiation.

Abstract: A method for simultaneous deposition of multiple compounds on a substrate is provided. In one aspect, a gas stream is introduced into a processing chamber and flows across a substrate surface disposed therein. The gas stream includes at least one dose of a first compound and at least one dose of a second compound. The doses of the first and second compounds are separated by a time delay, and the at least one dose of the first compound and the at least one dose of the second compound are simultaneously in fluid communication with the substrate surface.

Abstract: In a semiconductor manufacturing system for manufacturing compound semiconductor by MOCVD, a lead-in member is provided for guiding feed gas supplied from a feed gas supply unit onto the surface of a semiconductor substrate disposed in a reactor, a main body of the lead-in member is constituted as a hollow member to form a feed gas guide passage for conducting the feed gas in an prescribed direction and is formed with multiple orifices, and the feed gas in the feed gas guide passage is jetted from the orifices in a direction perpendicular to the prescribed direction so that the semiconductor substrate is bathed in a feed gas flow of uniform amount jetted from the lead-in member in this manner. Furthermore, a pressure differential produced between the inner side and outer side of the nozzle member enables the feed gas jetted from the nozzle member to flow over the whole surface of the substrate at a uniform flow rate.

Abstract: A method of forming a high quality epitaxial indium phosphide layer on a silicon substrate and a semiconductor device formed by the same method are described. In one aspect, a lead-based perovskite buffer is formed on a silicon substrate, and an epitaxial indium phosphide layer is formed on the lead-based perovskite buffer. In accordance with this approach, relatively large (e.g., up to 300 millimeters in diameter) high quality indium phosphide films may be produced with the relatively high mechanical stability provided by silicon substrates. In this way, intrinsic problems associated with prior approaches that involve growth of high quality indium phosphide thin films on indium phosphide substrates, which are characterized by small wafer size, brittleness and high cost, may be avoided.

Abstract: Methods are disclosed that provide for structures and techniques for the fabrication of ordered arrangements of crystallographically determined nanometer scale steps on single crystal substrates, particularly SiC. The ordered nanometer scale step structures are produced on the top surfaces of mesas by a combination of growth and etching processes. These structures, sometimes referred to herein as artifacts, are to enable step-height calibration, particularly suitable for scanning probe microscopes and profilometers, from less than one nanometer (nm) to greater than 10 nm, with substantially no atomic scale roughness of the plateaus on either side of each step.

Abstract: The present invention relates to oxides on suitable substrates, as converted from nitride precursors.

Abstract: Carbon nanotubes are implemented in a manner that facilitates their orientation and arrangement for a variety of applications. According to an example embodiment of the present invention, an electric field is used to orient carbon nanotubes along a direction of the electric field (e.g., along a direction generally parallel to an electric field applied between two electrodes). In one implementation, the electric field is used to orient a nanotube that has already been grown. In another implementation, the electric field is used in situ, with nanotubes being aligned while they are grown. With these approaches, carbon nanotubes can be selectively oriented for one or more of a variety of implementations. Furthermore, arrays of aligned carbon nanotubes can be formed extending between circuit nodes having both similar and different orientations.

Abstract: The invention relates to a substrate for epitaxy, especially for preparation of nitride semiconductor layers. Invention covers a bulk nitride mono-crystal characterized in that it is a mono-crystal of gallium nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium nitride has a surface area greater than 100 mm2, it is more than 1.0 &mgr;m thick and its C-plane surface dislocation density is less than 106/cm2, while its volume is sufficient to produce at least one further-processable non-polar A-plane or M-plane plate having a surface area at least 100 mm2. More generally, the present invention covers a bulk nitride mono-crystal which is characterized in that it is a mono-crystal of gallium-containing nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium-containing nitride has a surface area greater than 100 mm2, it is more 1.0 &mgr;m thick and its surface dislocation density is less than 106/cm2.

Abstract: Selected micro- and nanoscale, 1-dimensional and 2-dimensional periodic and random structures generated on silicon and other substrates are expected to perform as compliant, thin films for gettering defects and for accommodating lattice and thermal expansion mismatches during heteroepitaxial growth thereon, thereby leading to relatively defect-free, heteroepitaxial films of chosen thicknesses. The as-grown epilayers or completed electronic and optoelectronic devices can be bonded to a second substrate such as glass, or plastic following separation thereof from the substrate on which they were formed using preferential etching of a readily detachable, nanoporous silicon or silicon dioxide layer introduced between the generated structures and the substrate.

Abstract: A method for fabricating a carrier substrate. The technique includes providing a crystalline or mono-crystalline base substrate, growing a stiffening layer on a front face of the base substrate at a thickness sufficient to form a carrier substrate for subsequent processing, and detaching the stiffening layer from the base substrate to obtain the carrier substrate and a remainder of the base substrate. The carrier substrate is suitable for use in growing high quality homo-epitaxial or hetero-epitaxial films thereon.

Abstract: A method of making a Schottky diode comprising the steps of: providing a single crystal diamond comprising a surface; placing the single crystal diamond in a CVD system; heating the diamond to a temperature of at least about 950° C.; providing a gas mixture capable of growing diamond film and comprising a sulfur compound through the CVD system; growing an epitaxial diamond film on the surface of the single crystal diamond; baking the diamond at a temperature of at least about 650° C. in air for a period of time that minimizes oxidation of the diamond; and fabricating a Schottky diode comprising the diamond film. A Schottky diode comprising an epitaxial diamond film and capable of blocking at least about 6 kV in a distance of no more than about 300 &mgr;m.

Abstract: An amorphous silicon pattern is formed first. A first region, a second region, at least one first pointed region adjacent to the second region and having a second height, at least one fourth region between the first region and each first pointed region are included in the amorphous silicon pattern. Each fourth region has a fourth height smaller than the second height. A laser crystallization process is performed to form a first single crystal silicon grain in each fourth region.

Abstract: In a method for manufacturing a crystalline silicon film by utilizing a metal element that promotes the crystallization of silicon, an influence of this metal element can be suppressed. A nickel element 104 is retained in contact with a surface of an amorphous silicon film 103 patterned to form a predetermined pattern in such a manner that the metal element is brought into contact with the amorphous silicon film 103 patterned to form a predetermined pattern. Next, the crystalline silicon film 105 is formed by a heat treatment. At this time, the nickel element is segregated in the edge region of the pattern. Further, a crystalline silicon film 100 having no region to which the metal element concentrated by patterning using a mask 107. By using this crystalline silicon film 100 as an active layer, the thin film transistor is fabricated.

Abstract: A gas turbine component consists of a superalloy base material with a single crystal structure and a protective MCrAlY-coating. The MCrAlY-coating the MCrAlY has a &ggr;/&bgr;-phase and single crystal structure, which is epitaxial with the base material.

Abstract: A method of manufacturing potassium niobate single crystal thin film on a single crystal substrate that epitaxially grows orthorhombic potassium niobate single crystal at a temperature near room temperature at a high deposition rate. A surface acoustic wave element, frequency filter, frequency oscillator, electronics circuit, and electronic device employ the thin film manufactured by the method, and are high in k2, wideband, downsized, and economical in power consumption. The method includes the steps of coating liquid drops of a potassium niobate solution on a SrTiO3 single crystal substrate by a liquid drop emission method, and precipitating potassium niobate single crystal layer by epitaxial growth from the liquid drops.

Abstract: The present invention is related to a method of crystallizing an amorphous silicon layer and a crystallizing apparatus thereof which crystallize an amorphous silicon layer using plasma. The present invention includes the steps of depositing an inducing substance for silicon crystallization on an amorphous silicon layer by plasma exposure, and carrying out annealing on the amorphous silicon layer to the amorphous silicon layer. The present invention includes a chamber having an inner space, a substrate support in the chamber wherein the substrate support supports a substrate, a plasma generating means in the chamber wherein the plasma generating means produces plasma inside the chamber, and a heater at the substrate support wherein the heater supplies the substrate with heat.

Abstract: An Al0.15Ga0.85N layer 2 is formed on a silicon substrate 1 in a striped or grid pattern. A GaN layer 3 is formed in regions A where the substrate 1 is exposed and in regions B which are defined above the layer 2. At this time, the GaN layer grows epitaxially and three-dimensionally (not only in a vertical direction but also in a lateral direction) on the Al0.15Ga0.85N layer 2. Since the GaN layer grows epitaxially in the lateral direction as well, a GaN compound semiconductor having a greatly reduced number of dislocations is obtained in lateral growth regions (regions A where the substrate 1 is exposed).

Abstract: MEMS structure and a method of fabricating them from ultrananocrystalline diamond films having average grain sizes of less than about 10 nm and feature resolution of less than about one micron . The MEMS structures are made by contacting carbon dimer species with an oxide substrate forming a carbide layer on the surface onto which ultrananocrystalline diamond having average grain sizes of less than about 10 nm is deposited. Thereafter, microfabrication process are used to form a structure of predetermined shape having a feature resolution of less than about one micron.

Abstract: A method of forming a semiconductor structure including providing a single crystal semiconductor substrate of GaP, and fabricating a graded composition buffer including a plurality of epitaxial semiconductor Inx(AlyGa1−y)1−xP alloy layers. The buffer includes a first alloy layer immediately contacting the substrate having a lattice constant that is nearly identical to that of the substrate, subsequent alloy layers having lattice constants that differ from adjacent layers by less than 1%, and a final alloy layer having a lattice constant that is substantially different from the substrate. The growth temperature of the final alloy layer is at least 20° C. less than the growth temperature of the first alloy layer.

Abstract: A method for growing a single crystal GaN film at least 2 microns thick on a Si substrate is disclosed. The method includes growing a prelayer, a buffer layer including AlN on the Si substrate and a plurality of GaN layers and AlN layers deposited alternatively on the top of the AlN buffer layer. By controlling the deposition conditions and timings of the plurality of GaN layers and AlN layers, the single crystal GaN film can be grown thicker than 2 microns without cracks or pits.

Abstract: A process for producing an epitaxial layer of gallium nitride (GaN). A film of a dielectric whose thickness is about one monolayer is formed on a surface of a substrate. A continuous gallium nitride layer is then deposited on the dielectric film at a temperature sufficiently low to suppress island formation of the gallium nitride. The deposited gallium nitride layer is annealed at a temperature sufficiently high to promote island formation of the gallium nitride. An epitaxial regrowth with gallium nitride at the end of a spontaneous in situ formation of islands of gallium nitride then takes place. This method makes it possible to avoid having to use ex situ etching of masks by photolitographiy or chemical ethching techniques.

Abstract: A CVD method for growing MgO on a Si(100) substrate coated with a cubic SiC buffer layer provides a single-crystalline MgO film having improved quality.

Abstract: A method of producing an SOI wafer comprises the steps of forming an ion-implanted layer by forming an oxide film on at least one silicon wafer between two silicon wafers and implanting hydrogen ions or rare gas ions into one silicon wafer, superposing the surface of the silicon wafer on which the ion-implanted layer is formed and the other silicon wafer, heating at a temperature between 300° C. and 900° C., and delaminating from the ion-implanted wafer, and performing a heat treatment of the delaminated wafer at a temperature between 1000° C. and 1300° C., wherein the wafer forming the ion-implanted layer has an interstitial oxygen concentration of 1×1018/cm3 (old ASTM) or higher, and the method further comprises a step to grow an epitaxial layer on the SOI layer formed in the previous step.

Abstract: A buffer layer 2 made of aluminum nitride (AlN) is formed on a substrate 1 and is formed into an island pattern such as a dot pattern, a striped pattern, or a grid pattern such that substrate-exposed portions are formed in a scattered manner. A group III nitride compound semiconductor 3 grows epitaxially on the buffer layer 2 in a longitudinal direction, and grows epitaxially on the substrate-exposed portions in a lateral direction. As a result, a group III nitride compound semiconductor 3 which has little or no feedthrough dislocations 4 is obtained. Because the region where the group III nitride compound semiconductor 3 grows epitaxially in a lateral direction, on region 32, has excellent crystallinity, forming a group III nitride compound semiconductor device on the upper surface of the region results in improved device characteristics.

Abstract: A method for making photonic crystal structures using amorphous silicon that is temperature compatible with a wide variety of substrates. Both hydrogenated and non-hydrogenated amorphous silicon may be used.

Abstract: A thin film producing method in which the wafer film forming processing for a wafer to be a product may be carried out efficiently to shorten the processing time and to raise the operating ratio of the device. In a thin film deposition method using a single wafer processing for forming a thin film by chemical reaction under heat, a pseudo-process is provided which operates to suppress variations in the film thickness caused by the temperature in a reaction chamber 11. This pseudo process is the pre-heating processing of heating the reaction chamber 11 before actually charging the wafer W into the reaction chamber 11.

Abstract: The method of protectively coating metallic uranium which comprises dipping the metallic uranium in a molten alloy comprising about 20-75% of copper and about 80-25% of tin, dipping the coated uranium promptly into molten tin, withdrawing it from the molten tin and removing excess molten metal, thereupon dipping it into a molten metal bath comprising aluminum until it is coated with this metal, then promptly withdrawing it from the bath.

Abstract: A process of fabricating a CMOS device comprised with super-steep retrograde (SSR), twin well regions, has been developed. The process features the use of two, selective epitaxial growth (SEG), procedures, with the first SEG procedure resulting in the growth of bottom silicon shapes in the PMOS, as well as in the NMOS region of the CMOS device. After implantation of the ions needed for the twin well regions, into the bottom silicon shapes, a second SEG procedure is employed resulting in growth of top silicon shapes on the underlying, implanted bottom silicon shapes. An anneal procedure then distributes the implanted ions resulting in an SSR N well region in the composite silicon shape located in the PMOS region, and resulting in an SSR P well region in the composite silicon shape located in the NMOS region of the CMOS device.

Abstract: A method for fabricating a Group III nitride semiconductor substrate according to the present invention includes the steps of: (a) preparing a substrate; (b) forming, on the substrate, a first semiconductor layer composed of a Group III nitride semiconductor; (c) forming, on the first semiconductor layer, a heat diffusion suppressing layer lower in thermal conductivity than the first semiconductor layer; (d) forming, on the heat diffusion suppressing layer, a second semiconductor layer composed of a Group III nitride semiconductor; and (e) irradiating the first semiconductor layer through the substrate with a light beam transmitted by the substrate and absorbed by the first semiconductor layer to decompose the first semiconductor layer.

Abstract: The present invention provides a method for stabilizing an oxide-semiconductor interface, which is free from the formation of an interface layer (reactive layer) between a semiconductor and an interface oxide and which thereby allows satisfactory exhibition of performance capabilities of a functional oxide and achievement of the stability of oxide-semiconductor interface, yet independent of temperature; it also provides a stabilized semiconductor.