Coating (e.g., Masking, Implanting) Patents (Class 117/95)
  • Patent number: 6719841
    Abstract: A method of fabricating a high-density magnetic data-storage medium, the method comprising the steps of: (a) forming a plurality of nanodots of non-magnetic material in a regular array on a surface of a substrate, said array being notionally dividable into a plurality of clusters that each comprise a plurality of nanodots, wherein each nanodot of a said cluster overlaps with neighbouring nanodots of that cluster to form a well between them; (b) depositing magnetic material onto said substrate to at least partly fill the wells of each cluster; and (c) removing material to reveal a regular array of wells filled with magnetic material, each of said wells being separated from neighbouring wells by non-magnetic material.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: April 13, 2004
    Assignee: Data Storage Institute
    Inventors: Yunjie Chen, Jian-Ping Wang
  • Patent number: 6709513
    Abstract: In a process for producing a substrate for use in a semiconductor element: a porous anodic alumina film having a great number of minute pores is formed on a surface of a base substrate; the surface of the base substrate is etched by using the porous anodic alumina film as a mask so as to form a great number of pits on the surface of the base substrate; the porous anodic alumina film is removed; and a GaN layer is formed on the surface of the base substrate by crystal growth.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: March 23, 2004
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Toshiaki Fukunaga, Toshiaki Kuniyasu, Mitsugu Wada, Yoshinori Hotta
  • Patent number: 6692568
    Abstract: A method utilizes sputter transport techniques to produce arrays or layers of self-forming, self-oriented columnar structures characterized as discrete, single-crystal Group III nitride posts or columns on various substrates. The columnar structure is formed in a single growth step, and therefore does not require processing steps for depositing, patterning, and etching growth masks. A Group III metal source vapor is produced by sputtering a target, for combination with nitrogen supplied from a nitrogen-containing source gas. The III/V ratio is adjusted or controlled to create a Group III metal-rich environment within the reaction chamber conducive to preferential column growth. The reactant vapor species are deposited on the growth surface to produce single-crystal MIIIN columns thereon. The columns can be employed as a strain-relieving platform for the growth of continuous, low defect-density, bulk materials.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: February 17, 2004
    Assignee: Kyma Technologies, Inc.
    Inventors: Jerome J. Cuomo, N. Mark Williams, Andrew David Hanser, Eric Porter Carlson, Darin Taze Thomas
  • Patent number: 6689211
    Abstract: A SiGe monocrystalline etch-stop material system on a monocrystalline silicon substrate. The etch-stop material system can vary in exact composition, but is a doped or undoped Si1−xGex alloy with x generally between 0.2 and 0.5. Across its thickness, the etch-stop material itself is uniform in composition. The etch stop is used for micromachining by aqueous anisotropic etchants of silicon such as potassium hydroxide, sodium hydroxide, lithium hydroxide, ethylenediamine/pyrocatechol/pyrazine (EDP), TMAH, and hydrazine. These solutions generally etch any silicon containing less than 7×1019 cm−3 of boron or undoped Si1−xGex alloys with x less than approximately 18. Alloying silicon with moderate concentrations of germanium leads to excellent etch selectivities, i.e., differences in etch rate versus pure undoped silicon. This is attributed to the change in energy band structure by the addition of germanium.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: February 10, 2004
    Assignee: Massachusetts Institute of Technology
    Inventors: Kenneth C. Wu, Eugene A. Fitzgerald, Jeffrey T. Borenstein, Gianna Taraschi
  • Patent number: 6673149
    Abstract: A method for the production of a crack-free epitiaxial film having a thickness greater than that which can be achieved by continuous epitaxial crystal growth. This epitaxial film can be used as is in a device, used as a substrate platform for further epitaxy, or separated from the initial substrate material and used as a free-standing substrate platform. The method utilizes a defect-rich initial layer that absorbs epitaxially derived stresses and another layer, which is not defect-rich, which planarizes the crystal growth front, if necessary and provides high quality epitaxial region near the surface.
    Type: Grant
    Filed: September 6, 2000
    Date of Patent: January 6, 2004
    Assignees: Matsushita Electric Industrial Co., LTD, CBL Technologies, Inc.
    Inventors: Glenn S. Solomon, David J. Miller, Tetsuzo Ueda
  • Patent number: 6667102
    Abstract: A highly oxygen-sensitive silicon layer (2) is formed on a substrate (4) of, for example, SiC. The layer (2) has a 4×3 surface structure. The silicon layer (2) is deposited on a surface of the substrate (4) in a substantially uniform manner. The highly oxygen-sensitive silicon layer of the present invention may be used, for example in microelectronics.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: December 23, 2003
    Assignee: Commissariat A l'Energie Atomique
    Inventors: Fabrice Amy, Christian Brylinski, GĂ©rald Dujardin, Hanna Enriquez, Andrew Mayne, Patrick Soukiassian
  • Patent number: 6666916
    Abstract: A mandrel for use in a diamond deposition process has surfaces with different diamond adhesion properties. According to one embodiment, a mandrel is provided and has first and second surfaces on which a diamond film is deposited, with the second surface forming a perimeter around the first surface. The first surface of the mandrel has a first diamond bonding strength which is less than a second diamond bonding strength of the second surface. In an embodiment for forming a cup-shaped diamond film, the mandrel is a titanium nitride (TiN) coated molybdenum (Mo) substrate having a stepped solid cylindrical shape with a central mesa having a side wall or flank. The side wall is etched near the top surface of the mesa to expose a molybdenum band and to form a second surface which bounds the TiN first surface.
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: December 23, 2003
    Assignee: Saint-Gobain/Norton Industrial Ceramics Corporation
    Inventors: Randy D. Fellbaum, Volker R. Ulbrich
  • Patent number: 6656271
    Abstract: A process for manufacturing a semiconductor wafer which has superior suitability for mass production and reproducibility. The process comprises the steps of preparing a first member which has a monocrystalline semiconductor layer on a semiconductor substrate with a separation layer arranged therebetween with a semiconductor wafer as the raw material, transferring the monocrystalline semiconductor layer onto a second member which comprises a semiconductor wafer after separating the monocrystalline semiconductor layer through the separation layer, and smoothing the surface of the semiconductor substrate after the transferring step so as to be used as a semiconductor wafer for purposes other than forming the first and second members.
    Type: Grant
    Filed: December 3, 1999
    Date of Patent: December 2, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takao Yonehara, Kunio Watanabe, Tetsuya Shimada, Kazuaki Ohmi, Kiyofumi Sakaguchi
  • Patent number: 6648966
    Abstract: A method for making a free-standing, single crystal, gallium nitride (GaN) wafer includes forming a single crystal GaN layer directly on a single crystal LiAlO2 substrate using a gallium halide reactant gas, and removing the single crystal LiAlO2 substrate from the single crystal GaN layer to make the free-standing, single crystal GaN wafer. Forming the single crystal GaN layer may comprise depositing GaN by vapor phase epitaxy (VPE) using the gallium halide reactant gas and a nitrogen-containing reactant gas. Because gallium halide is used as a reactant gas rather than a metal organic reactant such as trimethygallium (TMG), the growth of the GaN layer can be performed using VPE which provides commercially acceptable rapid growth rates. In addition, the GaN layer is also devoid of carbon throughout. Because the GaN layer produced is high quality single crystal, it may have a defect density of less than about 107 cm−2.
    Type: Grant
    Filed: August 1, 2001
    Date of Patent: November 18, 2003
    Assignee: Crystal Photonics, Incorporated
    Inventors: Herbert Paul Maruska, John Joseph Gallagher, Mitch M. C. Chou
  • Patent number: 6645295
    Abstract: A buffer layer 2 made of aluminum nitride (AlN) is formed on a substrate 1 and is formed into an island pattern such as a dot pattern, a striped pattern, or a grid pattern such that substrate-exposed portions are formed in a scattered manner. A group III nitride compound semiconductor 3 grows epitaxially on the buffer layer 2 in a longitudinal direction, and grows epitaxially on the substrate-exposed portions in a lateral direction. As a result, a group III nitride compound semiconductor 3 which has little or no feedthrough dislocations 4 is obtained. Because the region where the group III nitride compound semiconductor 3 grows epitaxially in a lateral direction, on region 32, has excellent crystallinity, forming a group III nitride compound semiconductor device on the upper surface of the region results in improved device characteristics.
    Type: Grant
    Filed: May 9, 2000
    Date of Patent: November 11, 2003
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Seiji Nagai
  • Patent number: 6630023
    Abstract: A film (carbon and/or diamond) for a field emitter device, which may be utilized within a computer display, is produced by a process utilizing treatment of a substrate and then depositing the film. The treatment step creates nucleation and growth sites on the substrate for the film deposition process and promotes election emission of the deposited film. With this process, a patterned emission can be achieved without post-deposition processing of the film. A field emitter device can be manufactured with such a film.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: October 7, 2003
    Assignee: SI Diamond Technology, Inc.
    Inventors: Zhidan Li Tolt, Zvi Yaniv, Richard Lee Fink
  • Patent number: 6623560
    Abstract: A crystal growth method includes forming a mask layer capable of impeding crystal growth on a substrate in such a way a first nitride semiconductor layer has irregularities at a surface thereof exposed at a window region opened at a part of the mask layer, and growing a second nitride semiconductor layer over a region including the surface of the mask layer through crystal growth from the irregularities. Through-type dislocations can be reliably prevented from propagation due to the discontinuity of crystals at the irregularities and also to lateral crystal growth.
    Type: Grant
    Filed: July 17, 2001
    Date of Patent: September 23, 2003
    Assignee: Sony Corporation
    Inventors: Goshi Biwa, Hiroyuki Okuyama, Masato Doi, Toyoharu Oohata
  • Patent number: 6620710
    Abstract: A method of forming a single crystal semiconductor film on a non-crystalline surface is described. In accordance with this method, a template layer incorporating an ordered array of nucleation sites is deposited on the non-crystalline surface, and the single crystal semiconductor film is formed on the non-crystalline surface from the ordered array of nucleation sites. An integrated circuit incorporating one or more single crystal semiconductor layers formed by this method also is described.
    Type: Grant
    Filed: September 18, 2000
    Date of Patent: September 16, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Theodore I. Kamins
  • Patent number: 6610144
    Abstract: The present invention discloses a semiconductor film having a reduced dislocation density. The film comprises at least one interlayer structure, including a group III-nitride layer, a passivation interlayer disposed on the group III-nitride layer, interrupting the group III-nitride layer, and an island growth interlayer disposed on the passivation interlayer, and interrupting the group III-nitride layer. A method of making a semiconductor film of the present invention comprises producing a semiconductor film including at least one interlayer structure, each interlayer structure produced by the substeps of growing a group III-nitride layer, depositing a passivation interlayer on the group III-nitride layer, depositing an island growth interlayer on the passivation interlayer and continuing growing the group III-nitride layer.
    Type: Grant
    Filed: July 19, 2001
    Date of Patent: August 26, 2003
    Assignee: The Regents of the University of California
    Inventors: Umesh Kumar Mishra, Stacia Keller
  • Patent number: 6599362
    Abstract: A process of growing a material on a substrate, particularly growing a Group II-VI or Group III-V material, by a vapor-phase growth technique where the growth process eliminates the need for utilization of a mask or removal of the substrate from the reactor at any time during the processing. A nucleation layer is first grown upon which a middle layer is grown to provide surfaces for subsequent lateral cantilever growth. The lateral growth rate is controlled by altering the reactor temperature, pressure, reactant concentrations or reactant flow rates. Semiconductor materials, such as GaN, can be produced with dislocation densities less than 107/cm2.
    Type: Grant
    Filed: January 3, 2001
    Date of Patent: July 29, 2003
    Assignee: Sandia Corporation
    Inventors: Carol I. Ashby, David M. Follstaedt, Christine C. Mitchell, Jung Han
  • Publication number: 20030136333
    Abstract: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging between 100 and 300 nm, preferably between 200 and 250 nm, and whereof crystal lattice parameter is less than the crystal lattice parameter of the gallium nitride or of the mixed gallium nitride with another metal, is inserted in the coating of gallium nitride or mixed gallium nitride with another metal. The invention also concerns the method for preparing said coating. The invention further concerns electronic and optoelectronic devices comprising said coating.
    Type: Application
    Filed: December 9, 2002
    Publication date: July 24, 2003
    Inventors: Fabrice Semond, Jean Claude Massies, Nicolas Pierre Grandjean
  • Patent number: 6596079
    Abstract: A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds, from which wafers may be derived for fabrication of microelectronic device structures. The boule is of microelectronic device quality, e.g., having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 107 defects cm−2. The Group III-V nitride boule may be formed by growing a Group III-V nitride material on a corresponding native Group III-V nitride seed crystal by vapor phase epitaxy at a growth rate above 20 micrometers per hour.
    Type: Grant
    Filed: March 13, 2000
    Date of Patent: July 22, 2003
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Robert P. Vaudo, Jeffrey S. Flynn, George R. Brandes, Joan M. Redwing, Michael A. Tischler
  • Patent number: 6596095
    Abstract: A single crystal silicon wafer with a back surface free of an oxide seal and substantially free of a chemical vapor deposition process induced halo and an epitaxial silicon layer on the front surface, the epitaxial layer is characterized by an axially symmetric region extending radially outwardly from the central axis of the wafer toward the circumferential edge of the wafer having a substantially uniform resistivity, the radius of the axially symmetric region being at least about 80% of the length of the radius of the wafer.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: July 22, 2003
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Michael J. Ries, Charles Chiun-Chieh Yang, Robert W. Standley
  • Patent number: 6592661
    Abstract: A method of manufacturing semiconductor wafers in a processing chamber having at least one radiant heat source is provided. The method includes the steps of applying a predetermined amount of power to the radiant heat source and positioning a wafer within the processing chamber. The predetermined amount of power applied to the at least one radiant heat source is set such that the wafer reaches a predetermined temperature in a predetermined amount of time for carrying out a desired process in the processing chamber. The processing chamber is particularly suited for very low pressure environments and may be used to form HSG in a clustered or non-clustered system. A reflective plate may be used so that the radiated properties of the wafer are substantially independent of the emissivity of the wafer thereby minimizing emissivity variation from one wafer to another. Another plate may be used to form an isothermal cavity between the plate and the wafer to minimize emissivity variation from one wafer to another.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: July 15, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Randhir P. S. Thakur, Ronald A. Weimer
  • Publication number: 20030127043
    Abstract: A method of forming a tungsten nucleation layer using a sequential deposition process. The tungsten nucleation layer is formed by reacting pulses of a tungsten-containing precursor and a reducing gas in a process chamber to deposit tungsten on the substrate. Thereafter, reaction by-products generated from the tungsten deposition are removed from the process chamber. After the reaction by-products are removed from the process chamber, a flow of the reducing gas is provided to the process chamber to react with residual tungsten-containing precursor remaining therein. Such a deposition process forms tungsten nucleation layers having good step coverage. The sequential deposition process of reacting pulses of the tungsten-containing precursor and the reducing gas, removing reaction by-products, and than providing a flow of the reducing gas to the process chamber may be repeated until a desired thickness for the tungsten nucleation layer is formed.
    Type: Application
    Filed: July 12, 2002
    Publication date: July 10, 2003
    Applicant: Applied Materials, Inc.
    Inventors: Xinliang Lu, Ping Jian, John Hyun Yoo, Ken Kaung Lai, Alfred W. Mak, Robert L. Jackson, Ming Xi
  • Patent number: 6589336
    Abstract: Performing the post-implantation annealing for recovering crystallinity in a hydrogen atmosphere can successfully suppress the surface roughening on the ion-implanted layers without pre-implantation oxidation. This allows omission of the pre-implantation oxidation and allows ion implantation using only a photoresist film as a mask in a method for producing an epitaxial wafer having buried ion-implanted layers. Since an intentional formation of an oxide film, including such pre-implantation oxidation, on an epitaxial layer is omitted, the number of repetition of the thermal history exerted to the buried ion-implanted layers can be reduced, which effectively suppresses lateral diffusion of implanted ions. Since the formation and removal of the oxide film is thus no more necessary, the number of process steps in the production of the epitaxial wafer can dramatically be reduced.
    Type: Grant
    Filed: July 10, 2001
    Date of Patent: July 8, 2003
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Koji Ebara, Hiroki Ose, Yasuo Kasahara
  • Patent number: 6589333
    Abstract: A method is described for the production of a suitable substrate for the subsequent growth of a mono-crystalline diamond layer. This method includes the following steps: Selection of a substrate of a mono-crystalline material having a fixed lattice constant (aSi) or with a layer consisting of such a material. Manufacture of a strained silicon layer with foreign material atoms incorporated at substitutional lattice sites on the mono-crystalline material of the substrate. Transfer of the strained layer into an at least partly relaxed state in which it adopts by relaxation and through the selected foreign material concentration a lattice constant (aSi(C) which satisfies the condition n.aSi(C)=m.aD, wherein n and m are integers and aD is the lattice constant of diamond, with the relaxed layer forming the substrate or substrate surface for the epitaxial growth.
    Type: Grant
    Filed: September 18, 2000
    Date of Patent: July 8, 2003
    Assignee: Max-Planck-Gesellschaft zur Foerderung der Wissenschaften e.V.
    Inventors: Ulrich Gösele, Andreas Plössl
  • Patent number: 6589337
    Abstract: In a process of producing a SiC device, a Si layer is formed on the surface of a SiC substrate, and the Si layer is removed from the surface of the SiC substrate by supplying oxygen gas to the Si layer in a high ambient temperature and a low ambient pressure. The pressure is set at 1×10−2 to 1×10−6 Pa. Thus a cleaned surface of the SiC substrate, not contaminated by carbon and the like in atmospheric air, can be provided. Preferably, the oxygen pressure and temperature are set at about 10−6 Pa and 1000° C. for removing the Si layer. Thereafter, the oxygen is further supplied to raise the pressure to about 104 Pa to form an oxide film on the cleaned SiC substrate. Thus, the SiC substrate is cleaned and then formed with the oxide layer in the same chamber by changing the ambient pressure but without changing the ambient temperature.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: July 8, 2003
    Assignee: Denso Corporation
    Inventors: Yoshiyuki Hisada, Shinichi Mukainakano, Takeshi Hasegawa, Ayahiko Ichimiya, Tomohiro Aoyama, Kiyoshige Kato
  • Publication number: 20030111008
    Abstract: The invention relates to a process for the epitaxy of (indium, aluminum, gallium) nitride on foreign substrates.
    Type: Application
    Filed: August 9, 2002
    Publication date: June 19, 2003
    Inventors: Andre Strittmatter, Alois Krost, Dieter Bimberg
  • Patent number: 6579360
    Abstract: A method of forming a biaxially aligned superconductor on a non-biaxially aligned substrate substantially chemically inert to the biaxially aligned superconductor comprising is disclosed. A non-biaxially aligned substrate chemically inert to the superconductor is provided and a biaxially aligned superconductor material is deposited directly on the non-biaxially aligned substrate. A method forming a plume of superconductor material and contacting the plume and the non-biaxially aligned substrate at an angle greater than 0° and less than 90° to deposit a biaxially aligned superconductor on the non-biaxially aligned substrate is also disclosed. Various superconductors and substrates are illustrated.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: June 17, 2003
    Assignee: The University of Chicago
    Inventors: Uthamalingam Balachandran, Stephen E. Dorris, Beihai Ma, Meiya Li
  • Patent number: 6579359
    Abstract: A method is disclosed for fabricating monocrystal material with the bandgap width exceeding 1.8 eV. The method comprises the steps of processing a monocrystal semiconductor wafer to develop a porous layer through electrolytic treatment of the wafer at direct current under UV-illumination, and epitaxially growing a monocrystal layer on said porous layer. Growth on porous layer produces semiconductor material with reduced stress and better characteristics than with the same material grown on non-porous layers and substrates. Also, semiconductor device structure comprising at least one layer of porous group III material is included.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: June 17, 2003
    Assignee: Technologies and Devices International, Inc.
    Inventors: Marina Mynbaeva, Denis Tsvetkov, Vladimir Dmitriev, Alexander Lebedev, Nataliya Savkina, Alexander Syrkin, Stephen Saddow, Karim Mynbaev
  • Patent number: 6576053
    Abstract: In a method of forming a thin film using an atomic layer deposition (ALD) method, a thin film is formed on a substrate in cycles. Each cycle includes injecting a first reactant including an atom that forms the thin film and a ligand into a reaction chamber that includes the substrate, purging the first reactant, injecting a second reactant into the reaction chamber, and purging the second reactant. The thin film is formed by a chemical reaction between the atom that forms the thin film and a second reactant whose binding energy with respect to the atom that forms the thin film is larger than the binding energy of the ligand with respect to the atom that forms the thin film and the generation of by-products is prevented. The generation of a hydroxide by-product in the thin film is suppressed by using a material that does not include a hydroxide as the second reactant, purging the second reactant, and reacting the second reactant with a third reactant that includes hydroxide.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: June 10, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong-kwan Kim, Young-wook Park, Jae-soon Lim, Sung-je Choi, Sang-in Lee
  • Publication number: 20030094131
    Abstract: A process for modifying the surface of a quartz glass crucible and a modified quartz glass crucible produced by the process, where the crucible has a transparent coated layer containing a crystallization accelerator on the surface. The process includes coating a mixed solution containing a metal salt and a partial hydrolyzate of alkoxysilane oligomer on the surface of the crucible and heating to obtain a quartz glass crucible having a transparent coated layer. The crystallization accelerator contains a metal oxide or a metal carbonate dispersed in a silica matrix.
    Type: Application
    Filed: June 6, 2002
    Publication date: May 22, 2003
    Applicant: JAPAN SUPER QUARTZ CORPORATION
    Inventors: Toshio Tsujimoto, Yoshiyuki Tsuji
  • Patent number: 6555845
    Abstract: The Group III-V compound semiconductor manufacturing method which pertains to the present invention is a semiconductor manufacturing method employing epitaxy which comprises (a) a step in which growing areas are produced using a mask patterned on a substrate surface and (b) a step in which a Group III-V compound semiconductor layer is grown in the growing areas while forming facet structures. As epitaxy is continued, adjacent facet structures come into contact so that the surface of the semiconductor layer becomes planarized. Since lattice defects extend towards the facet structures, they do not extend towards the surface of the semiconductor layer. Accordingly, the number of lattice defects in the vicinity of the semiconductor layer surface is reduced.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: April 29, 2003
    Assignee: NEC Corporation
    Inventors: Haruo Sunakawa, Akira Usui
  • Patent number: 6537368
    Abstract: A process for preparing a silicon epitaxial wafer. The wafer has a front surface having an epitaxial layer deposited thereon, a back surface, and a bulk region between the front and back surfaces, wherein the bulk region contains a concentration of oxygen precipitates. In the process, the wafer is first subjected to an ideal oxygen precipitating heat treatment to causes the formation of a non-uniform distribution of crystal lattice vacancies with the concentration of vacancies in the bulk region being greater than the distribution of vacancies in the front surface. The ideal precipitating wafer is then subjected to an oxygen precipitation heat treatment to cause the nucleation and growth of oxygen precipitates to a size sufficient to stabilize the oxygen precipitates, with the oxygen precipitates being formed primarily according to the vacancy profile. An epitaxial layer is then deposited on the surface of the oxygen precipitate stabilized wafer.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: March 25, 2003
    Assignee: MEMC Electronic Materials SpA
    Inventors: Robert J. Falster, Marco Cornara, Daniela Gambaro, Massimiliano Olmo
  • Patent number: 6530991
    Abstract: A method for the formation of a semiconductor layer by which a defect density of structural defects, particularly a dislocation density of threading dislocations in the resulting semiconductor layer can be remarkably reduced, so that hours of work can be shortened as well as a manufacturing cost can be reduced without requiring any complicated process comprises supplying a structural defect suppressing material for suppressing structural defects in the semiconductor layer onto a surface of the layer of a material from which the semiconductor layer is to be formed.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: March 11, 2003
    Assignees: Riken
    Inventors: Satoru Tanaka, Misaichi Takeuchi, Yoshinobu Aoyagi
  • Patent number: 6521041
    Abstract: A SiGe monocrystalline etch-stop material system on a monocrystalline silicon substrate. The etch-stop material system can vary in exact composition, but is a doped or undoped Si1−xGex alloy with x generally between 0.2 and 0.5. Across its thickness, the etch-stop material itself is uniform in composition. The etch stop is used for micromachining by aqueous anisotropic etchants of silicon such as potassium hydroxide, sodium hydroxide, lithium hydroxide, ethylenediamine/pyrocatechol/pyrazine (EDP), TMAH, and hydrazine. For example, a cantilever can be made of this etch-stop material system, then released from its substrate and surrounding material, i.e., “micromachined”, by exposure to one of these etchants. These solutions generally etch any silicon containing less than 7×1019 cm−3 of boron or undoped Si1−xGex alloys with x less than approximately 18. Alloying silicon with moderate concentrations of germanium leads to excellent etch selectivities, i.e.
    Type: Grant
    Filed: April 9, 1999
    Date of Patent: February 18, 2003
    Assignee: Massachusetts Institute of Technology
    Inventors: Kenneth C. Wu, Eugene A. Fitzgerald, Jeffrey T. Borenstein
  • Publication number: 20030024472
    Abstract: A method for making a free-standing, single crystal, gallium nitride (GaN) wafer includes forming a single crystal GaN layer directly on a single crystal LiAlO2 substrate using a gallium halide reactant gas, and removing the single crystal LiAlO2 substrate from the single crystal GaN layer to make the free-standing, single crystal GaN wafer. Forming the single crystal GaN layer may comprise depositing GaN by vapor phase epitaxy (VPE) using the gallium halide reactant gas and a nitrogen-containing reactant gas. Because gallium halide is used as a reactant gas rather than a metal organic reactant such as trimethygallium (TMG), the growth of the GaN layer can be performed using VPE which provides commercially acceptable rapid growth rates. In addition, the GaN layer is also devoid of carbon throughout. Because the GaN layer produced is high quality single crystal, it may have a defect density of less than about 107 cm−2.
    Type: Application
    Filed: August 1, 2001
    Publication date: February 6, 2003
    Applicant: CRYSTAL PHOTONICS, INCORPORATED
    Inventors: Herbert Paul Maruska, John Joseph Gallagher, Mitch M.C. Chou
  • Patent number: 6511538
    Abstract: When performing film deposition on the surface of a wafer, a turntable supporting the wafer is first rotated. Next, a fluid containing an organic metal is applied onto the wafer via the tip of a nozzle. At the same time, an ultrasound wave is generated by an ultrasound wave generating device, and the turntable is vibrated. Thus the vibrations from the turntable are applied to the wafer, these wafer vibrations allow the fluid containing an organic metal to thoroughly permeate into the detailed patterning of the wafer surface, and said fluid covers its entirety. As a result, film deposition with excellent filling-in characteristics becomes possible.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: January 28, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Yuichi Wada, Hiroyuki Yarita, Hisashl Aida, Naomi Yoshida
  • Patent number: 6506252
    Abstract: The invention describes a CVD reactor on solid substrates and a related method of deposition of epitaxial layers on the wafers. In the reactor of the invention, the wafer carrier is transported between a loading position and a deposition position. In the deposition position, the wafer carrier is detachably mounted on an upper end of a rotatable spindle without an intermediate susceptor. The reactor of the invention may process a single wafer at the same time. The invention also describes several embodiments and variants of the invention. One of the variants of the invention provides a decrease in a heat drain from the wafer-supporting assembly through the spindle and a novel heating arrangement therefore. The advantages of the invention include lower reactor cycle, the lower cost and longer lifetime of the component parts, and better temperature control, among others.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: January 14, 2003
    Assignee: Emcore Corporation
    Inventors: Vadim Boguslavskiy, Alexander Gurary
  • Patent number: 6503321
    Abstract: A method is provided for detaching a single-crystal film from an epilayer/substrate or bulk crystal structure. The method includes the steps of implanting ions into the crystal structure to form a damage layer within the crystal structure at an implantation depth below a top surface of the crystal structure, and chemically etching the damage layer to effect detachment the single-crystal film from the crystal structure. The thin film may be detached by subjecting the crystal structure with the ion implanted damage layer to a rapid temperature increase without chemical etching. The method of the present invention is especially useful for detaching single-crystal metal oxide films from metal oxide crystal structures. Methods for enhancing the crystal slicing etch-rate are also disclosed.
    Type: Grant
    Filed: April 9, 1999
    Date of Patent: January 7, 2003
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Miguel Levy, Richard M. Osgood, Jr., Antonije M. Radojevic
  • Patent number: 6500257
    Abstract: An epitaxial material grown laterally in a trench allows for the fabrication of a trench-based semiconductor material that is substantially low in dislocation density. Initiating the growth from a sidewall of a trench minimizes the density of dislocations present in the lattice growth template, which minimizes the dislocation density in the regrown material. Also, by allowing the regrowth to fill and overflow the trench, the low dislocation density material can cover the entire surface of the substrate upon which the low dislocation density material is grown. Furthermore, with successive iterations of the trench growth procedure, higher quality material can be obtained. Devices that require a stable, high quality epitaxial material can then be fabricated from the low dislocation density material.
    Type: Grant
    Filed: April 17, 1998
    Date of Patent: December 31, 2002
    Assignee: Agilent Technologies, Inc.
    Inventors: Shih-Yuan Wang, Changhua Chen, Yong Chen, Scott W. Corzine, R. Scott Kern, Richard P. Schneider, Jr.
  • Patent number: 6497763
    Abstract: A method for making a multilayered electronic device with at least one epitaxial layer grown on a single-crystal film bonded to a composite wherein at least one layer is polycrystalline, the method includes the step of bonding a single-crystal film at least one of the epitaxial layers on the single-crystal film wherein thermal coefficients of expansion for the substrate and the epitaxial layer are closely matched.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: December 24, 2002
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Karl D. Hobart
  • Publication number: 20020179006
    Abstract: The process relates to a process for nucleating and growing oxygen precipitates in a silicon wafer. The process includes subjecting a wafer having a non-uniform concentration of crystal lattice vacancies with the concentration of vacancies in the bulk layer being greater than the concentration of vacancies in the surface layer to a non-isothermal heat treatment to form of a denuded zone in the surface layer and to cause the formation and stabilization of oxygen precipitates having an effective radial size 0.5 nm to 30 nm in the bulk layer. The process optionally includes subjecting the stabilized wafer to a high temperature thermal process (e.g. epitaxial deposition, rapid thermal oxidation, rapid thermal nitridation and etc.) at temperatures in the range of 1000° C. to 1275° C. without causing the dissolution of the stabilized oxygen precipitates.
    Type: Application
    Filed: April 22, 2002
    Publication date: December 5, 2002
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Marco Borgini, Daniela Gambaro, Marco Ravani, Michael J. Ries, Laura Sacchetti, Robert W. Standley, Robert J. Falster, Mark G. Stinson
  • Patent number: 6488771
    Abstract: A method is disclosed for growing high-quality low-defect crystal films heteroepitaxially on substrates that are different than the crystal films. The growth of the first two heteroepitaxial bilayers is performed on a first two-dimensional nucleate island before a second growth of two-dimensional nucleation is allowed to start. The method is particularly suited for the growth of 3C-SiC, 2H-AlN, or 2H-GaN on 6H-SiC, 4H-SiC, or silicon substrates.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: December 3, 2002
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: J. Anthony Powell, Philip G. Neudeck
  • Patent number: 6485564
    Abstract: In a thin film forming method of the invention, an atmosphere for a base as a thin film forming target is set to a high vacuum of, e.g., 0.01 Torr or less, and a gas of an organometallic compound and an oxidizing gas are introduced onto a base surface heated to about 450° C., to form a plurality of crystal nuclei, made of an oxide of a metal constituting the organometallic compound, on the base surface. The atmosphere for the base is then set to a lower vacuum than the first vacuum degree, and the gas of the organometallic compound and the oxidizing gas are subsequently introduced onto the base surface heated to about 45° C., to form a film made of the oxide of the metal there.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: November 26, 2002
    Assignee: Tokyo Electron Limited
    Inventors: Yijun Liu, Hiroshi Shinriki, Takashi Magara
  • Patent number: 6478871
    Abstract: An epitaxial deposition process produces epitaxial lateral overgrowth (ELO) of nitride based materials directly a patterned substrate (10). The substrate (10) is preferably formed from SiC or sapphire, and is patterned with a mask (12), preferably formed of silicon nitride, having a plurality of openings (13) formed therein. A nucleation layer (14), preferably formed of AlGaN, is grown at a high reactor temperature of 700-1100 degrees C., which wets the exposed substrate surface, without significant nucleation on the mask (12). This eliminates the need for regrowth while producing smooth growth surfaces in the window openings (13) as well as over the mask (12). Subsequent deposition of a nitride based material layer (16), preferably GaN, results in a relatively defect free planar surfaced material grown laterally over the mask (12).
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: November 12, 2002
    Assignee: Cornell Research Foundation, Inc.
    Inventors: James R. Shealy, Joseph A. Smart
  • Patent number: 6475456
    Abstract: There is disclosed a method for manufacturing a silicon carbide film in which a crystal orientation is continued on a single crystal substrate surface and silicon carbide is allowed to epitaxially grow, the method comprising the steps of: entirely or partially providing the substrate surface with a plurality of undulations extended parallel in one direction; and allowing silicon carbide to grow on the substrate surface.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: November 5, 2002
    Assignee: Hoya Corporation
    Inventors: Yukitaka Nakano, Hiroyuki Nagasawa, Kuniaki Yagi, Takamitsu Kawahara
  • Publication number: 20020152952
    Abstract: The invention concerns a method for producing a gallium nitride (GaN) epitaxial layer characterised in that it consists in depositing on a substrate a dielectric layer acting as a mask and depositing on the masked gallium nitride, by epitaxial deposit, so as to induce the deposit of gallium nitride patterns and the anisotropic lateral growth of said patterns, the lateral growth being pursued until the different patterns coalesce. The deposit of the gallium nitride patterns can be carried out ex-situ by dielectric etching on in-situ by treating the substrate for coating it with a dielectric film whereof the thickness is of the order of one angstrom. The invention also concerns the gallium nitride layers obtained by said method.
    Type: Application
    Filed: September 21, 2001
    Publication date: October 24, 2002
    Inventors: Bernard Beaumont, Pierre Gibart, Jean-Claude Guillaume, Gilles Nataf, Michel Vaille, Soufien Haffouz
  • Patent number: 6468347
    Abstract: A GaN single crystal is grown by synthesizing GaN in vapor phase, piling a GaN crystal on a substrate, producing a three-dimensional facet structure including facets in the GaN crystal without making a flat surface, maintaining the facet structure without burying the facet structure, and reducing dislocations in the growing GaN crystal. The facet structure reduces the EPD down to less than 106 cm−2.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: October 22, 2002
    Assignee: Sumitomo Electric Industries Ltd.
    Inventors: Kensaku Motoki, Takuji Okahisa, Naoki Matsumoto
  • Patent number: 6447605
    Abstract: Disclosed is a method for preparing heteroepitaxial thin films which are free of island structures which have a bad influence on the photoelectric properties and interfacial reactivity of the thin films. These heteroepitaxial thin films are deposited on grooved or curved surfaces of substrates. The use of grooved substrates relieves the coherent elastic strain from the thin films, thereby inhibiting the surface roughening and the island structure formation in the heteroepitaxial thin films. The method can be applied to all of the thin films that show island structures, including GaAs/Si and SiGe/Si typically used in semiconductor devices and various electronic parts, enabling the thin films to be flatly deposited at a significant thickness on various substrates without additionally processing.
    Type: Grant
    Filed: November 17, 1999
    Date of Patent: September 10, 2002
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Sung Yoon Chung, Suk Pil Kim, Byung Sung Kang, Si Kyung Choi, Suk Joong Kang
  • Patent number: 6447604
    Abstract: A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V/III ratio in a range of from about 1 to about 105, nitrogen source material partial pressure in a range of from about 1 to about 103 torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 500 microns per hour. The III-V nitride homoepitaxial microelectronic device structures are usefully employed in device applications such as UV LEDs, high electron mobility transistors, and the like.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: September 10, 2002
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Jeffrey S. Flynn, George R. Brandes, Robert P. Vaudo, David M. Keogh, Xueping Xu, Barbara E. Landini
  • Patent number: 6440214
    Abstract: A method of growing a nitride semiconductor layer, such as a GaN layer, by molecular beam epitaxy comprises the step of growing a GaAlN nucleation layer on a substrate by molecular beam epitaxy. The nucleation layer is annealed, and a nitride semiconductor layer is then grown over the nucleation layer by molecular beam epitaxy. The nitride semiconductor layer is grown at a V/III molar ratio of 100 or greater, and this enables a high substrate temperature to be used so that a good quality semiconductor layer is obtained. Ammonia gas is supplied during the growth process, to provide the nitrogen required for the MBE growth process.
    Type: Grant
    Filed: June 9, 2000
    Date of Patent: August 27, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Stewart Edward Hooper, Jennifer Mary Barnes, Jonathan Heffernan, Alistair Henderson Kean
  • Patent number: 6428635
    Abstract: An alloy capable of forming a (100) [001] cube-texture by thermo-mechanical techniques has 5 to 45 atomic percent nickel with the balance being copper. The alloy is useful as a conductive substrate for superconducting composites where the substrate is coated with a superconducting oxide. A buffer layer can optionally be coated on the substrate to enhance deposition of the superconducting oxide. Methods for producing the alloys, substrates, and superconductors are included.
    Type: Grant
    Filed: October 1, 1997
    Date of Patent: August 6, 2002
    Assignees: American Superconductor Corporation, The Regents of the University of California
    Inventors: Leslie G. Fritzemeier, Elliott D. Thompson, Edward J. Siegal, Cornelis Leo Hans Thieme, Robert D. Cameron, James L. Smith, W. Larry Hults
  • Patent number: 6409829
    Abstract: Integrated circuit devices are formed in a substrate wafer using selective epitaxial growth (SEG). Non-uniform epitaxial wafer thickness results when the distribution of SEG regions across the surface of the wafer is non-uniform, resulting in loading effects during the growth process. Loading effects are minimized according to the invention by adding passive SEG regions thereby giving a relatively even distribution of SEG growth regions on the wafer. The passive regions remain unprocessed in the finished IC device.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: June 25, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: John Joseph Bastek, Thomas J. Krutsick, Robert D. Plummer