Abstract: A thin film transistor array panel for a liquid crystal display, a liquid crystal display and a manufacturing method thereof are provided. The display panel includes: a substrate; and a first electrode portion disposed on the substrate, the first electrode portion having two pairs of main edges facing each other and a first cutout oblique to the main edges, wherein the main edges include first and second edges, the first electrode portion has an oblique edge substantially parallel to the first cutout, the oblique connecting the first edge and the second edge, the first edge includes a first portion extending from the oblique edge to an end of the first cutout, and the oblique edge is substantially equal to or longer than a half of the first portion of the first edge.

Abstract: Computer systems and methods that provide for cacheable above one megabyte system management random access memory (SMRAM). The systems and methods comprise a central processing unit (CPU) having a processor and a system management interrupt (SMI) dispatcher, a cache coupled to the CPU, and a chipset memory controller that interfaces the CPU to a memory. The memory includes system memory and the system management random access memory. The systems and methods un-cache the SMRAM while operating outside of system management mode, transfer CPU operation to system management mode upon execution of a system management interrupt (SMI), and change cache settings to cache the extended memory and system management random access memory with write-through. The systems and methods then change cache settings to cache the extended memory with write-back and un-cache the SMRAM upon execution of an resume instruction.