Abstract: A method of producing a semiconductor device having a bipolar transistor and a CMOS (Complementary Metal Oxide Semiconductor) transistor is disclosed. An epitaxial layer is formed on a semiconductor substrate having an n-type buried layer and a p-type buried layer thereinside. A field oxide film is formed on the epitaxial layer for delimiting active regions. An n-type and a p-type well region each is formed in a particular position. An insulation film playing the role of a gate oxide film at the same time is formed over the entire surface of the substrate. Subsequently, an emitter contact hole and a collector contact hole each extending to the epitaxial layer are formed at the same time. A polysilicon layer is formed over the entire surface of the substrate and then etched to form an emitter electrode and a gate electrode each having a preselected configuration. The resulting semiconductor device achieves a desirable current drive ability.

Abstract: An embodiment of the present invention is a process for semiconductor device having a silicon substrate. The process comprises positioning at least one field implant mask and field implanting a silicon substrate around a bipolar active region in a substrate such that boron atoms are blocked out of an active region, and only the field region surrounding the active area is implanted, the implanting such that a predetermined layout area of a semiconductor device does not need to be increased to compensate for a BV.sub.bso problem.

Abstract: A capacitor coupled contactless imager structure and method of manufacturing the structure results in a phototransistor that includes an N-type collector region formed in P-type semiconductor material. A P-type base region is formed in the collector region. An n-doped polysilicon emitter contact is formed in contact with the surface of the P-type base region such that an n+ epitaxial region is formed in the base region as the emitter of the imager phototransistor. Silicon dioxide separates the polysilicon emitter contact and exposed surfaces of the base region from a layer of poly2 about 500-600 .ANG. thick that is formed to cover the entire base region.

Abstract: A BiCMOS device and a manufacturing method thereof according to the present invention has a gate insulating layer of NMOSFET having non-uniform thickness. The thickness of the end portion of the gate insulating layer, which is near LDD regions, is thicker than that of center portion. Therefore, the GIDL and the gate-drain overlap capacitance is reduced. In addition, in case of the bipolar transistor of the BiCMOS device, there exists a portion of an oxide film below the side portion of the emitter polysilicon and over the side portions of the emitter region. Since this structure serves as a gate of field effect transistor, N- channel is produced in the emitter region when the emitter-base junction is reversely biased and thus the hot carrier reliability is improved.

Abstract: A BiCMOS manufacturing process for fabricating an emitter of a bipolar transistor includes the steps of forming footings on a silicon substrate for prospectively bearing edges of the emitter, forming a polysilicon emitter having a medial portion overlying the silicon substrate and lateral edges on the footings, removing the footings leaving notches at the lateral edges of the polysilicon emitter and refilling the notches with a thin polysilicon film. The bipolar transistor in a BiCMOS integrated circuit resulting from this process includes a silicon semiconductor substrate having a substantially flat surface, a field oxide film laterally bounding the silicon semiconductor substrate and a polysilicon emitter abutting the flat surface of the silicon semiconductor substrate.

Abstract: A bipolar device having a level difference between the contact area level of a base electrode and a base region in a silicon substrate, and the contact area level of an emitter electrode and an emitter region in the silicon substrate in the range of 0.03 .mu.m to 0.1 .mu.m by removing undesirable impurities from the emitter region and a predetermined horizontal distance between a sidewall and a device isolation film does not generate dislocation and show good electric characteristics.

Abstract: In a bipolar junction transistor of an epitaxial planar type comprising a base region, an emitter region formed in the base region, and a poly-silicon layer as an emitter poly-silicon electrode layer overlying the emitter region, the poly-silicon layer being used as an impurity diffusion source for forming the emitter region in fabrication of the transistor, the emitter poly-silicon electrode layer comprises a poly-silicon film containing an additive of one of C, O, and P overlying the emitter region and a poly-silicon layer overlying the poly-silicon film. An impurity is doped in the poly-silicon layer and is diffused into the base region through the poly-silicon film to form the emitter region in the base region in fabrication of the transistor. The poly-silicon film contains the additive and serves to prevent the poly-silicon film and the poly-silicon layer from grain growth which badly affects the impurity diffusion for forming the emitter region.

Abstract: A capacitor coupled contactless imager structure and a method of manufacturing the structure results in a phototransistor that structure includes an N-type collector region formed in P-type semiconductor material. A P-type base region is formed in the collector region. An n-doped polysilicon emitter contact is formed in contact with the surface of the P-type base region such that an n+ epitaxial region is formed in the base region as the emitter of the phototransistor. Silicon dioxide separates the poly1 emitter content and exposed surfaces at the base region from a layer of poly2 about 3000-4000 .ANG. thick that partially covers the base region; the gates of the CMOS peripheral devices are also poly2. The poly2 over the base region serves as a base coupling capacitor and a row conductor for the imager structure. The thickness of the poly2 capacitor plate allows it to be doped utilizing conventional techniques and silicided to improve the RC constant.

Abstract: In a method of manufacturing a bipolar transistor, an oxide film pattern is formed on an epitaxial collector layer of a first conductive type which is formed on a buried layer of the first conductive type. A selectively-ion-implanted-collector (SIC) region is then formed in the collector layer, and after that, a base layer is grown on the SIC region with an inversely graded impurity distribution profile.

Abstract: The present invention teaches a method and structure of enhancing the current gain characteristics of a bipolar junction transistor using a semiconductor substrate comprising a base, an emitter and a collector and an interface at the emitter, such that a carrier current conducts between the base and the emitter. Further, a first polysilicon layer is formed superjacent the interface, and is implanted with O.sub.2. Subsequently, the substrate is heated such that the emitter interface is obstructed by a silicon dioxide formation, thereby blocking a portion of carrier current from passing through the interface.

Abstract: A method for fabricating a super self-aligned bipolar junction transistor which reduces or eliminates emitter defects caused during critical etching steps by providing a non-critically thick dielectric etch stop (protection) layer (116) during all potentially damaging etching steps. An oxide or other dielectric layer (116, 130), is provided above the emitter region (152) of the semiconductor surface (110) during potentially damaging etching steps, such as dry etch procedures used to form critical device structures such as emitter opening 124 and sidewall spacers 146. Non-damaging etching procedures, such as wet etching, are used to remove dielectric protection layers (116, 130) to form less critical device structures, and/or form intermediate layer openings without damaging the silicon surface in the emitter (152), or other critical regions.

Abstract: A method of manufacturing a bipolar transistor including the steps of doping an impurity of the one conductivity type in a major surface portion of the semiconductor substrate to form a buried layer of the one conductivity type and growing an epitaxial layer on an entire surface on a major surface of the semiconductor substrate, forming a diffusion region of the opposite conductivity type in an emitter formation region on the major surface of the semiconductor substrate and forming a base connecting region in a base formation region to be in contact with the diffusion region of the opposite conductivity type, forming an insulating interlayer on the major surface of the semiconductor substrate including the diffusion region of the opposite conductivity type and the base connecting region, forming an emitter electrode layer contact hole reaching the diffusion region of the opposite conductivity type in an emitter formation region of the insulating interlayer and forming a collector region hole reaching the epit

Abstract: The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. For example, in one step, polysilicon gate electrodes for the FETs and polysilicon emitters for the BJTs are formed simultaneously. In another aspect of the invention, a polysilicon layer is used to reduce channeling which would otherwise occur during an implant step.

Abstract: A bipolar transistor has a base rink structure epitaxially grown from an overhang portion of a poly-crystal silicon base electrode and an epitaxial collector layer and an intrinsic base structure grown on a concave central portion of the base rink structure after a diffusion stage of a dopant impurity into the base rink structure, and the intrinsic base structure is electrically connected through a buried collector region passing through the concave central portion into an epitaxial collector layer, thereby maintaining the dopant impurity profile in the intrinsic base structure without deterioration of transistor characteristics.

Abstract: In a method of manufacturing a bipolar transistor by forming emitter regions of PNP and NPN transistors with diffusion of impurity from the polycrystalline silicon film into the substrate, the B-doped polycrystalline silicon film is deposited on the interlayer insulating film in which the emitter holes of the PNP and NPN transistors are made. Further, the interlayer insulating film is deposited on this film, and the portion of the insulating film which situated on the NPN transistor region is removed. Then, the thermal treatment is carried out in a high-concentration P atmosphere, so as to change the portion of the film which is located on the NPN transistor region to a P-doped polycrystalline silicon film. With this thermal treatment, the P-type and N-type emitter diffusion regions are formed on the base regions of the PNP and NPN transistors.

Abstract: The present invention teaches a method and structure of enhancing the current gain characteristics of a bipolar junction transistor. The method comprises the step of forming a patterned silicon dioxide layer superjacent a semiconductor substrate comprising a base, an emitter and a collector, such that a carrier current conducts between the base and the emitter. The silicon dioxide layer forms an interface on the substrate at the emitter. Further, a first polysilicon layer is formed superjacent both the patterned silicon dioxide layer and the interface, and is implanted with O.sub.2. Subsequently, the substrate is heated such that the emitter interface is obstructed by a silicon dioxide formation, thereby blocking a portion of carrier current from passing through the interface.

Abstract: On manufacturing a bipolar transistor, a field silicon oxide layer (7) having a beaked edge portion (bird's beak portion) is formed by a heat oxidation process using a silicon nitride film (5) as an oxidation mask. In this event, an edge of the nitride film is boosted up as a boosted portion by an upper part of the beaked edge portion. The upper part of the beaked edge portion is etched to form an undercut portion under the boosted portion. The undercut portion is filled with a base leading polysilicon (10) having impurities. On forming an insulator film (11) on the base leading polysilicon in a heated atmosphere, an outer base region (14) is formed in an epitaxial layer (3) by making the impurities diffuse from the base leading polysilicon towards the epitaxial layer in the heated atmosphere. Between the epitaxial layer and an edge portion of a nonboosted portion of the nitride film, a silicate glass (12) containing impurities is buried.

Abstract: A lateral bipolar transistor (10) includes a retrograde doping profile (21) that is formed within a substrate (11) to form the transistor's (10) collector region (14). A base region (16) that includes an inactive base area and an active base area (17) is formed in the collector region (14). An emitter (18) is formed within the active base area (17) wherein current (22) flows through the emitter (18) through the active base area (17) and through the collector region (14). The base region, the emitter, and a collector contact region are all formed by driving dopants from an overlying polysilicon layer.

Abstract: The present invention is directed to a method for forming a self-aligned epitaxial base transistor in a double polysilicon type process using non-selective low temperature epitaxy (LTE) to form the base layer. The present invention utilizes a thin very heavily doped LTE layer that is both a conductive etch stop and a diffusion source for doping the extrinsic base of the transistor. The deposition of the non-selective LTE base layer is followed immediately by the deposition of the conductive etch stop layer. A layer of undoped polycrystalline semiconductor is deposited on the conductive etch stop layer and subsequently ion implanted. Oxide and nitride insulating layers are deposited and the structure is patterned using a highly directional reactive ion etch to form the emitter window leaving a thin layer of the polycrystalline layer. The thin polycrystalline layer is selectively removed in a KOH solution leaving the conductive etch stop layer.

Abstract: A process is provided for forming a bipolar transistor and a structure thereof. In particular a single polysilicon self-aligned process for a bipolar transistor having a polysilicon emitter is provided. A sacrificial layer defining an opening is provided in a device well region of a substrate, and, after forming a self-aligned base region within the opening, emitter material is selectively provided in the opening to form an emitter-base junction. The sacrificial layer functions as a mask for ion implantations to form the base region, and if required, an underlying local collector region. The sacrificial layer is removed, to expose the well region adjacent sidewalls of the emitter structure. A self-aligned link region implant may be performed before forming isolation on exposed sidewalls of the emitter structure. Extrinsic base contacts are formed in the surface of the surrounding well region.

Abstract: A method of fabricating a semiconductor device includes the steps of forming a base diffusion layer in a predetermined region in a semiconductor substrate of a first conduction type, the base diffusion layer being of a second conduction type; forming first insulating films and simultaneously forming an emitter lead-out electrode and a collector lead-out electrode in regions above an emitter-contact-forming region and a collector-contact-forming region, the first insulating films extending on the emitter and collector lead-out electrodes, the emitter and collector lead-out electrodes including impurity corresponding to the first conduction type; forming second insulating films at sides of the emitter and collector lead-out electrodes; forming a base contact; forming a base lead-out electrode including impurity corresponding to the second conduction type; diffusing the impurity from the emitter lead-out electrode, the collector lead-out electrode, and the base lead-out electrode to form an emitter diffusion lay

Abstract: A fabrication method for semiconductor devices connecting a multi-crystal semiconductor thin film and a semiconductor region including a high density of an impurity formed in a single crystal semiconductor substrate. After forming a N-type semiconductor region as the emitter by ion implanting, for instance, as into a P-type semiconductor region as the base, a polysilicon thin film 114 is deposited so as to be implanted with As ions and then heat treated. In this case, an amorphous portion of the N-type semiconductor region and an amorphous silicon thin film in contact therewith are transformed by solid phase epitaxial growth so as to form a single crystal semiconductor region, a single-crystalline silicon thin film, and a polysilicon thin film, thus forming a bipolar element having an emitter.

Abstract: A bipolar transistor includes a base region made of silicon crystal doped with a first impurity to a first level so as to establish a first carrier concentration in the base region and an emitter region made of silicon crystal doped with a second impurity to a second level substantially larger than the first level by a predetermined factor so as to establish a second carrier concentration in the emitter region, in which the second impurity exceeds the solubility limit of the second impurity in silicon crystal. The first and second levels are chosen in such a range that a difference in the carrier concentrations between the emitter region and the base region decreases substantially with increasing impurity level in the base region.

Abstract: A method of manufacturing a bipolar transistor by use of low temperature emitter process is disclosed. After completion of the usual base and collector formation in a vertical bipolar transistor, an emitter opening is etched in the insulator layer over the base layer at selected locations. A thin layer (less than 500 .ANG.) of in-situ doped amorphous silicon is deposited over the substrate and heated to densify for 30 to 60 minutes at about 650.degree. C. Subsequently an in-situ doped polysilicon layer of 100 to 200 nm is deposited over the amorphous Si film preferably at about 600.degree. C. Subsequently the layers are heated below 600.degree. C. for several hours to convert partially the amorphous Si into a monocrystalline emitter layer over the base regions.

Abstract: According to this invention, in a method of manufacturing a bipolar transistor, a first oxide film, a nitride film, a first polysilicon film containing boron, and a second oxide film are formed on a substrate. A first opening is formed in the second oxide film and the first polysilicon film. The nitride film and the first oxide film are etched in and near the first opening to form overhung portions between the substrate and the first semiconductor film around the first opening. A second polysilicon film for burying the overhung portions is formed on the entire surface of the resultant structure. Thereafter, boron in the second polysilicon film is thermally diffused in the substrate to form an external base region and a link region. The second polysilicon film is etched to leave the second polysilicon film at only the overhung portions. After an internal base region formed in the substrate. Thereafter, an emitter region formed in the internal base region.

Abstract: A bipolar transistor having a silicon oxide film having a stoichiometric composition ratio of silicon to oxygen controlled to 1 to 2 formed at the boundary between a monocrystalline layer and a polycrystalline layer. In fabrication, a natural oxidized film formed on the surface of an intrinsic base region of a single-crystal is removed in an ultrahigh-vacuum chamber. Subsequently, oxygen ions are supplied to the surface of the base region at room temperature to form a silicon oxide film. Further, silicon molecular beams are supplied in the same chamber to form the polycrystalline silicon layer. The current gain factor h.sub.FE of the bipolar transistor thus formed can be greatly improved.

Abstract: In the method of manufacturing a semiconductor device, a buffer oxide film, an oxidation-resistant film and a first poly-Si film containing a p-type impurity are successively formed to form a laminate structure on the n-type collector region, followed by forming a protective oxide film by CVD. Then, an opening portion reaching the oxidation-resistant film is formed, followed by forming a second protective insulation film to cover the surface of the first poly-Si film exposed at the side wall of the opening portion. The oxidation-resistant film is excessively etched using the protective insulation films as an etching mask so as to expose the buffer oxide film and to form a bore below the first poly-Si film. The exposed buffer oxide film is removed, followed by filling the bore with a second poly-Si film. Then, a heat treatment is performed under an oxidative atmosphere to form a thermal oxide film covering the surface of the second poly-Si film.

Abstract: A method of controlling the interfacial oxygen concentration of a monocrystalline/polycrystalline emitter includes the steps of: passivating the monocrystalline silicon surface by immersing the wafer in a diluted HF acid solution; transferring the wafer into a high vacuum environment; heating the wafer to between 400.degree. and 700.degree. C.; exposing the monocrystalline silicon surface to a gas having a partial pressure of oxygen of between 10.sup.-5 to 1 Torr for between 1 and 100 minutes; and, depositing polysilicon onto the monocrystalline silicon surface.

Abstract: A method for manufacturing a bipolar transistor semiconductor device for preventing a degradation phenomenon of the transistor resulting from a reduction of a lateral electric field intensity. This is achieved by grading an emitter junction by way of refilling an emitter window with polycrystalline silicon. The resulting transistor structure overcomes the etch stop barrier by removing layer of oxide disposed below a layer of nitride along the region where formation of removing sidewalls of polycrystalline silicon have been formed. Subsequently, a doping distribution of the laterally graded emitter junction can easily be obtained by refilling the emitter window with the removed oxide layer with polycrystalline silicon. Because the shallowness of the oxide layer can be selectively and easily controlled, a thickness of the sidewalls is chosen which most efficiently raises the lateral electric field intensity of the transistor junction.

Abstract: A process for producing a semiconductor device for an integrated circuit is disclosed. A patterned structure made of first polycrystalline silicon and a first thermal oxide film is formed on an underlayer or foundation. A protrusion or raised portion is formed by using the patterned structure as a mask. A first insulating region is formed around the protrusion. After removing the first thermal oxide film an remaining portion of the patterned structure is thermally oxidized to obtain second thermal oxide film while the peripheral area of the surface of the protrusion is exposed. A second polycrystalline silicon pattern layer with a high impurity concentration is formed so as to contact with the exposed surface of the protrusion and with sideface of the second thermal oxide film, and to extend onto the first insulating layer.

Abstract: This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignment of the above mentioned elements using a single lithographic and masking step. The structure of the transistor, in addition to having the self-algined elements, incorporates a composite dielectric isolation layer which not only permits the carrying out of a number of functions during device fabrication but also provides for desired electrical characteristics during device operation. The composite isolation layer consists of an oxide layer adjacent the semiconductor surface; a nitride layer on the oxide layer and an oxide layer on the nitride layer in the final structure of the device.

Abstract: A method of manufacturing a bipolar transistor. A first mask material film pattern is formed on an internal base region prospective portion on a collector region of a first conductive type, and then a first conductive film is deposited. A recess around the projection of the mask film pattern are transferred on the surface of the first conductive film. After a second mask material film pattern is buried in the recess, the first conductive film is selectively etched using the second mask material pattern as a mask, thereby exposing the first mask material film pattern. The first conductive film is continuously, selectively etched by anisotropic etching using the exposed first mask material film pattern and the second mask material film pattern as etching masks to form a first opening between the two mask material film patterns. An impurity of a second conductivity type is doped in the wafer through the first opening to form an external base region of the second conductivity type.

Abstract: According to a method of manufacturing a high-frequency bipolar transistor, a p-type base region is formed on an n-type silicon substrate. A first oxide film and a nitride film are formed on the base region. A base contact hole is formed by etching, and a first polysilicon film containing a p-type impurity and serving as a base electrode is formed thereon. A second oxide film having a thickness larger than that of the first oxide film is formed by thermal oxidation around the base contact hole to surround the first polysilicon film. A portion of the nitride film which is not covered with said second oxide film and a portion of the first oxide film therebelow are removed by etching to form an emitter contact hole. A second polysilicon film including an n-type impurity and serving as an emitter electrode is formed in the emitter contact hole. The n-type impurity in the second polysilicon film is diffused in the substrate by annealing to form an n-type emitter region.

Abstract: A method of manufacturing a semiconductor device forms an intrinsic base layer by doping an impurity in the emitter polysilicon electrode into the intrinsic base region of the surface of a semiconductor substrate by heat treatment through the emitter lead-out part hole self-aligned to the base lead-out electrode. Thus, beneath the insulation film of the substrate surface between the base lead-out part hole and emitter lead-out part hole, the outer marginal part of the intrinsic base layer and the inner marginal part of the extrinsic base layer overlap uniformly. Still more, since the diffusion of the impurity by heat treatment is very fast in the polysilicon emitter electrode as compared with that in the silicon substrate, an extremely shallow intrinsic base layer may be formed.

Abstract: In a bipolar transistor, having a micronized structure for a high-speed LSI, which is fabricated by a self-alignment technology, a barrier insulating film is buried in a portion around an emitter layer so as to be deeper than a junction level between an active base layer and a collector layer. When a polysilicon film pattern which defines an active base region and serves as a portion of a base electrode is formed on a wafer surface, a surface portion of a photoresist serving as an etching mask is converted to a carbonized layer by ion implantation. When a micronized emitter layer is formed by a polysilicon-emitter technology, ion implantation is performed before deposition of the polysilicon film or an impurity is doped in the polysilicon film simultaneously with deposition, and rapid thermal annealing is performed so as to activate the doped impurity.

Abstract: In a method for manufacturing a heterojunction bipolar transistor using a silicon microcrystal as an emitter, a mask 4 having an opening on an element forming region of the main surface of an n-type silicon monocrystal substrate 1 serving as a collector, a p-type outer base 5 is formed on a part of the element forming region of the main surface of the substrate via the opening of the mask 4 by ion-implanting p-type impurity therein, a p-type inner base 6 is formed on the entire surface of the element forming region of the substrate 1 by ion-implanting p-type impurity therein after removing the mask 4, and an n-type emitter 8 is formed by depositing an n-type silicon microcrystal layer on the inner base 6 at a growth velocity of 15 .ANG./sec by a plasma chemical vapor deposition method in a state that the temperature of said substrate 1 is maintained at a constant temperature between 460.degree. to 550.degree. C.

Abstract: A method of forming a self-aligned contact to a transistor component located on a semiconductor substrate comprising forming a transistor component opening in a masking layer overlying a semiconductor substrate and using epitaxial lateral overgrowth to form a self-aligned contact, the epitaxial overgrowth beginning in the masking layer opening at an upper surface of the semiconductor substrate and extending normal to and laterally over the masking layer surface.

Abstract: A structure and process for fabricating a fully self-aligned high-performance bipolar semiconductor device is disclosed. In accordance with one embodiment of the invention, a substrate is provided having a first surface. A heavily doped buried layer is formed in the substrate extending from the first surface and a lightly doped epitaxial layer overlies the first surface. An isolation region is formed in the epitaxial layer dividing the epitaxial layer into an active surface region and an isolation region. A base electrode is formed on a first portion of the active surface region having an opening which exposes a second portion of the active surface region. An emitter electrode, which is self-aligned to the base electrode, overlies a portion of the base electrode and extends through the opening in the base electrode making contact with the second portion of the active surface region.

Abstract: A fully self-aligned polycrystalline silicon emitter bipolar transistor. Self-alignment of the p.sup.+ base contact (12) is achieved by using oxidized sidewalls (8) (sidewall spacers) of the emitter mesa (7) as part of the p.sup.+ base contact implantation mask. Collector contact (13) alignment can be achieved using oxidized sidewalls (17) of polycrystalline silicon alignment mesas (14) defined in the same polysilicon as the emitter mesa (7) but deposited on oxide (2) rather than the implanted base region (5).

Abstract: A bipolar transistor and method of making the same is disclosed. The transistor has an emitter region which is diffused from polysilicon into the intrinsic base region, where the polysilicon is doped with two dopant species of different diffusivity. The impurity concentration of the higher diffusivity species, for example phosphorous, can be selected to define the emitter junction depth, which is preferably shallow, while the impurity concentration of the lower diffusivity species, for example arsenic, can be selected to provide a high conductivity emitter electrode, as well as reduce the sensitivity of the emitter electrode to counterdoping from the implantation of the extrinsic base region. The structure is compatible with BiCMOS processing, as the same anneal can be used to diffuse the emitter and the source/drains of the MOS transistors, with the emitter junction depth optimized via the implant conditions of the higher diffusivity species.

Abstract: A bipolar transistor having an intrinsic base portion for forming emitter-base PN junction with an emitter region and an extrinsic base portion for connecting a base electrode is disclosed. A concavity is formed between the intrinsic and extrinsic base portions, and the intrinsic base portion is electrically connected to the base electrode through a passage formed under the concavity and through the extrinsic base portion. The emitter region is contacted at its side to an insulating film formed in the concavity.

Abstract: In a method of manufacturing a semiconductor device, when contact holes are to be formed in an insulating film formed on a monocrystalline or polycrystalline semiconductor layer, the contact holes can be formed using a polycrystalline semiconductor layer formed on the insulating film as a mask. Therefore, the lithographic step of forming the contact holes in the insulating film formed on the monocrystalline or polycrystalline semiconductor layer can be eliminated.

Abstract: A polysilicon layer may need to have electrical characteristics which are relatively uniform from wafer to wafer. The use of polysilicon as a resistor is one such example. In order to obtain the requisite uniformity, the temperature of the wafers which are receiving the polysilicon must all be the same within a tight tolerance. The reaction takes place in a furnace which takes a long time to reach the requisite temperature tolerance. While the furnace is stabilizing the temperature, oxide, which is an insulator, is growing on the contact locations of the various substrates. To minimize the deleterious oxide formation, a thin layer of polysilicon is deposited at a time significantly prior to the time that the furnace stabilizes which ensures a good, low-resistance contact. The remainder of the polysilicon is then deposited on the thin layer of polysilicon after the temperature has stabilized to obtain the requisite wafer-to-wafer resistance uniformity.

Abstract: A method of forming semiconductor device contacts includes the steps of: providing a semiconductor substrate having at least two features thereon whereat it is desired to make electrical connections; forming a layer of etch stop material having a first etch characteristic over each of the features; forming a layer of dielectric material having a second etch characteristic over each of the features; simultaneously etching at least two vias through the layer of dielectric material using an etchant selective to the layer of dielectric material so as to substantially stop on the layer of etch stop material, the at least two vias including a via over each of the features; and extending the vias through the layer of etch stop material so as to expose the features for subsequent electrical connections.

Abstract: In a transistor fabrication process, the use of a three-step base doping technique enables the characteristics of a vertical bipolar transistor to be controllably reproduced at highly optimal values from run to run. Insulating spacers (52A) are employed in forming a self-aligned base contact zone (58B). A shallow emitter (46) is created by outdiffusion from a patterned non-monocrystalline semiconductor layer (38A) that serves as the emitter contact. The fabrication process is compatible with the largely simultaneous manufacture of an insulated-gate field-effect transistor of the lightly doped drain type.

Abstract: A process is disclosed for fabricating bipolar transistors having self aligned and closely spaced polycrystalline silicon base and emitter electrodes. The process is especially amenable to integration with the fabrication of MOS transistors to form BiMOS integrated circuits. In accordance with one embodiment of the invention, a P type polycrystalline silicon layer is deposited overlying an N type silicon substrate. The polycrystalline silicon layer is patterned to form base contact electrodes and to leave exposed a portion of the surface of the N-type substrate. An electrically insulating layer is formed overlying the polycrystalline silicon base contacts and the exposed silicon substrate. Sidewall spacers are formed on the electrically insulating layer at the sidewalls of the base contact electrode.

Abstract: This invention discloses a method of manufacturing an SST bipolar transistor, and the manufacturing method is capable of defining the size of a base region of the SST bipolar transistor. An insulating film and a spacer film serving as a spacer are sequentially formed in a bipolar transistor forming region on the main surface of a semiconductor substrate. Thereafter, the spacer film is patterned into a spacer film pattern for defining the size of the base region. A second insulating film, a base electrode pattern and a third insulating film are sequentially formed on the spacer film pattern. A first opening which reaches the spacer film pattern through the second insulating film, the base electrode pattern and the third insulating film is formed. The spacer film pattern is etched from the first opening to form a second opening having a diameter larger than that of the first opening. The insulating film exposed in the second opening is etched.

Abstract: A method with less processing steps for making a BiCMOS semiconductor device which can be used both in high-integration, high-speed digital devices and in precise analog devices by forming within a single substrate a CMOS transistor, a metal contact emitter bipolymer transistor having the high load driving power and highly effective matching characteristics, and a polycrystalline silicon emitter bipolar transistor having a high-speed characteristic at a low current level. Said device includes a first and a second MOSFET, and a first and a second bipolar transistor on a first conductivity-type silicon substrate, wherein performing a second conductivity-type of ion-implantation for producing a first substrate region to thereon form the first MOSFET, and a third and a fourth substrate region to thereon form the first and second bipolar transistors, respectively on said substrate. The second MOSFET is subsequently formed in a second substrate region being located between the first and third substrate regions.

Abstract: A process for fabricating a CMOS compatible bipolar transistor is described. The transistor, which is of the polysilicon emitter type, is fabricated by forming a p-type layer in a well, providing a polysilicon emitter in contact with the layer, using the emitter as a mask to implant p.sup.+ -type base contact regions, and applying contacts to the device.

Abstract: A self-aligned process for the fabrication of a walled-emitter transistor includes the formation of an isolated device island on the surface of a semiconductor wafer. A layer of dielectric is then formed on the wafer, leaving only part of the device island exposed. A `substitute emitter` of silicon nitride is then formed on the exposed part of the device island in the position which will subsequently be occupied by the emitter. The exposed surface of the device island is then oxidized, some oxide being formed beneath the periphery of the substitute emitter. Oxide spacers are then formed non-lithographically about the periphery of the substitute emitter, after which the substitute emitter is removed and a base is formed in the semiconductor thus exposed. An emitter is then formed in the exposed semiconductor.