Abstract: A mixed bipolar-CMOS self-aligned process and integrated circuit provide a high performance NPN bipolar transistor in parallel to fabrication of a PMOSFET and an NMOSFET. Gate and base contacts are formed in a first polysilicon layer. The base contacts are implanted with P+ ion concentrations for diffusing base contact regions of the substrate in a later drive-in step. Source and drain contacts and emitter contacts are formed in a second polysilicon layer. The source and drain contacts are formed as a unit and then separated into discrete contacts by a spin-on polymer planarization and etch-back procedure. Lightly-doped lateral margins of the source, drain and base regions are ion-implanted in an initial low concentration (e.g. about 10.sup.13 atoms/cm.sup.2). The gate and base contact structures serve as a mask to self-align the implants. Then, the gate and base structures are enclosed in an oxide box having sidewalls.

Abstract: A bipolar transistor structure wherein the emitter zone is produced by outward diffusion from etching residues which are formed by deposition of conductive material and re-etching, with the etching residues forming part of the emitter terminal region. In addition to individual transistors, pairs of transistors having coupled emitters can also be produced and employed in hig precision differential amplifiers. Memory cells can also be produced which have low surface requirements, particularly due to the reproduceable attainment of emitter widths below one micron. Since the methods enable the production of completely self-aligned transistors, they can be implemented with straightforward steps which are largely independent of lithography. Emitter widths in the range of about 0.2 to 0.5 microns can be produced.

Abstract: A semiconductor device comprising a semiconductor substrate with at least one semiconductor region formed in it, a polycrystalline silicon layer formed in contact with the semiconductor region and a metal layer formed on the polycrystalline silicon layer. The peripheral portion and outer edges of the polycrystalline silicon layer are covered with an insulation layer.

Abstract: In an NPN transistor, a contact base region, an active base region, and a further base region are formed in the silicon substrate. The further base region is between the contact base region and the active base region, and is adjacent to the contact base region and the active base region. The further base region has a depth shallower than that of the contact base region and deeper than that of the active base region. In the method of forming the bipolar transistor, a polysilicon semiconductor layer is formed on a semiconductor substrate. The polysilicon semiconductor layer is partially etched to form a base leading electrode and an emitter leading electrode. A semiconductor impurity is implanted into a base forming region of the silicon substrate via that portion where the polysilicon semiconductor layer is removed.

Abstract: In fabricating the contact, the electrode layer of polycrystalline silicon whose rim portion is bonded via a layer portion of insulating material to the substrate, is used at least throughout the length of a part of its rim portion for the lateral delimitation of a etching process, as an etch mask, in the course of which a frame-shaped layer portion is formed underneath the rim portion of the electrode layer, and the contact area of the substrate as bordering on the layer portion is exposed. Following the deposition of a metal layer of a metal forming a silicide in a thickness smaller than the thickness of the layer portion, and the heating for forming the silicide, the metal which has so far not reacted with the silicon, is removed by using an etching agent selectively dissolving the metal.

Abstract: The method of manufacturing a semiconductor device according to the present invention comprises the step of forming an opening in use for forming an emitter region. This step uses the independent etching characteristics of N and P type polysilicons to simplify the opening forming process, which is very complicated in the conventional method. To be more specific, the impurity doped in the first polysilicon layer at a high concentration is diffused into the second polysilicon layer adjacent to the first polysilicon layer. When the impurity doped in the first polysilicon layer is diffused into the second polysilicon layer, the diffused impurity dominantly determines the conductivity type of that portion of the second polysilicon layer, into which the impurity is diffused. Therefore, one of the first polysilicon layer and the second polysilicon layer portion is etched by a solution, independently of the other.

Abstract: A well structure for a semiconductor device has a dopant profile such that the maximum net dopant level is below the device surface. This is achieved by a two stage doping with materials of opposite conductivity type.

Abstract: In a method for fabricating a favorable bipolar semiconductor device in which the extrinsic base and emitter diffusion holes are formed in self-alignment, an optimum structure between the extrinsic base and instrinsic base is realized. By controlling the concentration of the impurities in the extrinsic base, the base contact and emitter region can be finely formed in self-alignment, and occurence of damage or contamination in the intrinsic base region is inhibited.

Abstract: A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks.

Abstract: A semiconductor integrated circuit device is disclosed which comprises a bipolar transistor and a field effect transistor, in which a gate electrode of the field effect transistor and a collector electrode of the bipolar transistor are formed from a common electrode layer of a high impurity concentration, and in which the collector region of the bipolar transistor comprises a region of a high impurity concentration having a conductivity type the same as that of the collector region of the bipolar transistor.

Abstract: An improved integrated circuit structure is disclosed comprising bipolar and MOS devices formed on the same substrate. The bipolar devices have at least the emitter and the collector contact portions formed from a polysilicon layer which results in raised contacts. The MOS devices are similarly formed with raised gate contact portions formed from the same polysilicon layer. Metal silicide is formed over at least a portion of the base, source, and drain regions to provide conductive paths to the base, source, and drain contacts. In one embodiment, the base, source, and drain contacts are also formed from the same polysilicon layer to permit formation of a highly planarized structure with self-aligned contacts formed by planarizing an insulating layer formed over the structure sifficiently to expose the upper surface of the contacts.

Abstract: Regions of the substrate which are to be the collector sinker and the active area of a bipolar transistor are isolated by forming a trench about them and filling it with a dielectric. The dielectric can be oxide formed in a LOCOS process. A dielectric body, which may be nitride, is formed on part of the active area, and base contacts implanted using it as a mask. Polysilicon is deposited over the whole and then cut to form future metallization-to-base contacts. The dielectric body is removed and the base implanted through the resulting aperture. Oxide spacers are formed on the sidewall of the aperture and polysilicon deposited. The polysilicon is doped and used to produce the emitter by driving the dopant into the substrate between the oxide spacers.

Abstract: A process for making a semiconductor device including a semiconductor layer heavily doped to a predetermined dopant concentration and a multilayer contact system in contact with a surface portion of the heavily doped semiconductor layer, the multilayer contact system comprising a metal silicide layer of the silicide of a refractory metal, the metal silicide layer directly contacting the surface portion of the heavily doped semiconductor layer and being lower in dopant concentration than the predetermined dopant concentration of the semiconductor layer, a barrier layer of at least one metal on the metal silicide layer, and an electrode layer including a highly conductive metal on the barrier layer.

Abstract: An improved method is described for constructing one or more integrated circuit components including bipolar and MOS devices on a silicon substrate without damaging areas of the substrate wherein active elements of the integrated circuit components will be formed. The method comprises forming multilayer pedestals of masking materials over the active regions of the substrate and subsequently removing these masking materials using wet etching to avoid damage to the substrate by dry etching.

Abstract: A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has a typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks.

Abstract: A process for the simultaneous production of self-aligned bipolar transistors and complementary MOS transistors on a common silicon substrate wherein n-doped zones are produced in the p-doped substrate and insulated npn-bipolar transistors are formed into the n-doped zones. The n-zones form the collectors of the transistors and are modified according to conventional technology by additional process steps such that bipolar transistors are formed which are self-aligning both between the emitter and the base and also between the base and collector with extremely low-ohmic base terminals consisting of polysilicon and a silicide. Storage capacitances can also additionally be integrated into the structure. The use of the base terminals thus produced permits very small lateral emitter-collector distances. The combination of dynamic CMOS memory cells with fast bipolar transistors is made possible by the integration of the storage capacitances.

Abstract: A method for fabricating bipolar transistors comprises a step of forming a multi-layered film consisting of a polysilicon film (600), a silicon nitride film (202) and a silicon oxide film (104) on an emitter region (7) and on an external base region (54, 56), a step of causing the silicon oxide film (104) to recede inwardly from the polysilicon film (600) and silicon nitride (202) film, a step of patterning the polysilicon film (600) by using the inwardly receded oxide film (104) as a mask while defining the external base region (54, 56), a step of forming an emitter region (7) and an active base region (6) by using the patterned polysilicon as an impurity diffusion source while self-alignedly forming an external base region (54, 56), and a step of self-alignedly forming an insulation film (107, 203) for electrical isolation between base and emitter electrode interconnections (9) on the side wall of the polysilicon film (603) by means of anisotropic etching.

Abstract: A method for making a semiconductor device having transistors comprising the active regions which are protected by polysilicon layer during the whole process from damages due to the other processing, that is dry etching, etc. and a minimized base region so as to provide a high operating speed and a minimium size thereof as well as lowest power consumption features.

Abstract: A semiconductor structure is provided by forming an isolation region in a portion of a semiconductor layer, forming a doped region in the semiconductor layer adjacent the isolation region, such doped region having a conductivity type opposite the conductivity type of the semiconductor layer, selectively masking a surface of the semiconductor layer exposing a portion of the doped region adjacent to the isolation region, and selectively etching the exposed portions of the adjacent doped region forming a depression having converging side walls separated from the isolation region by portions of the doped region. The semiconductor layer is an epitaxial layer providing the collector region of a transistor. The bottom portion of the depression is lightly doped to provide an active base region for the transistor. The active base region is electrically connected to the base contact through the more heavily doped region formed in the semiconductor layer.

Abstract: A method for manufacturing semiconductor devices is presented. The method comprises the steps of opening two windows on an insulating layer covering a semiconductor substrate, and forming a polysilicon layer over the entire surface of the insulating layer and the windows. Donor and acceptor impurities are respectively implanted into the portions of the polysilicon layer corresponding to the two opening windows through the appropriate photoresists. The doped impurities are thereafter subjected to annealing to form two different conduction type regions under the two opening windows. Thereafter, a metal layer and a photoresist are deposited in order to make the metal electrodes for each conduction region. Thus, the patterning of the polysilicon can be made in self-alignment with the etching mask, and the formation of two different conduction type semiconductor regions are simultaneously attained.

Abstract: Semiconductor device, such as bipolar transistor, is made by molecular beam epitaxy, wherein a emitter layer (27) and overriding contact regions (28) of polycrystalline silicon are grown continuously on a silicon substrate (23+26) without breaking high vacuum, thus eliminating the adverse interface of natural oxide film under the polycrystalline silicon layer (28) and the adverse donor-acceptor compensation while attaining a well controlled h.sub.FE and enabling a shallow emitter junction.