Abstract: The method for fabricating a semiconductor device includes steps of forming a layered structure by sequentially depositing a silicon film containing an impurity, a metal silicide film, and an amorphous silicon film containing an impurity, forming an electrode or an interconnect in a three-layer structure by selectively etching the amorphous silicon film, the metal silicide film and the silicon film in this order, and diffusing the impurity in the amorphous silicon film into the metal silicide film by a thermal process. Thus, the impurity is supplied from the amorphous silicon film to the metal silicide film so that the ion-implantation as required in the prior art is not necessary.

Abstract: A method for fabricating a semiconductor device, such as a MOS (metal-oxide semiconductor) transistor, with self-aligned silicide is provided. This method can prevent junction leakage between the silicide and the substrate so as to allow the resultant semiconductor device to have reliable performance. The method includes the steps of preparing a semiconductor substrate; forming at least one transistor element over the substrate, the transistor element including a pair of source/drain regions, a gate, a dielectric layer over the gate, and a spacer on the sidewall of the gate; and performing an ion-bombardment process so as to transport one part of the dielectric layer that is adjacent to the top of the spacer to beside the bottom of the spacer.

Abstract: Low resistivity metal silicide layers are formed on a gate electrode and source/drain regions at an optimum thickness for reducing parasitic series resistances with an attendant consumption of silicon from the gate electrode and source/drain regions. Consumed silicon from the gate electrode and source/drain regions is then replaced employing metal induced crystallization, thereby avoiding a high leakage current. Embodiments include depositing a layer of amorphous silicon on the metal silicide layers and heating at a temperature of about 400.degree. C. to about 600.degree. C. initiating metal induced crystallization, thereby causing the metal silicide layers grow upwardly as silicon in the underlying gate electrode and source/drain regions is replaced.

Abstract: A silicon semiconductor substrate including a silicon semiconductor layer at one of upper and lower surfaces thereof, the silicon semiconductor layer being composed of polysilicon or noncrystal silicon and containing oxygen in the range of 2 atomic % to 20 atomic % both inclusive, nitrogen in the range of 4 atomic % to 20 atomic % both inclusive, or both nitrogen at 2 atomic % or greater and oxygen at 1 atomic % or greater. The polysilicon or noncrystal silicon semiconductor layer acts as a core for extrinsic gettering. In the silicon semiconductor substrate, the gettering performance is not deteriorated, even if the silicon semiconductor substrate experiences thermal treatment. Thus, it is possible to get rid of contamination caused by heavy metals in the silicon semiconductor substrate.

Abstract: A process for reducing halogen concentration in a material layer (56) includes the deposition of a dielectric layer (58) overlying the material layer (56). An annealing process is carried out to diffuse halogen atoms from the material layer (56) into the overlying dielectric layer (58). Once the diffusion process is complete, the dielectric layer (58) is removed.

Abstract: A method is provided for forming silicide surfaces on source, drain, and gate electrodes in active devices to decrease the resistance of the electrode surfaces, without consuming the silicon of the electrodes in the process. Silicide is directionally deposited on the electrodes so that a greater thickness accumulates on electrode surfaces, and a lesser thickness accumulates on the gate sidewall surfaces isolating the gate from the source/drain electrodes. Then, the electrodes are isotropically etched so that the lesser thickness on the sidewalls is removed, leaving at least some thickness of silicide covering the electrodes. In further steps, the electrodes are masked with photoresist, and any silicide deposited in the region of field oxide around the electrodes is removed.

Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment. P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

Abstract: An improved method for forming a self-aligned silicide structure with reduced bridging effect is disclosed. The method includes forming a gate oxide on a substrate. Then a polysilicon layer is formed on the gate oxide. The polysilicon layer and the gate oxide are then patterned using a photoresist mask which defines a gate region. Next, the substrate is lightly-doped to form lightly-doped source/drain regions. Dielectric spacers are formed on a sidewall of the gate, and portions of the polysilicon layer and the substrate are removed with the dielectric spacers serving as a mask. A conductive layer is formed on the gate and the substrate, and is then silicided. Afterward, the unsilicided portions of the conductive layer are removed. Finally, heavily-doped source/drain regions are formed on the substrate with the dielectric spacers serving as a heavy-doping mask.

Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment. P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

Abstract: A method of forming cobalt silicide on source/drain regions and polysilicon gate areas of an MOS integrated circuit uses an improved technique to prevent unwanted oxidation of cobalt or growth of silicide on other areas of device. A thin titanium nitride (or titanium tungsten) film is deposited on top of a cobalt film following the steps of patterning the polysilicon gate, source/drain implant and sidewall oxide spacer deposition and etch. The titanium nitride film allows formation of defect-free cobalt silicide during an elevated-temperature anneal. Without the titanium nitride film, the cobalt is likely to oxidize and/or form cobalt silicide in unwanted regions of the device, which can cause device failure.

Abstract: In a method for fabricating an offset polysilicon thin-film transistor through the formation of silicide, the width of offset regions can be controlled as a narrow width of below 1 .mu.m. Drain voltage is decreased due to the reduction of the offset regions' width. The effect of an increased parallel resistance and a bias voltage dependency of an overlap capacitance due to the arrangement of low concentration ion region reduces leakage current and improves the response to applied voltages. Also, gate voltage is decreased due to the decreased gate resistance when the polysilicon of the gate is substituted with the silicide.

Abstract: A process for forming a titanium silicide local interconnect between electrodes separated by a dielectric insulator on an integrated circuit. A first layer of titanium is formed on the insulator, and a layer of silicon is formed on the titanium. The silicon layer is masked and etched to form a silicon strip connecting the electrodes, and an overlying second layer of titanium is formed over the silicon strip. The titanium and silicon are heated to form nonsilicidized titanium over a strip of titanium silicide, and the nonsilicidized titanium is removed.

Abstract: A method is described for fabricating a lightly doped drain MOSFET integrated circuit device which overcomes the polycide peeling problems. A pattern of gate electrode structures is formed upon a semiconductor substrate which each includes a gate oxide, a polysilicon layer and an amorphous refractory metal silicide. The resulting structure may be annealed in oxygen at this time to change the refractory metal silicide from it deposited amorphous phase into its crystalline phase. This causes the formation of a thin layer of silicon dioxide upon the exposed silicon substrate, the exposed polysilicon layer and the exposed metal silicide layer. A pattern of lightly doped regions in the substrate is formed by ion implantation using the polycide gate structures as the mask. A dielectric layer is blanket deposited over the surfaces and spacer structures formed by anisotropic etching.

Abstract: A process for the formation of a planar epitaxial cobalt silicide and for the formation of shallow conformal junctions for use in semiconductor processing. A cobalt silicide and titanium nitride bilayer is formed. The titanium nitride layer is chemically removed. Ions with or without a dopant are then implanted into the cobalt silicide layer. During the ion implantation, at least a portion of the cobalt silicide layer is transformed into an amorphous cobalt silicon mixture while the non-amorphous portion remains single crystal. If the ion implantation contains dopants, then after the implantation is completed, both the amorphous and non-amorphous portions of the cobalt silicide layer contain the dopants. The substrate is then annealed in either an ambient comprising a nitrogen gas or in an oxidizing ambient. During the anneal, the amorphous portion of the silicon substrate recrystallizes into a single crystal cobalt silicide layer.

Abstract: In forming a MISFET having a salicide structure, a polysilicon film forming a gate electrode in the MISFET is constructed of a first silicon film having a high n-type impurity concentration on the side of a gate insulating film and a second silicon film having a low n-type impurity concentration on the surface side of the gate electrode. Further, a Ti film is deposited on the second silicon film. The Ti film and the second silicon film are annealed twice at proper different temperatures to thereby promote a silicide reaction and form a low-resistance silicide layer in the second silicon film.

Abstract: The phase transformation temperature of a metal silicide layer formed overlying a silicon layer on a semiconductor wafer is lowered. First, a refractory metal is disposed proximate to the surface of the silicon layer, a precursory metal is deposited in a layer overlying the refractory metal, and the wafer is heated to a temperature sufficient to form the metal silicide from the precursory metal. The precursory metal may be a refractory metal, and is preferably titanium, tungsten, or cobalt. The concentration of the refractory metal at the surface of the silicon layer is preferably less than about 10.sup.17 atoms/cm.sup.3. The refractory metal may be Mo, Co, W, Ta, Nb, Ru, or Cr, and more preferably is Mo or Co. The heating step used to form the silicide is performed at a temperature less than about 700.degree. C., and more preferably between about 600.degree.-700.degree. C.

Abstract: Disclosed is a process for the formation of a tungsten silicide layer on an integrated circuit structure of a semiconductor wafer mounted on a susceptor in a vacuum chamber, wherein the tungsten silicide layer is applied at a temperature of at least 500.degree. C. and the susceptor has an aluminum nitride surface. After the chamber has been cleaned with one or more fluorine-containing etchant gases, the improvement comprises depositing a layer of tungsten silicide on the surface of the susceptor prior to an initial deposition of tungsten silicide on a wafer mounted on the susceptor after cleaning with the fluorine-containing etchant gases.

Abstract: Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

Abstract: A method is described for fabricating an integrated circuit with polycide gate electrodes in which there is no delamination of the overlying dielectric layer. A polysilicon layer over a gate dielectric is provided on a silicon substrate. A silicide layer is formed over the polysilicon layer using WF.sub.6 and SiH.sub.4 as the reaction gases. The silicide and polysilicon layers are patterned to form polycide gate electrodes. The substrate is annealed initially in an inert gas atmosphere to remove excess fluorine gas, then in an oxygen atmosphere. Lightly doped source and drain ion implants are performed. Spacers are formed on the sidewalls of the polycide gate electrodes. Source/drain ion implants are performed with include fluoride ions. The substrate is degassed in an inert atmosphere to remove the excess fluoride ions. A dielectric layer is deposited over the pattern of polycide gate electrodes and flowed. There is no excess fluorine gas concentration to form a bubble in the dielectric layer.

Abstract: An integrated circuit is fabricated on a semiconductor substrate and comprises an n channel type field effect transistor, a p channel type field effect transistor and an interconnection coupled between the drain regions of the two field effect transistors, and each of the gate electrodes and the interconnection is provided with a polycrystalline silicon and a refractory metal silicide deposited over the polycrystalline silicon, wherein side spacers are eliminated from the gate electrodes and the interconnection, because no short circuiting takes place between the gate electrodes and the source and drain regions by virtue of the deposition of the refractory metal silicide.

Abstract: A contact for a semiconductor device is provided by depositing a layer of palladium on a silicon substrate, causing the palladium to react with the substrate for forming palladium silicide, removing unreacted palladium from the substrate, forming doped silicon on the palladium silicide and substrate, causing the silicon to be transported through the palladium silicide for recrystallizing on the substrate for forming epitaxially recrystallized silicon regions on the substrate and lifting the palladium silicide above the epitaxially recrystallized silicon regions for forming a silicided contact therefor, and removing the doped silicon from the substrate.

Abstract: A workpiece is formed comprising a silicon substrate covered by four successive layers of silicon dioxide, undoped polysilicon, undoped WSi.sub.2 and a top layer of silicon dioxide on silicon nitride. The four layers are patterned to provide gate electrode structures each comprising the four layers. The workpiece is covered with a masking layer and the top layer of each structure is exposed through the masking layer. The top layers are then removed and ions of one conductivity type are implanted into the WSi.sub.2 layers of one group of gate electrode structures while another group of structures is masked, and ions of the other conductivity type are implanted into the WSi.sub.2 layers of the second group while the first group is masked. Thereafter, doped regions are formed in the substrate adjacent to the gate electrode structures.

Abstract: A method substantially eliminating consumption of silicon from semiconductor devices is provided. The method includes controlling gases within the environment wherein the semiconductor device is positioned. The environment is formed to include an inert gas and oxygen. The oxygen content is formed to have a concentration between approximately 1.times.10.sup.1 and 1.times.10.sup.5 parts per million. Such an oxygen concentration substantially prevents converting silicon from the semiconductor device into silicon monoxide thereby substantially eliminating silicon consumption.

Abstract: Low temperature silicon-on-insulator wafer bonding using a silicide bond formation reaction. Dielectric isolation with silicon dioxide, diamond, silicon nitride, and so forth yields buried resistors under trench isolated silicon islands. Buried dielectrics can be thermally susceptible films like diamond due to the low temperature of the bonding silicidation reaction. Bonding silicides also provide thermal dissipating layer between a buried diamond layer and a handle wafer for good overall thermal conductivity. Bonding silicides also act as diffusion barriers. The silicide bonding takes place in the presense of a liquid oxidizer such as aqueous solution of HNO.sub.3 and H.sub.2 O.sub.2.

Abstract: A method for forming a connection between two levels in a semiconductor structure includes first forming a VIA (14) through an insulating layer (12) to an underlying structure (10). Sidewall spacers (22) and (24) are formed on the vertical walls of the VIA (14). The spacers (22) and (24) have tapered surfaces. A barrier layer (30) is then formed over the bottom surface of the VIA followed by CVD deposition of a conductive layer (32) of WSi.sub.2 to provide a conformal conductive layer. An aluminum layer (38) is then deposited by physical vapor deposition techniques with the descending portions of layer (32) providing a conductive connection between the aluminum layer (38) and the lower structure (10) in the VIA (14).

Abstract: A method for fabricating titanium silicide contacts wherein prior to a Ti sputtering process, ions having a conductivity opposite to the conductivity of source and drain regions on each well are implanted in the source and drain regions by using the same mask as used in the Ti sputtering process, so as to form low concentration regions at contact surfaces and high concentration regions at regions beneath the contact surfaces.

Abstract: Selective salicidation of source/drain regions of a transistor is accomplished by performing an implant into a first plurality of transistor source/drain regions on an integrated circuit. As a result of the implant, doping density of the first plurality of transistor source/drain regions is greater than doping density of a second plurality of transistor source/drain regions on the integrated circuit. The integrated circuit is heated to a heating temperature sufficient to produce oxidation regions immediately over the first plurality of transistor source/drain regions and the second plurality of transistor source/drain regions. The heating temperature is chosen so that the oxidation regions immediately over the first plurality of transistor source/drain regions are thicker than the oxidation regions immediately over the second plurality of transistor source/drain regions.

Abstract: A method of forming a contact is disclosed. The method of the present invention includes the steps of: forming an insulating layer on a silicon compound; forming a contact hole in the insulating layer, the contact hole reaching the silicon compound; forming at least one layer of a refractory material film on an inner wall of the contact hole and on a surface of the insulating layer; forming a silicon containing tungsten layer on the refractory material film by CVD; and growing tungsten on the silicon containing tungsten layer by CVD, to fill the contact hole with the tungsten wherein the silicon containing tungsten layer contains silicon in the range of 0.6 wt. % to 20 wt. %.

Abstract: According to this invention, a method of manufacturing a semiconductor device includes the steps of forming an impurity diffusion layer of a second conductivity type on a semiconductor substrate of a first conductivity type, forming a transitition layer containing a constituent element of the semiconductor substrate on the impurity diffusion layer, and doping an impurity of the second conductivity type in the metal compound layer by annealing in a reducing atmosphere.

Abstract: A method of manufacturing a semiconductor device whereby a layer (12) containing Co or Ni is deposited on a surface (2) of a semiconductor body (1) bounded by silicon regions (3, 4, 5, 6) and regions of insulating material (8, 9), after which the semiconductor body (1) is heated during a heat treatment to a temperature at which the Co or Ni forms a metal silicide with the silicon (3, 4, 5, 6), but not with the insulating material (8, 9). On the surface (2) of the layer (12) containing the Co or Ni, according to the invention, a layer of an amorphous alloy of this metal with a metal from a group comprising Ti, Zr, Ta, Mo, Nb, Hf and W is deposited, while furthermore the temperature is so adjusted during the heat treatment that the layer (12) of the amorphous alloy remains amorphous during the heat treatment.

Abstract: A process for producing self-aligned titanium silicide. A silicon substrate is provided, silicon electrode and oxide insulator regions are formed on the substrate, and a titanium layer overlying the electrode and insulator regions is formed. The device is heated in an oxygen rich environment to form titanium silicide overlying the electrode regions and to form titanium oxide overlying the insulator regions and metal silicide.

Abstract: A method of providing a conformal layer of TiSi.sub.x atop a semiconductor wafer within a chemical vapor deposition reactor includes the following steps: a) positioning a wafer within the reactor; b) injecting selected quantities of gaseous Ti(NR.sub.2).sub.4 precursor, gaseous silane and a carrier gas to within the reactor, where R is selected from the group consisting of H and a carbon containing radical, the quantities of Ti(NR.sub.2).sub.4 precursor and silane being provided in a volumetric ratio of Ti(NR.sub.2).sub.4 to silane of from 1:300 to 1:10, the quantity of carrier gas being from about 50 sccm to about 2000 sccm and comprising at least one noble gas; and c) maintaining the reactor at a selected pressure and a selected temperature which are effective for reacting the precursor and silane to deposit a film on the wafer, the film comprising a mixture of TiSi.sub.x and TiN, the selected temperature being from about 100.degree. C. to about 500.degree. C.

Abstract: A LPCVD method for depositing a film of TiN on a semiconductor structure includes reacting an organometallic titanium source gas such as TMAT and organic silane as a reactive gas. The deposited film is a mixed phase of TiN and TiSi.sub.2 and is characterized by a low contact resistance, good step coverage and good barrier properties. The reaction is preferably carried out in a cold wall CVD reactor at relatively low temperatures (i.e. 200.degree. C.) and at pressures of from about 0.05 to 30 Torr.

Abstract: An epitaxial growth of a first component of a multilayer stack for use in optical, electro-optical and electronic or magnetic components, e.g. on a silicon wafer, can be formed by depositing a second component in a form in which that second component produces a precipitate or inclusions in the first component which with continued deposition may be partly replaced by a third component so that the precipitate itself is buried in a monocrystalline structure and, after a thermal treatment in which the precipitate coalesces, a buried layer is formed of the second component or a compound thereof with, say, the first component, in that monocrystalline structure.

Abstract: As a wiring for semiconductor devices, the wiring consisting of an Al-Si-Cu alloy film is excellent in the electromigration resistance but is inferior in the stressmigration resistance. In order to compensate this aspect a laminated film consisting of an Al-Si-Cu alloy film and a refractory metal silicide film began to be used as the wiring, but a wiring thus obtained has a weakness in that its electromigration resistance deteriorates. However, it is possible to suppress the deterioration in the electromigration resistance while maintaining the stressmigration resistance by adding Cu to the refractory metal silicide film. In particular, when the refractory metal silicide film is a tungsten silicide film, the concentration of Cu is preferable that it is in the range of 0.1 to 1.0 wt. %.

Abstract: A method of manufacturing a semiconductor device in which a thin buried silicide layer is formed by implantation includes the step of first forming an amorphous layer by implantation, which layer is then converted into the buried silicide layer by a heat treatment. A sufficiently thin buried silicide layer, of about 10 nm thickness, can be obtained in this manner, and the resulting structure is suitable, for example, for the manufacture of a metal-base transistor.

Abstract: The surface of a barrier layer interposed between a silicon substrate and aluminum wiring connected thereto is oxidized by heat treatment at 350.degree. to 450.degree. C. in an atmosphere having substantially the same composition as that of air or immersion in an oxidizing chemical to form an oxide film on the surface, and a wiring layer is then formed thereon. The presence of the oxide film inhibits interdiffusion between the silicon substrate and the aluminum wiring and reaction between the aluminum wiring and the barrier layer. Since this oxide film is formed by oxidation at the atmospheric pressure, the oxide film is not excessively oxidized even if it is exposed in air at a relatively high temperature of about 300.degree. C. The oxide film having a thickness and properties which produce the tunnel effect can be formed with good reproducibility.

Abstract: A semiconductor manufacturing process for depositing a tungsten silicide film on a substrate includes deposition of a tungsten silicide nucleation layer on the substrate using a (CVD) process with a silane source gas followed by deposition of the tungsten silicide film with a dichlorosilane source gas. This two step process allows dichlorosilane to be used as a silicon source gas for depositing a tungsten silicide film at a lower temperature than would otherwise by possible and without plasma enhancement. Tungsten silicide films deposited by this process are characterized by low impurities, good step coverage, and low stress with the silicon substrate.

Abstract: A method for formation of silicide structures on a semiconductor device. Oxide sidewalls are formed upon and selectively removed from polysilicon contacts. Refractory metal is deposited and heated, unreacted metal is removed, leaving a metal silicide on selected polysilicon sidewalls.

Abstract: A source/drain region of a MOS FET having a silicon substrate is covered with a metal silicide alloy layer. A silicon deposition layer is formed between the substrate and the silicide layer. The conductivity type of the deposition layer is different from that of the substrate, and the deposition layer per se functions as an impurity diffusion layer as the source/drain region or intervenes between the alloy layer and the impurity diffusion layer. The impurity diffusion layer, or the source/drain region, is formed in a shallow region in the substrate.

Abstract: A process for fabricating a semiconductor device including the steps of: depositing a tungsten silicide adhesive layer over a wafer having a SiO.sub.2 insulating layer with a contact hole defined therein; treating the wafer by a rapid thermal annealing technique to impart further adherence to the tungsten silicide adhesive layer; and depositing tungsten over the tungsten silicide adhesive layer by CVD process to form a tungsten plug layer for electrical contact and a tungsten wiring layer.

Abstract: A semiconductor device such as a solar cell, photodiode and solid state imaging device comprises a semiconductor layer made of amorphous silicon formed on a given substrate, and a transparent conductive layer formed by an interfacial reaction between the amorphous silicon and a metallic film directly formed on the amorphous silicon. This transparent conductive layer is used as a transparent electrode of the device and if necessary the remainder after having partially removed the metallic film for the transparent conductive layer is used as a conductive layer and light shielding film.

Abstract: A dry etching method for refractory metal or its compound uses a mixed gas of an etchant gas for etching said refractory metal and a deposit gas for depositing said refractory metal. Halide of the etched refractory metal is used as the deposit gas. By using such a mixed gas, the refractory metal is etched at a portion where ion assist is strong, while the refractory metal is deposited at a portion where the ion assist is weak. In the dry etching, the ion mostly hits the surface of the object facing against the anode and hence the ion assist is strong, while the ion assist is weak at the side wall. Accordingly, the refractory metal is etched at the bottom surface of an etched groove, but at the side wall of the groove the refractory metal is deposited. This deposited metal protects the side wall from side etching. Therefore a fine pattern having a high aspect ratio etching is achieved.

Abstract: A method is described for fabricating a lightly doped drain MOSFET integrated circuit device which overcomes the peeling problems of refractory metal silicide layers on a polycide gate. The process of this invention has been simplified by not using several of the high thermal cycle process steps believed to be necessary for successfully making a polycide gate lightly doped drain MOS FET integrated circuit. These steps are (1) the thermal oxidation after the polycide etching step, (2) the densification step after the blanket deposition of silicon dioxide layer for the spacer preparation, and (3) the silicon oxide capping of the refractory metal silicide layer after the spacer formation by anisotropically etching. The result is a process that provides a non-peeling polycide gate lightly doped drain MOS FET integrated circuit device.

Abstract: A method for fabricating a semiconductive device is described, wherein a semiconductive substrate having a thermally shrinkable, refractory metal silicide thin film is provided, on which an insulating film on the metal silicide thin film is formed. The metal silicide thin film is thermally treated in an atmosphere containing hydrogen. By this, no morphological degradation is observed in the silicide thin film without an increase of the resistance.

Abstract: An antireflection coating (21) for use in integrated circuit processing consists of a film of tungsten silicide (WSi.sub.0.45) or tungsten silicon nitride (WSiN). These coatings are preferably made by sputtering, with the tungsten silicon nitride coating being made by sputtering in a nitrogen-containing atmosphere.

Abstract: A process for forming tungsten or molybdenum silicide on silicon apparent regions (6) of a silicon wafer surface (1) also comprising oxidized regions (2) includes the steps consisting in uniformly coating the wafer with a tungsten or molybdenum layer (10) and annealing at a temperature ranging from 700.degree. C. to 1000.degree. C. The annealing step is carried out in presence of a low pressure gas forming a chemical composite with tungsten or molybdenum. The composite is then selectively etched.

Abstract: A method of forming low-resistive contact to at least two preohmic regions formed in a silicon substrate having a thick insulating layer thereon, including the steps of depositing a polysilicon on the insulating layer, performing an anisotropic etch for opening the preohmic regions, sputter-depositing a titanium deposit, the deposited titanium having electrical disconnections on the vertical side-walls of the opening regions, siliciding the titanium deposit, and depositing a metal silicide deposit for preventing electrical disconnections. Another embodiment uses a sputter-deposited titanium silicide deposit instead of titanium silicide. Still another embodiment includes the step of forming holes by an anisotropic etch, depositing polysilicon in the holes and on the insulating layer, sputter-depositing an titanium deposit, forming an titanium silicide deposit, and depositing a metal silicide deposit.

Abstract: A process for developing conductive interconnect regions between integrated circuit semiconductor devices formed on an insulating substrate utilizes the semiconductor material itself for formation of device interconnect regions.A patterned layer of semiconductor material is formed directly on the surface of an insulating substrate. The patterned layer includes regions where semiconductor devices are to be formed and regions which are to be used to interconnect terminals of predetermined ones of the semiconductor devices. After forming the semiconductor devices in selected regions of the semiconductor material, the regions of the semiconductor material patterned for becoming interconnects are converted to a metallic compound of the semiconductor material.

Abstract: A method for fabricating integrated circuits is used to improve contacts between polycrystalline interconnect and underlying polycrystalline or monocrystalline silicon regions. After contact openings are formed, a layer of titanium is deposited over the integrated circuit. The titanium is reacted in nitrogen to form a silicide layer only in the openings. Titanium nitride and unreacted titanium are then removed, and a layer of polycrystalline silicon deposited and patterned. The silicide layer between the polycrystalline interconnect and the underlying silicon ensures that a high quality contact is formed.