Abstract: A novel MOS transistor structure comprises electrodes of metallic silicide and especially tantalum silicide. In the case of the gate electrode, the silicide is directly in contact with an insulating thin-film layer. In the case of the drain and source electrodes, the silicide is directly in contact with the monocrystalline silicon. The method of fabrication is thus simplified while avoiding the use of polycrystalline silicon.

Abstract: A transition metal silicide film 3 is formed on a transparent substrate 1, and an oxidized transition metal silicide film 4 is formed on said transition metal silicide film 3. Dry etching can be easily applied to the transition metal silicide film 3 and the oxidized transition metal silicide film 4. Since the silicified metal films have good adhesion to the transparent substrate 1, the fine patterns can hardly be detached at the time of mask rinsing. In addition, the oxidized transition metal silicide film 4 has a low reflection factor, which prevents the lowering of the resolution.

Abstract: A low collector parasitic resistance in bipolar transistors may be achieved without the use of an epitaxial layer or a high energy implant. Essentially, the invention employs the use of trenches in an N.sup.- layer overlying a P.sup.- substrate to surround the transistor, forming an N.sup.+ region in the walls defining the trench and below the surface, extending the trench into the P.sup.- substrate, implanting the bottom of the trench with a P-type dopant and refilling the trench with insulating material.The process of the invention permits fabrication of complex bipolar integrated circuits having a very high performance, and is particularly adaptable to very small geometry devices of 1 .mu.m and lower.

Abstract: Described is a method for producing metal silicide/silicon heterostructures. The method comprises depositing a very thin Si "template" layer on a relatively cold (<200.degree. C.) silicide substrate, raising the substrate temperature into the approximate range 500.degree.-800.degree. C. and maintaining it there while depositing further Si onto the template. The resulting Si layer can be of high crystalline perfection. The silicide advantageously is CoSi.sub.2, Co.sub.x Ni.sub.1-x Si.sub.2, CoSi.sub.y Ge.sub.2-y, or NiSi.sub.2, with 0<x<1,1<y<2.

Abstract: A process for forming closely spaced silicon or silicon-silicide gate electrodes for an integrated circuit involving the successive deposition over the semiconductive substrate of layers of silicon oxide, polycrystalline silicon, a metal, for example, tantalum which can be converted to a silicide, an oxide layer and a masking layer. Then the masking layer is patterned by photolithography and the exposed oxide layer etched in a fashion to undercut the overlying masking layer to leave an overhang. Then the exposed metal layer is removed, and the metal forming a silicide redeposited through the opening in the masking layer on the central portion of the exposed polycrystalline corresponding to the opening. The metal is then converted to a silicide and the polycrystalline silicon free of the silicide is removed.

Abstract: A method of making an improved metal silicide fuse of controlled thickness for an integrated circuit structure is disclosed. The metal silicide fuse is formed by first forming a layer of known thickness of a metal capable of reacting with silicon to form a metal silicide. A layer of amorphous silicon is then formed over the metal and patterned to form the desired fuse dimensions prior to formation of the silicide. The structure is then sintered to form the metal silicide. Excess silicon remaining over the metal silicide fuse layer is then removed as is unreacted metal from areas where no silicon was present to react with the metal to form the silicide. Control of the thickness of the metal layer which subsequently reacts to form the silicide controls the thickness of the subsequently formed silicide layer to thereby form a fuse of reproducible thickness.

Abstract: An improved ECL bipolar memory cell is disclosed which comprises connecting the respective collectors of the memory transistors in the flip-flop circuit to bit lines using Schottky diodes to protect against latch-up of the ECL cell; and the inversion of the transistors in the circuits to provide a buried emitter construction for alpha strike protection. In a preferred embodiment, the Schottky diode and the load devices, such as resistors or load transistors used to coupled the cell to one of the word lines are made using polysilicon to facilitate construction of the cell, reduce the total number of contacts needed, and enhance the speed of the cell.

Abstract: A method of manufacturing a semiconductor device comprises a step of preparing a semiconductor substrate (12) having a surface layer of silicon, a step of forming a conductive thin film (14) of a silicide composed of a metal having a high melting point and silicon on the semiconductor substrate (12), a step of forming an oxidation-resistant mask (18) on a first portion (14a) of the conductive thin film (14) and a step of converting a second, exposed, portion (19) of the conductive thin film (14) into an insulating film (19a) of a composite oxide composed of silicon oxide and an oxide of the subject metal by oxidizing the exposed portion (19) while maintaining the first portion (14a) of the conductive thin film (14) covered by the mask (18).

Abstract: A method for making a MOS field effect transistor structure having tungsten silicide contact surfaces for the gate and source and drain regions is disclosed. Protective oxide is very precisely positioned so that a tungsten layer is formed on only selected silicon surfaces by selective deposition. Next, a layer of polysilicon is formed on said tungsten layer. The resulting structure is treated in an oxygen atmosphere to form the desired tungsten silicide. A silicon nitride cap can also be used to cover the gate portion during source and drain formation.

Abstract: There is disclosed a method of manufacturing a semiconductor device comprising the steps of forming a polysilicon film on a semiconductor substrate through an oxidation film, forming a mask of a predetermined pattern on the polysilicon film, forming a molybdenum film on the polysilicon film, and silicifying those regions of said molybdenum film not covered by the mask so that a structure of the uncovered molybdenum film regions and those regions of the polysilicon film located under the uncovered molybdenum regions have low resistance, while a region of the molybdenum film covered by the mask has high resistance.

Abstract: A method for constructing titanium silicide integrated circuit gate electrodes and interconnections is disclosed. The method finds particularly useful applications in metal-oxide semiconductor integrated circuit fabrication. Following standard active and passive circuit component construction, a thin film of titanium is overlayed on the die structure covering thereby the pre-patterned polysilicon gates and interconnections. The die is then rapidly heated and baked to form a silicide layer superposing said polysilicon. The undesired titanium layer over other areas can be stripped using simple ammonium hydroxide/hydrogen etching and cleaning solution. Titanium silicide electrodes and interconnections are self-aligned and have a sheet resistance of 1 to 5 ohms per square.

Abstract: A method for manufacturing a semiconductor device of the invention comprises the steps of(a) forming a gate insulating film on a surface of a silicon substrate, and a gate electrode on said gate insulating film;(b) forming a self-aligned insulating film at least on a side wall of said gate electrode;(c) forming a self-aligned metal or metal silicide film on a region on which an insulating film is not formed, said region including a source region, a drain region and a diffusion interconnection region which is an extended part of at least one of said source region and said drain region, or prospective regions for said source, drain and diffusion interconnection regions; and(d) forming said source region, said drain region and said diffusion interconnected region which is the extended part of at least one of said source region and said drain region, by doping at least one time said substrate with an impurity which has a conductivity type opposite to a conductivity type of said silicon substrate any time after st

Abstract: A Schottky barrier diode is made from a substrate of semiconductor material by forming, on a major surface of the wafer, a layer of dielectric material defining a restricted opening through which the semiconductor material is exposed. A metal which forms with the semiconductor material a single phase compound which is inherently stable at temperatures up to 600 deg. C. is deposited into the opening, into contact with the exposed semiconductor material. By heating the substrate and the metal deposited thereon, the metal reacts with the semiconductor material to form a body of the single phase compound. A layer of refractory metal which reacts with the dielectric material is deposited over the dielectric material and the body of single phase compound.

Abstract: A method of manufacturing a semiconductor device manufactures a semiconductor device provided with plural kinds of Schottky barrier diodes having different forward voltages on one substrate. The method includes (a) a step of forming at least one Schottky barrier diode of a first kind, and (b) a step of forming at least one Schottky barrier diode of a second kind. The step (a) is performed by placing a first metal layer at a first surface part of a silicon substrate, and then by silicifying the first metal layer. The step (b) is performed by plating, at a second surface part of the silicon substrate which is different from the first surface part of the silicon substrate, a second metal layer which consists of a metal different from the metal consisting of the first metal layer and then by silicifying the second metal layer.

Abstract: A process for selective formation of a titanium silicide, TiSi.sub.2, layer at high temperatures and low pressures via chemical vapor deposition during semiconductor device manufacturing. At 700.degree. to 1000.degree. C. and 0.5 to 1.5 torr, TiSi.sub.2 deposits only on exposed silicon or polysilicon surfaces and not at all on neighboring silicon dioxide. The process provides an excellent means of providing low resistivity interconnects without a mask step or subsequent annealing and removal of unreacted titanium.

Abstract: The invention concerns an integrated circuit the monocrystalline or polycrystalline silicon zones of which the source, gate and drain are covered with tantalum silicide TaSi.sub.2 while the remainder of the slice is covered with portions of a layer of tantalum oxide Ta.sub.2 O.sub.5, especially on the sides of the grids of polycrystalline silicon and on the thick oxide and an aluminum alloy layer comes into contact with the tantalum silicide to form connections with the portions of tantalum silicide.

Abstract: Metal contacts and interconnections for semiconductor integrated circuits are formed by a process using direct-reacted silicide to increase step or sidewall coverage. First a thin layer of titanium or other refractory metal is deposited, extending into a contact hole, then polysilicon is deposited and a preferential etch removes all of the polysilicon except on the vertical sides of steps or apertures. A second thin layer of titanium is deposited, then a heat treatment forms silicide to create conductive sidewalls or a plug. Metal contacts then engage the direct-reacted silicide rather than relying upon step coverage.

Abstract: An improved integrated circuit structure characterized by enhanced step coverage and a method of making it are disclosed. The structure comprises a base layer of silicon, a first oxide layer on the silicon layer, strips of poly silicon having selected portions thereof reacted with a metal capable of forming a metal silicide in situ on the surface of the poly silicon strips, a further oxide layer over the metal silicide, and a metal layer providing electrical contact to selected portions of the structure. The construction makes it possible to remove all of an intermediate oxide layer during manufacture except for an oxide layer above the poly load resistor. This elimination of one oxide layer, together with the integration of the conductive metal silicide and underlying poly silicon into one layer and the rounding of the metal silicide edge with oxide spacers via anisotropic etching of the intermediate oxide layer, permits better step coverage for the resulting structure.

Abstract: A CMOS static RAM, which has P channel transistors formed in a second polysilicon layer, N channel transistors formed in the substrate, and gates of both the N channel and P channel transistors formed in a first polysilicon layers, requires that ohmic contact be made between semiconductor material of differing conductivity type. The first polysilicon layer is N-type, and the second polysilicon layer is P-type. Ohmic contact therebetween is achieved by providing a silicide layer which is between these two layers and in physical contact with both. Ohmic contact between N-type regions in the substrate and the second polysilicon layer is similarly achieved by sandwiching silicide therebetween.

Abstract: An MOS device having a gate electrode and interconnect of titanium nitride and especially titanium nitride which is formed by low pressure chemical vapor deposition. In a more specific embodiment the titanium nitride gate electrode and interconnect have a silicon layer thereover to improve oxidation protection.

Abstract: A thin conducting line such as a gate pattern is defined on a semiconductor chip (10) by applying a narrow ion beam, suitably a focused-ion-beam (16) having a submicrometer thickness from a source (18) onto a thin layer (14) of an inorganic material such as silicon or aluminum overlying a layer (12) of refractory metal on a substrate (11). The ion beam is translated to form a gate pattern at a dose between about 0.1 to 50.times.10.sup.15 cm.sup.-2 and an energy from about 1 to 1000 KeV. Ions are implanted into the silicon and aluminum layers and into the underlying portions of the refractory metal layer and to render the exposed portions of the layers preferentially resistant to wet-etchant. The portions of layers which are not exposed nor protected by layers which are exposed, are preferentially removed to form a gate. Conventional MOSFET or MESFET processing to implant ions to form source and drain regions may then be performed.

Abstract: The present invention relates to a method of forming a diffused region with a shallow junction having a refractory metal silicide layer thereon. At first, the refractory metal silicide layer is selectively formed on a silicon substrate of one conductivity type. An insulating film is then formed at least on the refractory metal silicide layer, and a contact hole is opened on a part of the silicide layer. After necessary high temperature treatments have been conducted, a dopant impurity of the opposite conductivity type is introduced from the contact hole to the silicide layer. The impurity is laterally dispersed in the silicide layer and diffused into the whole portion of the silicon substrate in contact with the silicide layer, whereby the diffused region with a shallow junction can be formed.

Abstract: A method of forming a metallic silicide on silicon or polysilicon in which a masking layer such as silicon dioxide is formed on a silicon slice and patterned to expose selected areas of the slice surface. The slice is then sputter etched followed by in situ deposition of a metal layer. The slice is heated to convert the portion of the metal layer in contact with the silicon and/or polysilicon to a metal silicide, then the non-converted metal is removed by a selective etchant. According to another embodiment of the invention a titanium layer is deposited and reacted in an ambient including nitrogen to prevent the out-diffusion of silicon through the TiSi.sub.2 and titanium layers.