Abstract: A BiCMOS process where a base region is formed in a relatively highly doped n-type substrate region. Boron is implanted at two different energy levels to form the base region and a counter doped n region near the base collector junction to prevent impact ionization.

Abstract: A bipolar fabrication process, illustratively suited for integration into a conventional CMOS process to thereby form a BiCMOS integrated circuits is disclosed. The collector and base are formed through multiple implants and a single masking step to thereby provide a continuous low resistance collector region.

Abstract: Formed on a p-type semiconductor substrate are bipolar transistors and CMOS transistors. A bipolar transistor has a base extraction electrode a side-surface of which is covered with an oxide layer, a silicon nitride layer, and a polysilicon layer. A CMOS transistor has a gate electrode a side-surface of which is covered with an oxide layer, a silicon nitride layer, and a side-wall layer. The silicon nitride layer on the side-surface of the base extraction electrode is formed by the same fabrication step that the silicon nitride layer on the side-surface of the gate electrode is formed.

Abstract: In a method for manufacturing an LDD-structured MOS transistor and a bipolar transistor, a gate insulating layer is formed on a MOS transistor region and a bipolar transistor region. Then, a gate electrode is formed on the MOS transistor region. Then, an insulating layer is formed on the entire surface, and as etched back by a reactive ion etching process to form a sidewall spacer. The MOS transistor region and the bipolar transistor region are etched by a wet etching process using the gate electrode and its sidewall spacer as a mask.

Abstract: A method of manufacturing a semiconductor device made up of a Bi-CMOS integrated circuit with the performance of MOS and bipolar elements enhanced. A semiconductor substrate surface is selectively oxidized to divide surface into a bipolar element forming area and a MOS element forming area. Next, the entire substrate surface is oxidized to form an oxide film 9, after which high-density ions are implanted into a collector leading area. Then, driving-in of the collector leading area is performed by performing heat treatment in an oxidizing atmosphere while forming an oxide film 9b on the collector leading area and another oxide film 9a on the MOS element forming area. Subsequently, the oxide film is etched all over the semiconductor substrate surface by the thickness of the oxide film 9a to expose the semiconductor substrate surface of the MOS element forming area. Lastly, the substrate surface is entirely oxidized to form a gate insulation film thinner than the oxide film 9.

Abstract: An IC voltage clamp and a process for forming the voltage clamp. The voltage clamp includes an MGFO device having an n-type source region, an n-type drain region, and a p-type field implant diffusion between the source and drain regions. The voltage clamp further employs a parasitic NPN device having a collector region coincident with the MGFO drain region, an emitter region coincident with the MGFO source region, and a base region formed by the substrate. A metal gate electrode overlies and is insulated from the field implant diffusion, but electrically connects the source and emitter regions to ground. An input electrode contacts the drain region so as to electrically connect the drain and collector regions to the input voltage of an integrated circuit. The field implant diffusion and drain/collector regions are formed by overlapping their masks, such that a lower breakdown voltage is achieved between the NPN collector and the substrate and field implant diffusion (the NPN base).

Abstract: To enable a high speed operation and to increase the current gain, the disclosed a method of manufacturing a semiconductor device, comprising the steps of: forming a first semiconductor layer with a first-conductivity type in a semiconductor substrate; forming a second semiconductor layer with a second-conductivity type different from the first-conductivity type on the first semiconductor layer; insulation separating the formed second semiconductor layer into a first semiconductor region and a second semiconductor region by an insulating film; changing the second semiconductor region to the first-conductivity type; forming a pattern of an insulating film or a photoresist film having a hole at a partial area of the first semiconductor region of the semiconductor substrate; and implanting first-conductivity type impurities and second-conductivity type impurities at the first semiconductor region, respectively by use of the formed pattern as a mask, to form a first-conductivity type impurity region contacting wi

Abstract: In an NPN bipolar transistor having a special structure in which each impurity region is formed by ion implantation, a width of a base region is significantly reduced, and therefore, current amplification factor hfe is increased, resulting in improvement in performance thereof. Furthermore, a Bi-CMOS transistor can be manufactured using a CMOS process. The use of the bipolar transistor having a special structure for a driving circuit allows implementation of a driving circuit having large driving force with slight increase in cost.

Abstract: A method of manufacturing a semiconductor device with a bipolar transistor (1) and a MOS transistor (2) formed in a silicon body (3) which for this purpose is provided with a field insulation region (4) by which semiconductor regions (6, 7) adjoining a surface (5) of said body are mutually insulated. A first region (6) is to be used for the bipolar transistor and a second region for the MOS transistor. The two regions are provided in that order with a gate dielectric layer (10) and an auxiliary layer (11) of non-crystalline silicon. The auxiliary layer and the gate dielectric layer are subsequently removed from the first region. Then an electrode layer (13) of non-crystalline silicon is deposited. An emitter electrode (15) is formed in the electrode layer on the first region, and a gate electrode (16) is formed both in the electrode layer and in the auxiliary layer on the second region.

Abstract: A BiCMOS device and a manufacturing method thereof according to the present invention has a gate insulating layer of NMOSFET having non-uniform thickness. The thickness of the end portion of the gate insulating layer, which is near LDD regions, is thicker than that of center portion. Therefore, the GIDL and the gate-drain overlap capacitance is reduced. In addition, in case of the bipolar transistor of the BiCMOS device, there exists a portion of an oxide film below the side portion of the emitter polysilicon and over the side portions of the emitter region. Since this structure serves as a gate of field effect transistor, N- channel is produced in the emitter region when the emitter-base junction is reversely biased and thus the hot carrier reliability is improved.

Abstract: In a BiMOS semiconductor device, emitter and base electrodes formed by polycrystalline Si of a bipolar transistor are isolated from each other by way of a sidewall and an insulator layer. As this insulator layer acts as an offset during the formation of the sidewall, its layer thickness can be made larger. Further, as this insulator layer is not provided in a MOS region, its step can be made smaller. Consequently, parasitic capacitance can be reduced while the insulator layer can be made thicker. Thus, there can be achieved both fast operation and high reliability of the bipolar transistor and, moreover, reduction in the reliability of a MOS transistor can also be prevented.

Abstract: A bipolar transistor with a relatively deep emitter region is formed in a BICMOS device using the source/drain mask used to form the source and drain regions of MOSFETs of the device and the base region mask which would otherwise be required in any event to diffuse an emitter region of the bipolar transistor. The emitter is diffused or implanted to a depth greater than the depth to which a source and a drain region of the MOSFET are diffused. By using only the base region and source/drain region masks, and developing in sequence, each of two coatings of photoresist applied on top of one another, an access opening to the emitter region is define solely by the co-location of openings in each of the two coatings, thereby allowing the emitter region to be separately and additionally implanted. The access to the base region for the additional implication is achieved using only a few additional photo-ops and not as a result of using an additional emitter mask.

Abstract: Fabrication of a high frequency bipolar transistor structure is integrated into a CMOS process flow with minimal additional cost. The polysilicon emitter of the bipolar device and the polysilicon gate of the MOS device use separate polysilicon layers and, therefore, allow the bipolar emitter and the MOS gate to be doped independently of each other. The process scheme does not require the MOS device to be subdivided.

Abstract: A silicon oxide film and a polysilicon film are formed on a silicon substrate and are selectively etched to form a contact hole in a region where an emitter is to be formed. A polysilicon film is laid on the substrate and two polysilicon films are patterned to form an emitter electrode and a gate electrode made of the two polysilicon films which are doped with arsenic. The arsenic is diffused from the polysilicon films of the emitter electrode into the silicon substrate to form an N.sup.+ emitter layer which has a high concentration and is shallow. Consequently, the contamination of a gate insulator film can be prevented from occurring and a bipolar transistor having high performance, for example, a high current amplification factor or the like can be formed.

Abstract: A method of manufacturing both bipolar and CMOS devices including vertical PNP, NPN, PMOS and NMOS devices on the same chip, includes the steps of, simultaneously forming an N+ region (14) on part of a P base region (11) of the vertical NPN device to form the emitter contact region thereof, an N+ region (14) on a part of an N- epitaxial layer (5) of the vertical NPN device to form the collector contact region thereof, N+ regions (14) on first and second parts of a P well region (8) of the NMOS device to form the source and drain thereof, and an N+ region (14) on an N base region (9) of the vertical PNP device to form the base contact thereof.

Abstract: A method of manufacturing an integrated circuit having a buried layer of a low doped type of conductivity (2) and a buried layer of a highly doped type of the same conductivity (3) by masking a substrate (1) so as to define open areas on the substrate where it is desired to provide the two buried layers and doping the open areas of the substrate with a low concentration of dopants to form the low doped type of buried layer (2) is formed. Then one open area where the low doped type of buried layer (2) is formed is masked and the other open area is doped with a high concentration of dopants to form the highly doped type of buried layer (3).

Abstract: The present method for forming a BICMOS device includes the steps of defining first and second active regions for formation of bipolar and MOS transistors respectively. A gate oxide is provided over the second active region, and a polysilicon layer portion is provided over the gate oxide. A second, relatively thick polysilicon layer is provided over the resulting structure so as to overlie the first and second active regions, gate oxide and polysilicon layer portion. A portion of the thick polysilicon layer overlying the first active region is masked, and the unmasked portion of the thick polysilicon layer is etched to thin it. After removal of the masking, the processing steps to complete the bipolar transistor and MOS transistor are undertaken, the thinning of the unmasked portion of the thick polysilicon layer having been undertaken so that as appropriate etching in further processing takes place, gouging of the first active region during such further etching is avoided.

Abstract: In a method for manufacturing a "BiCMOS" semiconductor integrated circuit, a gate oxide film 110 and a polysilicon film are grown on a semiconductor substrate, and after phosphorus is doped, the polysilicon film is patterned to form gate electrodes 112a and 112b and an emitter electrode 112c. A heat treatment is performed to form an emitter diffused region 113. Phosphorus and boron are selectively implanted with a low impurity concentration, respectively, to form a LDD N.sup.- region 114 and a LDD P.sup.- region 115. Thereafter, a side wall 116 is formed, and boron is implanted into areas B and C so as to form P.sup.+ source/drain regions 117 and a graft base region 18, respectively. Phosphorus is implanted to form N.sup.+ source/drain regions 119.

Abstract: In a method of manufacturing a bipolar transistor, a collector region having a first portion and a second portion around the first portion is covered with an insulating film and a polysilicon layer is formed on the insulating film, the polysilicon layer having an opening. The insulating film is then selectively removed about an area that is larger than the area of the opening to thereby expose the first and second portions of the collector region and form a gap between a part of the polysilicon layer and the second portion of the collector region. The gap is then filled with a silicon layer and impurities are doped to form an intrinsic base region in the first portion, followed by forming a side wall space to make the opening smaller than the original area.

Abstract: A bipolar transistor (10) includes a collector region (13), a base region (14) in the collector region (13), and an emitter region (20) in the base region (14). A portion (18) of an electrical conductor (16) is located over a base width (23) of the bipolar transistor (10). The emitter region (20) is self-aligned to the portion (18) of the electrical conductor (16) and is preferably diffused into the base region (14) in order to decrease the base width (23) without relying on extremely precise alignment between base region (14) and the portion (18) of the electrical conductor (16). The portion (18) of the electrical conductor (16) is used to deplete a portion of the base width (23) of the bipolar transistor (10).

Abstract: Spacers are formed on the inside walls of a narrow silicon loss trench of a poly-emitter type bipolar transistor structure so that at most a narrow strip on the bottom of the trench receives high concentration doping when an extrinsic base region of the bipolar transistor is being doped. The narrowness of the exposed silicon surface which is etched to form the silicon loss trench slows vertical etching and thereby facilitates the formation of a shallow trench. The narrowness of the strip on the bottom of the trench which receives high concentration doping causes slow vertical diffusion of dopants. As a result, the highly doped link region which extends downward from the bottom of the trench does not extend downward much farther than the base region. A high cutoff frequency is therefore achievable by reducing the distance between the bottom of the base region and the top of the buried layer without decreasing the base-to-collector breakdown voltage.

Abstract: Methods of forming BiCMOS semiconductor devices include steps for forming bird's beak shaped oxide extensions between the gate electrodes and drain and source regions of CMOS devices to inhibit drain leakage currents and reduce gate-to-drain capacitance. These methods also include steps for forming bird's beak shaped oxide extensions at the emitter-base junctions of BJTs to reduce hot carrier induced P-N junction breakdown. A preferred method includes the steps of forming a gate electrode of a field effect transistor on a face of a semiconductor substrate and then forming self-aligned source and drain regions in the substrate using the gate electrode as a mask. A first conductive layer is then formed on the source and drain regions and used to diffuse dopants into the source and drain regions to increase the conductivity therein.

Abstract: A method for producing a semiconductor device which decrease the number of processes at the time of producing BiCMOSLSI than the usual. Impurities are introduced into a semiconductor substrate under a second insulating film and a first electric conductive film utilizing a first insulating film and the first conductive film formed on the semiconductor substrate as masks. Therefore, it is able to perform concurrent introduction of impurities into the gate electrode, the source and the drain of the MOSFET, the base electrode of the bipolar transistor, the emitter and the collector contact of the lateral bipolar transistor, the outlet electrode of the capacitor, and the resistor, so that the number of process steps can be reduced.

Abstract: A process has been developed in which narrow base width, lateral bipolar junction transistors, and short channel length MOSFET devices, can be simultaneously fabricated, in a silicon on insulator layer. The narrow base width is defined by the width of an insulator sidewall spacer, formed on the sides of a polysilicon gate structure. The narrow base width, resulting in increased transistor gain and switching speed, along with reductions in parasitic capacitances, due to placing devices in a silicon on insulator layer, result in enhanced device performance.

Abstract: In a method of fabricating a semiconductor device having a MISFET and/or bipolar transistor and/or a resistor formed with different surface portions of a single silicon semiconductor substrate in which a silicide layer is formed on each of source/drain regions of the MISFET and/or collector contact region and extrinsic base region of the bipolar transistor and/or contact regions of the resistor, the bipolar transistor has its emitter region formed by diffusing an impurity contained in doped polysilicon film serving as an emitter electrode of the bipolar transistor into a part of its base region. The resistor may have a resistive region formed in a surface portion of the substrate and may be covered with an insulating film and a doped polysilicon film thereon or may have a doped polysilicon film formed over a surface portion of the substrate as a resistor element.

Abstract: An npn bipolar transistor and a p-channel MOS transistor are formed on a p-type silicon substrate. The outer base electrode of the npn bipolar transistor and the gate electrode of the p-channel MOS transistor contain a p-type impurity and are composed of films consisting of the same material. The inner and outer bases are formed in a surface region of the p-type silicon substrate. The outer base is connected to the outer base electrode. The emitter electrode of the npn bipolar transistor is formed on the inner base. A laminated film constituted by a silicon oxide film and a silicon nitride film is formed on a p-type silicon substrate at a position between the outer base electrode and the emitter electrode.

Abstract: A process has been developed in which narrow base width, lateral bipolar junction transistors, and narrow channel length MOSFET devices, can be simultaneously fabricated, using a silicon on insulator approach. Insulator sidewall spacer and gate processing is used to produce narrow base widths for enhanced collector--base device characteristics, in terms of transistor gain, switching speeds and junction breakdowns.

Abstract: A method in accordance with one embodiment of the present invention may be used to self-align isolation regions, sinkers, and wells. In this improved method, P+ isolation regions, N+ sinkers, and P-wells are defined using the same masking step used to define the N-wells. The use of a single masking step to initially define the P+ isolation regions, N+ sinkers, N-wells, and P-wells results in the self-alignment of these regions. Several critical mask alignments are thereby eliminated, thus avoiding/simplifying fabrication steps, conserving die area, and allowing increased component density.

Abstract: A semiconductor BiCMOS device and method of manufacturing suitable for attaining high packing density and thereby speeding up a switching operation, wherein the device is formed to have one of a source region or a drain region of an MOS transistor be immediately adjacent a base region of a bipolar transistor so as to be electrically connected. In this manner, an electrical terminal is eliminated, thereby permitting a higher packing density.

Abstract: The present invention is mainly characterized in that a Bi-CMOS is obtained in which characteristics of a bipolar transistor are not deteriorated. The device includes a bipolar transistor and a CMOSFET formed on a semiconductor substrate separately from each other by a field oxide film. The thickness of a gate electrode of an NMOSFET and a gate electrode of a PMOSFET is made larger than the thickness of an emitter electrode of the bipolar transistor.

Abstract: A method of manufacturing a semiconductor device. A semiconductor substrate is prepared and a gate oxide film is formed on a surface of the semiconductor substrate. The gate oxide film is selectively removed to expose portions of the semiconductor substrate and a first polysilicon layer is formed on a resultant semiconductor structure. Impurities are implanted in the polysilicon layer and a resultant semiconductor structure is annealed to activate the impurities. The first polysilicon layer is patterned to form a base electrode of the bipolar transistor and a source drain electrode of the MOS transistor. An insulating layer is then formed on a resultant semiconductor structure. Portions of the semiconductor substrate are then selectively exposed and a second polysilicon layer is formed on a resultant semiconductor structure. The second polysilicon layer is then patterned to form an emitter electrode of the bipolar transistor.

Abstract: The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. For example, in one step, polysilicon gate electrodes for the FETs and polysilicon emitters for the BJTs are formed simultaneously. In another aspect of the invention, a polysilicon layer is used to reduce channeling which would otherwise occur during an implant step.

Abstract: A method of manufacturing a semiconductor device whereby on a surface (3) of a semiconductor body (1) a conductor track (21) of polycrystalline silicon insulated from the surface (3) is provided in a layer of doped polycrystalline silicon (11) provided on a layer of insulating material (10), and whereby a strip of polycrystalline silicon (19, 35) is formed between an edge (18) of the conductor (21) and a portion (24, 34) of the surface (3) adjoining the edge (18), after which a semiconductor zone (30) is formed through diffusion of dopant from the conductor (21) through the strip (19, 35) into the semiconductor body (1).

Abstract: A semiconductor device includes a plurality of semiconductor regions of a first conductive type and a plurality of semiconductor regions of a second conductive type. AMOS transistor having a channel of the second conductive type is formed in the semiconductor regions of the first conductive type, and a bipolar transistor and a MOS transistor having a channel of the first conductive type are formed in the semiconductor regions of the second conductive type.

Abstract: The present invention includes a BiMOS device having an MOS transistor that triggers a bipolar transistor, wherein the base and channel region are formed within a well region that electrically floats. The present invention also includes a BiMOS device having separate regions for the collector and drain regions and for the base and channel regions. The present invention further includes processes for forming the BiMOS devices. The BiMOS device may include a floating well region. The BiMOS device may include both low voltage MOS logic transistors and a high voltage or high power bipolar transistor. A low voltage or low power bipolar transistor may also be used. Separate drain, collector, base, and channel regions allow the bipolar transistor performance to be optimized independently of the MOS transistor, which may have its performance independently optimized, too. A plurality of MOS logic transistors, such as an AND or an OR gate may be used in the BiMOS device.

Abstract: In a bipolar or BiCMOS process, a heavily doped buried layer of a first conductivity type and a heavily doped channel stop region of a second conductivity type are formed in a lightly doped substrate of the second conductivity type. A lightly doped epitaxial layer of the first conductivity type is grown. An implant of the first conductivity type creates a guard ring around the bipolar transistor active region and also creates a higher-doped collector region inside the active region. In the BiCMOS process, during the formation of CMOS wells, a silicon nitride mask over the bipolar transistor inhibits oxidation of the epitaxial layer and the oxidation-enhanced diffusion of the buried layer. As a result, the epitaxial layer can be made thinner, reducing the collector resistance. The MOS transistor wells can be formed without an underlying buried layer, simplifying the process and decoupling the bipolar and MOS transistor characteristics from each other.

Abstract: A lateral bipolar transistor and method of making the transistor are disclosed. The device is made by etching a trench around a central region of a semiconductor body. An emitter is buried beneath the surface of this central area and contact to it is made via a self-alignment technique. The collector region of the transistor is contacted through the floor of the trench while the base region of the transistor is contacted in a region that surrounds the trench. The described method is compatible with the simultaneous manufacture of FET devices on the same chip.

Abstract: A merged BiCMOS device 10 having a bipolar transistor 60 and a PMOS transistor 64 formed in the same well region 18. Bipolar transistor 60 is comprised of an emitter electrode 30, base region 26, and collector region formed by well region 18. Emitter electrode 30 is separated from base region 26 by thick oxide 24. Tungsten-silicide layer 32 covers emitter electrode 30. PMOS transistor 64 comprises source/drain regions 52 and 52a, gate electrode 40, and gate oxide 36. PMOS transistor 64 may optionally comprise LDD regions 44. Source/drain region 52a is in contact with base region 26. If desired, the emitter electrode 30 and gate electrode 40 may be silicided.

Abstract: A truly complementary bipolar transistor structure and a combined bipolar and CMOS transistor structure are disclosed, each including a silicide layer formed upon a substrate that acts as an extrinsic base and gate. Optionally, a layer of polysilicon can be formed between the silicide layer and the substrate. An oxide layer (LTO) is formed or deposited over the silicide layer by chemical vapor deposition (CVD). Selected regions are defined and etched using a photoresist layer. Subsequent steps of implanting, etching and metalization are performed to produce transistors with reduced gate and extrinsic base resistances. Polysilicon may be used, instead of metal, as a contact in one embodiment of the invention.

Abstract: A bipolar transistor (408) is formed at a face of a semiconductor layer (152) of a first conductivity type. A first tank region (410) is formed in the semiconductor layer to be of a second conductivity type. A second tank region (412) is formed in the self-conductor layer to be of the first conductivity type and to be formed within the first tank region (410). At least one moat insulator region (210) is selectively grown on the face, with first, second, third, and fourth portions thereof being spaced apart. The first and second portions of the moat insulator region (210) self-align the implantation of a collector contact region. The second and third portions of the moat insulator region (210) self-align the implantation of an emitter. The third and fourth portions of the moat insulator region (210) self-align the implantation of a base contact region.

Abstract: In a BiCMOS process, a gate oxide is grown over the MOS transistors and over the base regions of the bipolar transistors. The base is implanted through the gate oxide and, in some embodiments, through a thin polysilicon layer overlying the base oxide. Then an opening is etched over the base regions in the thin polysilicon layer and the gate oxide, another polysilicon layer is deposited, and the two polysilicon layers are patterned to provide emitter contact regions and gate regions. The polysilicon etch terminates on the gate oxide. After an LDD implant or implants, an insulating layer is deposited and etched anisotropically to create spacers on the sidewalls of the emitter contact regions and the gate regions. During the etch, the gate oxide is etched away around the spacers to expose the extrinsic base regions and the source and drain regions.

Abstract: A complementary bipolar CMOS fabrication method uses a common deposition for both the CMOS gate contacts, and as a sacrificial layer for patterning bipolar devices. The deposition is removed from the bipolar devices and, after implanting base and emitter regions, is replaced with a separate emitter contact. Prior to its removal the sacrificial layer is coated with an oxidation resistant layer that imparts a desirable rounded shape to the edge of a thermal oxide layer that is grown around the bipolar emitter area. Common mask and implant steps are also used to fabricate lightly doped CMOS drains together with bipolar base-link regions, and CMOS source/drain regions together with bipolar external base regions. The fabrication technique also facilitates the fabrication of capacitors with no additional steps required, and includes an improved NiCr resistor contact method.

Abstract: An insulated-gate field-effect transistor (426, 452) has reduced gate oxide stress. According to one embodiment, the control gate (458) has a doped region (460) adjacent the source end of the transistor (452), and an undoped dielectric portion (462) adjacent the gate end. According to another embodiment, the drain end of the conductive gate (434) is disposed on top of a thick insulator region (432) that also acts to mitigate the high electric fields present when the transistor is subjected to a high voltage transient.

Abstract: A varactor (10, 115, 122) is formed using a BICMOS process flow. An N well (28) of a varactor region (13) is formed in an epitaxial layer (22) by doping the epitaxial layer (22) with an N type dopant. A cathode region (55, 132) is formed in the N well (28) by further doping the N well (28) with the N type dopant. Cathode electrodes (91, 114) are formed by patterning a layer of polysilicon (62, 86) over the epitaxial layer (22). Subsequently, the cathode electrodes (91, 114) are doped with an N type dopant. A region adjacent the cathode region (55, 132) is doped to form a lightly doped region (103, 117). The lightly doped region (103, 117) is doped with a P type dopant to form an anode region (109, 119).

Abstract: A semiconductor device in which a bipolar transistor is provided, such as a BiCMOS, and a production process thereof. The device has collector region of a first conductivity type; an intrinsic base region of a second conductivity type provided on the collector region; a graft base provided on the periphery of this intrinsic base region; and an emitter region of the first conductivity type provided by self-alignment with respect to the intrinsic base. A base electrode is provided in the upper portion where the graft base is scheduled to be formed. A trench is provided by self-alignment along the end portion on the outer circumference side of this base electrode. The graft base is provided in contact with the inner circumference of this trench.

Abstract: A semiconductor device and method to reduce the size of bipolar transistors and decrease the number of steps required to fabricate the bipolar transistor by using a unitary contiguous oxide sidewall to separate a collector contact from the base, emitter and emitter contact. The device and method may also be used during the fabrication of BiCMOS devices.

Abstract: Generally, and in one form of the invention, an integrated circuit comprising a bipolar transistor and a field effect transistor, wherein a channel of the field effect transistor and a base of the bipolar transistor are formed from a base epitaxial layer 16, and whereby field effect and bipolar transistors are formed within a common material structure is disclosed. In another form of the invention, an integrated circuit comprising a substrate 10, an epitaxial subcollector layer 12, an epitaxial collector layer 14, an epitaxial base layer 16, an epitaxial emitter layer 18, a bipolar transistor formed with an emitter electrical contact 20, 28, 35 to the emitter layer 18, a base contact 34 to the base layer 16, and a collector contact 42 to the subcollector layer 12, and a field effect transistor formed with a first gate contact 20, 30, 39 to the emitter layer 18, a first source contact 36 to the base layer 16, and a first drain contact 37 to the base layer 16, is disclosed.

Abstract: In a bipolar transistor, the collector and the base are formed in an isolation region laterally bounded by a field insulator. The isolation region corners are spaced far from the emitter to reduce the collector-emitter leakage current. The base does not extend laterally throughout the isolation region. Thus the base is small and the collector-base capacitance is small as a result. Those corners of the isolation region that are not covered by a base contact region are covered and contacted by an insulator. This insulator prevents the field insulator from being pulled back during wafer clean steps. Consequently, the field insulator does not expose the collector. Further, the insulator covering the corners prevents the metal silicide on the surface of the extrinsic base from contacting the corners. The insulator overlying the corners thus reduces the collector-base leakage current.

Abstract: A pnp device in a BiCMOS structure (1). PNP transistors (4) are fabricated without the need for additional process steps on the same substrate as npn (2), PMOS (8), and NMOS (6) devices. The process not only requires a minimum number of additional process steps, but results in devices with near optimum device characteristics.

Abstract: A process is disclosed which simultaneously forms high quality complementary bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.