Abstract: This is a method for fabricating integrated heterojunction bipolar transistors (HBTs) and heterojunction field effect transistors (HFETs) on a substrate. The method comprises: forming a subcollector layer 12 over the substrate 10; forming a collector layer 14 over the subcollector layer; forming a base layer 16 over the collector layer; etching the base layer to form one or more base pedestals 16 over a portion of the collector layer; forming a buffer region 18 in a portion of the collector layer over which one or more HFETs are fabricated; forming one or more channel regions 20,22 over the buffer region; forming a wide bandgap material emitter/gate layer 26 over the base pedestal and the channel region; forming isolation regions 30,32, whereby there is one or more separate HBTs and one or more separate HFETs over the substrate utilizing an epitaxially grown emitter/gate layer to form both an HBT emitter and an HFET gate. Other devices and methods are also disclosed.

Abstract: Disclosed is a scaled, self aligned, bipolar transistor and a method of fabrication which is compatible with MOSFET device structures. A transistor intrinsic base region is formed in the face of an isolated epitaxial region and polysilicon is deposited, patterned and etched to form emitter regions. An oxide cap and first sidewall oxide spacers are formed on the polysilicon emitters and the single crystal silicon is etched using the oxide covered emitters as a mask to form recessed regions in the epitaxial layer. The extrinsic base region is then formed adjacent at least one side of the base by implanting appropriate dopants into one of the recessed regions. A second sidewall oxide spacer is then formed on the vertical base emitter structure and a heavily doped collector contact region is formed by implanting appropriate dopants into another one of the recessed silicon regions.

Abstract: In a semiconductor IC, a vertical pnp or npn transistor of a uniform characteristic and a high breakdown voltage is made by forming, for example, a p.sup.- -collector region (39) in an n-type epitaxial region, an n-well base region (41) formed in the p.sup.- -collector region (39) and a p-emitter region (42) formed in the n-well base region (41); and furthermore, for example as shown in FIG. 9, p.sup.- -regions (40) and (49) are formed simultaneously with the p.sup.- -collector region (39) and an n-region (53) is formed simultaneously with the n-well base region (41), thereby constituting IIL of superior characteristics and a high resistance device at the same time as forming of the vertical transistor without substantial increase of manufacturing steps; and in the similar way, by combining the p.sup.- -region and n-region formed in the above-mentioned simultaneous steps with other region formed simultaneously with the forming of the vertical transistor, high h.sub.

Abstract: A Bi-MOS semiconductor device of a type having a bipolar device and a plurality of MOS devices formed on a principal surface of a semiconductor substrate and a method of producing the same. The device includes a plurality of element isolation regions each thereof being composed of a first semiconductor region formed in the semiconductor substrate and having the same type of conductivity as the semiconductor substrate, and a thick insulation layer formed on the first semiconductor region, and at least one of an emitter electrode and a collector electrode formed in the bipolar device, gate electrodes formed in the MOS devices, a low-resistivity polycrystalline layer formed by a buried contact from one of the MOS devices and a high-resistivity portion formed by a high resistivity polycrystalline silicon layer connected to the low-resistivity polycrystalline silicon layer are formed from a polycrystalline silicon layer formed by the same layer formation.

Abstract: A method for forming a BICMOS device having MOS devices and bipolar devices formed during the same process includes the steps of first forming bipolar and MOS regions and then patterning gate electrodes in the MOS regions to define source/drain regions on either side thereof. A layer of oxide is formed over the bipolar transistor region which has an intrinsic base defined therein. The oxide is patterned to form an opening for an emitter and an opening for an extrinsic base, the opening separated by a layer of oxide. The refractory metal is then sputtered over the substrate and a silicide layer forms in the emitter and base regions of the bipolar transistor and the source/drain regions of the MOS transistors.

Abstract: The invention provides a bipolar transistor structure on a buried oxide layer for use in an integrated circuit and a method for fabricating the same. The invention may be incorporated into a method for fabricating bipolar transistors in a BiCMOS structure. The bipolar transistor is constructed in two stacked epitaxial layers. The first epitaxial layer is used to form both the MOSFET and the buried collector of the bipolar transistor. The second epitaxial layer is grown as a blanket epitaxial layer. The intrinsic collector and the base of the bipolar transistor are formed in the second epitaxial layer. An oxide layer is formed over the base. The emitter is formed of a polysilicon layer which is deposited through an opening in the oxide layer such that the polysilicon layer contacts the second epitaxial layer.

Abstract: A semiconductor device such as a Bi-CMOS having vertical or lateral bipolar transistors and MOS transistors is disclosed. The MOS transistors include a gate electrode made of a first conductive thin film, and sidewall spacers formed on the sides of the gate electrode and consisting of at least one deposition film. The vertical bipolar transistors include an emitter electrode made of a second conductive thin film, and an emitter diffusion window formed in the deposition film which is disposed under the emitter electrode. The lateral bipolar transistors include a base width defining region for defining the base width, and an insulation film formed between the base width defining region and the collector and emitter, and consisting of the deposition film.

Abstract: A method for fabricating a BIMOS device includes steps of forming a first insulator layer on the semiconductor layer in correspondence to a first region, providing a gate electrode of a metal-insulator-semiconductor transistor on the first insulator layer, and providing a base electrode of a bipolar transistor on a second region of the semiconductor layer. The method also includes introducing impurities into the semiconductor layer in the first region using the gate electrode as a mask to form self-aligned source and drain regions, introducing impurities into the base electrode and causing a diffusion of the impurities into the semiconductor layer to form a base region in the second region. Also included are steps of providing a second insulator layer so as to cover the first region and the second region, providing an insulator material on the second insulator in the form of liquid and curing subsequently to form a third insulator layer on the second insulator layer with a planarized top surface.

Abstract: A method of forming self-aligned transistors wherein both bipolar and field effect transistors are formed in the same Integrated Circuit simultaneously is described. A heavily doped conductive layer of one conductivity type is formed upon a monocrystalline semiconductor substrate of the opposite conductivity type to that of the one type. The conductive layer may be typically polycrystalline silicon. An insulator layer is formed upon the surface of the conductive layer. Openings with substantially vertical sidewalls are formed through the conductive layer to the semiconductor substrate in the locations of the first element, the emitter for the bipolar and gate for the MOSFET, of the transistors to be formed. The structure is heated to form the heavily doped portions of the second element of said transistors of the one conductivity type by outdiffusing from the conductive layer.

Abstract: A method of forming a semiconductor device on a body of semiconductor material having a first doped region of a first conductivity type, comprising the steps of: forming a stud over the first doped region; using the stud as a mask to form a second doped region of a second conductivity type in the surface of the first doped region adjoining the stud; forming a sidewall of insulating material on the stud; forming a first device contact within the sidewall; and forming a second device contact over the second doped region adjoining the sidewall, such that the first and second electrical contacts are separated by the sidewall.In accordance with an embodiment of the present invention, the step of forming the second device contact includes the steps of forming a layer of conductive material generally conformally over the first doped region and the stud, and then planarizing the layer of conductive material to a height equal to or less than that of the sidewalls.

Abstract: A BiCMOS process which provides both isolated and vertical NPN and PNP transistors with better performance characteristics and fewer additional steps than the prior art. The additional steps consist of masked implants with no changes in the thermal steps of the CMOS process. An N-well to contain the vertical PNP transistor is formed during the same step that the NPN vertical transistor collector is formed. The N base of the PNP transistor is formed by implanting an N type material. A P type material is implanted at a high energy of at least 300 keV (150 for doubly ionized Boron) to form a collector of the PNP transistor. A P region is then formed as an emitter of PNP transistor. The high energy P implant gives a peak at approximately 0.8 .mu.m below the surface to form the equivalent of a buried layer (without growing an epitaxial layer after a P implant to form a buried layer as in the prior art).

Abstract: A process for fabricating semiconductor devices is disclosed which utilizes a selective deposition process to reduce the total number of process steps and especially the total number of photolithography steps required. In accordance with one embodiment of the invention a semiconductor substrate is provided having an insulating layer, a nucleating layer, and a second insulating layer overlaying the substrate. A photoresist mask is used an implant mask and as an etch mask to expose a portion of nucleating layer. A second implant mask is formed by the selective deposition of tungsten or other material on the exposed nucleating layer. The selectively deposited material is then used a mask for a second implantation.

Abstract: In a transistor fabrication process, the use of a three-step base doping technique enables the characteristics of a vertical bipolar transistor to be controllably reproduced at highly optimal values from run to run. Insulating spacers (52A) are employed in forming a self-aligned base contact zone (58B). A shallow emitter (46) is created by outdiffusion from a patterned non-monocrystalline semiconductor layer (38A) that serves as the emitter contact. The fabrication process is compatible with the largely simultaneous manufacture of an insulated-gate field-effect transistor of the lightly doped drain type.

Abstract: The manufacture of an integrated circuit including an isolated vertical PNP, an isolated vertical NPN and isolated CMOS transistors is described. The PNP transistor has a shallow densely doped emitter made simultaneously with the source and drain of the PMOS transistor. The PNP base is made simultaneously with lightly doped portions of the LDD source and drain of the NMOS transistor. The PNP collector is made simultaneously with the P-well in which the NMOS transistor is formed. A P-buried layer in the isolated vertical PNP transistor provides a low collector resistance and is formed simultaneously with the P-buried layer of the NMOS transistor that extends the P-well there and better isolates the NMOS transistor from the substrate. And the N-buried layer providing superior isolation of the PNP with respect to the substrate is formed simultaneously with the N-buried layer of the vertical NPN transistor. All four of these transistors provide and are well suited for use in analog signal handling circuits.

Abstract: An epitaxial layer (2a) is grown on a substructure (1) of semiconductor material, an area (7a) on said layer being doped negatively (n). A thick oxide layer (16) is grown around an area which is the active area of a bipolar transistor (BIP) and field effect transistor (FET). The active area is oxidized to an oxide layer (19) which is coated with a polycrystalline silicon layer (20a). A weak positive doping, so-called LDD doping, is carried out in an area (P) between this silicon layer (20a) and the silicon dioxide layer (16). A heavily negative doping (n+) is carried out on one side of the polycrystalline layer (20a) for constituting emitter (E) of the bipolar transistor (BIP). Its collector consists of the doped epitaxial layer (7a) which is connected to a polycrystalline layer (20c) on the silicon dioxide layer (16).

Abstract: A method of making bipolar and MOS devices simultaneously using a single fabrication process. In one embodiment of the invention, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide, having a thickness in the range of from approximately 150 angstroms to 300 angstroms, is thermally grown on the silicon substrate. A thin layer of polycrystalline silicon, having a thickness in the range of from approximately 500 angstroms to 1000 angstroms is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing. Both the thin polysilicon layer and the gate oxide layer are removed from the bipolar region where the emitter is to be formed. To maintain the integrity of the gate oxide layer during etching, a photoresist mask used during the polysilicon etch is retained during the gate oxide etch, and the gate oxide is etched in a buffered oxide solution.

Abstract: A process is disclosed for fabricating bipolar transistors having self aligned and closely spaced polycrystalline silicon base and emitter electrodes. The process is especially amenable to integration with the fabrication of MOS transistors to form BiMOS integrated circuits. In accordance with one embodiment of the invention, a P type polycrystalline silicon layer is deposited overlying an N type silicon substrate. The polycrystalline silicon layer is patterned to form base contact electrodes and to leave exposed a portion of the surface of the N-type substrate. An electrically insulating layer is formed overlying the polycrystalline silicon base contacts and the exposed silicon substrate. Sidewall spacers are formed on the electrically insulating layer at the sidewalls of the base contact electrode.

Abstract: A process for fabricating integrated circuits containing bipolar transistors in semiconductor wafers comprising the following steps:forming a well and an upper insulating layer on a semiconductor wafer;selectively patterning and doping a bipolar transistor base implant region into the well;selectively patterning a layer of conductive material atop the insulating layer, the conductive material layer selectively exposing a first area of the base implant region and covering other areas of the base implant region, the conductive material layer having at least one first edge which at least in part defines the exposed first area;doping through the exposed first area to form an emitter implant region within the base implant region, the conductive material layer masking without photoresist the other covered areas of the base implant region during doping of the exposed first area; then patterning the layer of conductive material to expose a second area of the base implant region and to form gates of MOS transistors el

Abstract: With a trend toward higher operation speed and higher gain of a Bi-MIS semiconductor device, wherein a bipolar transistor and a MIS FET are formed on the same silicon substrate, a wide bandgap material such as silicon carbide or micro-crystalline silicon is utilized as an emitter material of the bipolar transistor and further a gate electrode of the MIS FET is simultaneously formed using the same wide bandgap material. By applying the above method in the manufacturing of the Bi-MIS semiconductor device, a high amplification factor of the bipolar transistor and a high cutoff frequency of the MIS FET thereof can be easily obtained without additional processes.

Abstract: A method with less processing steps for making a BiCMOS semiconductor device which can be used both in high-integration, high-speed digital devices and in precise analog devices by forming within a single substrate a CMOS transistor, a metal contact emitter bipolymer transistor having the high load driving power and highly effective matching characteristics, and a polycrystalline silicon emitter bipolar transistor having a high-speed characteristic at a low current level. Said device includes a first and a second MOSFET, and a first and a second bipolar transistor on a first conductivity-type silicon substrate, wherein performing a second conductivity-type of ion-implantation for producing a first substrate region to thereon form the first MOSFET, and a third and a fourth substrate region to thereon form the first and second bipolar transistors, respectively on said substrate. The second MOSFET is subsequently formed in a second substrate region being located between the first and third substrate regions.

Abstract: A compressed vertical bipolar transistor configuration that eliminates one side of the standard symmetrical base contact, while also eliminating the requirement for a collector contact reach-thru. The bipolar transistor comprises: a collector layer; a base layer disposed over the collector layer; an emitter layer disposed over the base layer; a first sidewall insulating layer disposeed adjacent to and in contact with one side of the emitter layer, the base layer, and at least a portion of the collector layer; a second sidewall insulating layer disposed adjacent to and in contact with another side of the emitter layer and at least a portion of the base layer; and a base contact extension layer formed from heavily doped semiconductor material of the same conductivity type as the base layer, said base contact extension layer being in contact with and extending laterally from another side of the base layer.

Abstract: A Bi-CMOS device comprises a first insulating layer formed on a principal surface of a semiconductor substrate to extend outwardly from an edge portion of a base region of a bipolar transistor and from an edge portion of each source/drain region of each MOS transistor. A first polycrystalline semiconductor layer is formed on and in contact with a surface area of the base region of the bipolar transistor and a surface area of each source/drain region of each MOS transistor so as to extend on the first insulating layer. A second insulating layer is formed to cover the first polycrystalline semiconductor layer, a base-emitter junction exposed at the principal surface of the substrate and a portion of each of the base region and the emitter region adjacent to the exposed base-emitter junction. The second insulating layer also covers an inside edge of each source/drain region of the MOS transistors, and portions of each source/drain region and a channel region adjacent to the inside edge.

Abstract: The invention relates to a pnp lateral transistor comprised of two regions of p-type conductivity which are incorporated into the surface of a semiconductor area of n-type conductivity and constitute the emitter and collector regions. The portion of the semiconductor area of n-type conductivity located between these two regions constitutes the active base region. The invention is based on the fact that the active base region includes below the semiconductor surface and adjacent to the emitter region and to the collector region; a buried semiconductor region containing additionally counter-doping impurities relative to the remaining surrounding base region area, which buried region produces a conductive channel for the minority charge carriers in the base region. This substantially reduces the parasitic surface recombination and substrate transistor influences, and achieves a very high direct current gain in the lateral transistor.

Abstract: This invention provides a method for fabricating a semiconductor device comprising the steps of forming buried layers on the silicon substrate; etching an epitaxial layer after said layer is grown up, the step further including the processes of etching selectively the silicon epitaxial layer of well region on which a high speed bipolar transistor is formed to be thin and keeping the silicon epitaxial layer of well region on which nMOS transistor is formed remained the same thickness as grown up; and forming a pMOS transistor, a nMOS transistor and a bipolar transistor. High efficiency and high integration is easily attained in fabricating the high speed bipolar transistor and high performance CMOS transistor on same chip and by reducing the difficulty in processing according to the method of present invention.

Abstract: A mixed bipolar-CMOS self-aligned process and integrated circuit provide a high performance NPN bipolar transistor in parallel to fabrication of a PMOSFET and an NMOSFET. Gate and base contacts are formed in a first polysilicon layer. The base contacts are implanted with P+ ion concentrations for diffusing base contact regions of the substrate in a later drive-in step. Source and drain contacts and emitter contacts are formed in a second polysilicon layer. The source and drain contacts are formed as a unit and then separated into discrete contacts by a spin-on polymer planarization and etch-back procedure. Lightly-doped lateral margins of the source, drain and base regions are ion-implanted in an initial low concentration (e.g. about 10.sup.13 atoms/cm.sup.2). The gate and base contact structures serve as a mask to self-align the implants. Then, the gate and base structures are enclosed in an oxide box having sidewalls.

Abstract: Integrated semiconductor circuits with at least one bipolar transistor (17) and at least one MOS field effect transistor (18) on a chip wherein contacts from a metal interconnect level to diffused active emitter (8) and collector (5) regions of the bipolar transistor (17) as well as the gate electrode (9) of the MOS transistor are composed of a high melting point silicide, such as tantalum, tungsten, molybenum or titanium silicide, are disclosed, along with a method of producing such circuits. In addtion to achieving independence from a metallization grid and achieving low-resistance wiring, the use of the silicide, in conjunction with the high temperature stability of silicides, enables its simultaneous use as an implantation mask. The invention allows the production of bipolar/MOS components on a chip without added outlay.

Abstract: An integrated circuit containing bipolar and complementary MOS transistors wherein the emitter terminals of the bipolar transistors as well as the gate electrodes of the MOS transistors are composed of the same material, consisting of a metal silicide or of a double layer containing a metal silicide and a polysilicon layer. The emitter base terminals are arranged in self-adjusting fashion relative to one another and the collector is formed as a buried zone. The collector terminal is annularly disposed about the transistor. As a result of the alignment in dependent spacing between the emitter and the base contact, the base series resistance is kept low and a reduction of the space requirement is achieved. The doping of the bipolar emitter and of the n-channel source/drain occurs independently.

Abstract: A means and method for forming improved merged complementary bipolar, complementary MOS (CBICMOS) structures is described. The N-channel and N-base devices are grouped in a first isolated semiconductor region and the P-channel and P-base devices are grouped in a second isolated semiconductor region. The two regions are separated by lateral isolation. By sharing internal device regions and arranging the internal device regions in the proper sequence a particularly compact structure is obtained which may be wired to implement a variety of CBICMOS circuits using a single wiring layer. Both CMOS and vertical NPN and PNP bipolar devices are produced in a common substrate by a common process.

Abstract: This invention provides a method for fabricating a BiCMOS device, in which said device has a Si substrate of a first conductivity in which there is formed a first substrate region of a second conductivity for a bipolar transistor, a second substrate region of said second conductivity for a first MOSFET, having a source and drain of the first conductivity, and in which a part of said Si substrate is formed to provide a second MOSFET which has a source and drain of the second conductivity. A first nitride layer is used to prevent the substrate under a masking layer from oxidizing during the following oxidation processes, wherein the masking layer is composed of a oxide layer and the nitride layer. After some processes, the masking layer is removed. Implanting As impurities, a new oxide layer and a new nitride layer are deposited, wherein the role of the nitride layer is to protect a shallow emitter region.

Abstract: A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks.

Abstract: A method for forming a BICMOS device having MOS devices and bipolar devices formed during the same process includes the steps of first forming bipolar and MOS regions and then patterning gate electrodes in the MOS regions to define source/drain regions on either side thereof. A layer of oxide is formed over the bipolar transistor region which has an intrinsic base defined therein. The oxide is patterned to form an opening for an emitter and an opening for an extrinsic base, the opening separated by a layer of oxide. The refractory metal is then sputtered over the substrate and a silicide layer forms in the emitter and base regions of the bipolar transistor and the source/drain regions of the MOS transistors.

Abstract: An improved integrated circuit structure is disclosed comprising bipolar and MOS devices formed on the same substrate. The bipolar devices have at least the emitter and the collector contact portions formed from a polysilicon layer which results in raised contacts. The MOS devices are similarly formed with raised gate contact portions formed from the same polysilicon layer. Metal silicide is formed over at least a portion of the base, source, and drain regions to provide conductive paths to the base, source, and drain contacts. In one embodiment, the base, source, and drain contacts are also formed from the same polysilicon layer to permit formation of a highly planarized structure with self-aligned contacts formed by planarizing an insulating layer formed over the structure sifficiently to expose the upper surface of the contacts.

Abstract: The invention relates to a method of manufacturing a Bi-CMOS semiconductor IC device in which the bipolar transistor structure contained therein has a flat PN plane junction between its base and emitter regions, said device having improved breakdown voltage characteristics.The improved method involves preparing a silicon substrate having a P-type base region formed in an N-type collector region, forming a thick silicon oxide layer over the suface of a bipolar transistor region on said substrate, selectively removing the silicon oxide layer to form a first window exposing a part of the collector region and a second window exposing a part of the base region, diffusing phosporus atoms into the base region and collector region through said first and second windows to form an emitter region in the base region and a collector contact in the collector region, subjecting the structure thus-obtained to an oxidation process in a wet oxygen atmosphere at a temperature of 940.degree. C..+-. 20.degree. C.

Abstract: A process for creating bipolar and CMOS transistors on a p-type silicon substrate is disclosed. The silicon substrate has a typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer in contact with the epitaxial layer. Walls of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon in contact with the epitaxial layer is deposited outside the walls surrounding the stacks.

Abstract: The invention includes a method of manufacture of monolithic integrated VLSI circuits comprising bipolar transistors whose base regions are contacted in a self-aligned manner in proximity to the respective emitter regions by the use of silicide layers. The invention starts out from a process which, when using an insulating masking layer portion covering up the emitter area of the planar transistor, permits the self-aligned fabrication of emitter regions extending to the adjoining base region and to the base contacting region. Further embodiments of the process according to the invention permit the simultaneous manufacture of co-integrated CMOS circuits and of polycrystalline. Si-conductor leads whose resistances are reduced owing to the use of silicide layers.

Abstract: A process for the simultaneous production of bipolar transistors and CMOS transistors on a substrate using very large circuit integration (VLSI) semiconductor technology, modified by additional process steps in such a way that a decoupling of the two types of transistors is obtained with respect to the process. This is achieved by the use of a protective oxide above the active zones of the CMOS transistors during the production of the bipolar-specific base zones and by employing a gate electrode material in two layers, the second layer being used for the emitter and collector zone, resulting in a decoupling of phosphorus doping used for forming MOS gates, and arsenic doping used for polysilicon emitters. The use of the same resist mask for the gate structuring and the production of the emitter contact, and also for the production of the source/drain terminal zones, serves to keep the implanted phosphorus out of the emitter zone.

Abstract: A process for the simultaneous production of self-aligned bipolar transistors and complementary MOS transistors on a common silicon substrate wherein n-doped zones are produced in the p-doped substrate and insulated npn-bipolar transistors are formed into the n-doped zones. The n-zones form the collectors of the transistors and are modified according to conventional technology by additional process steps such that bipolar transistors are formed which are self-aligning both between the emitter and the base and also between the base and collector with extremely low-ohmic base terminals consisting of polysilicon and a silicide. Storage capacitances can also additionally be integrated into the structure. The use of the base terminals thus produced permits very small lateral emitter-collector distances. The combination of dynamic CMOS memory cells with fast bipolar transistors is made possible by the integration of the storage capacitances.