With Heat Sink Patents (Class 174/16.3)
  • Patent number: 10172258
    Abstract: A cooling structure for large electronic boards with closely-spaced heterogeneous die and packages is disclosed. The assembly includes a frame having a plurality of openings. The assembly further includes a cold plate mounted to the frame. The cold plate includes at least one inlet and at least one outlet and fluid channels in communication with the at least one inlet and the at least one outlet. The assembly further includes a heat sink mounted within each of the plurality of openings which in combination with sidewalls of the openings of the frame and the cold plate form individual compartments each of which are in fluid communication with the fluid channels.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul F. Bodenweber, Kenneth C. Marston, Kamal K. Sikka, Hilton T. Toy, Randall J. Werner, Jeffrey A. Zitz
  • Patent number: 10163752
    Abstract: There is provided a semiconductor device provided with a metal base, a frame-shaped resin case adhered to the metal base, a semiconductor chip having a main electrode and being disposed inside the resin case, a main terminal having an internal end which is electrically connected to the main electrode of the semiconductor chip, integrally fixed to the resin case, and exposed inside the resin case and an external end exposed outside the resin case, a heat dissipation member which is placed, in contact with the metal base, between the metal base and the internal end of the main terminal, and has higher thermal conductivity than that of the resin case.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: December 25, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Kousuke Komatsu
  • Patent number: 10159151
    Abstract: A chip package circuit board module including a circuit board and at least one original chip is provided. The circuit board includes at least one first pad, at least one second pad and at least one substitute pad. The at least one second pad is located besides the at least one first pad and separated from the at least one first pad. The at least one substitute pad is adjacent to the at least one second pad and separated from the at least one first pad and the at least one second pad. The at least one original chip is connected to the at least one first pad and at least one the second pad, respectively. A total width of a portion corresponding to each of the at least one second pad and a portion corresponding to the substitute pad adjacent to the second pad of the first pad is greater than or equal to twice a width of the original chip.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: December 18, 2018
    Assignee: Unimicron Technology Corp.
    Inventors: Wen-Fang Liu, Shao-Chien Lee, Chen-Wei Tseng, Zong-Hua Li, Chien-Tsai Li
  • Patent number: 10157957
    Abstract: The present disclosure relates to a solid-state imaging element in which the cost reduction of a curved imaging element can be achieved, a method for manufacturing the solid-state imaging element, and an electronic apparatus. A curvature base is formed so as to be curved in a concave shape at a center leaving a small edge. The curvature base is divided into five portions of an element disposition portion and four peripheral portions. This element disposition portion is formed in a porous state. A pore (air bubble) in the porous state is smaller than a pixel size. A porous material such as a ceramic-based material, a metal-based material, or a resin-based material can be used as the porous material, for example. The present disclosure can be applied to a CMOS solid-state imaging element to be used for an imaging device, for example.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: December 18, 2018
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yuichi Yamamoto, Kojiro Nagaoka
  • Patent number: 10150440
    Abstract: A restraints control module (RCM) assembly attached to the tunnel in the floor of a vehicle. The bracket includes a base plate supporting the restraints control module. A helmet shield is secured over the RCM and encloses the RCM on three sides. The helmet shield includes slots that extend downwardly and outwardly from opposite side of the helmet shield that receive a plurality of bolts as the helmet shield is moved in a vertically downward direction. Two vertically extending sidewalls of the helmet shield are assembled over the RCM with a clearance being defined between the sidewalls and the RCM. The helmet shield is adapted to protect the RCM in a side impact collision.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: December 11, 2018
    Assignee: FORD GLOBAL TECHNOLOGIES, LLC
    Inventors: Mohamed Ridha Baccouche, Saied Nusier, David James Bauch, Mahmoud Yousef Ghannam, Jhony J. Barbosa
  • Patent number: 10134718
    Abstract: A power semiconductor module including a positive-side switching device and a positive-side diode device which are mounted on a positive-side conductive pattern, and a negative-side switching device and a negative-side diode device which are mounted on an output-side conductive pattern. When an insulating substrate is viewed in plan view, the positive-side diode device and the negative-side diode device are disposed between the positive-side switching device and the negative-side switching device, and the negative-side diode device is disposed closer to the positive-side switching device than the positive-side diode device is.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: November 20, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yasushige Mukunoki, Yoshiko Tamada
  • Patent number: 10121721
    Abstract: A dummy bump electrode for heat-dissipating is provided on a surface of a semiconductor chip. The semiconductor chip is mounted on a wiring substrate. A lead line is formed on the wiring substrate. The heat-dissipating bump electrode and a lead line are connected to each other through a heat dissipation pattern, thereby efficiency of the heat dissipation is improved.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: November 6, 2018
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroyoshi Ichikura
  • Patent number: 10117321
    Abstract: A device including a first semiconductor package that includes a semiconductor chip, an encapsulation material at least partly covering the semiconductor chip, and a contact element electrically coupled to the semiconductor chip and protruding out of the encapsulation material. In addition, the device includes a printed circuit board (PCB), wherein the first semiconductor package is mounted on the PCB and the contact element of the first semiconductor package is electrically coupled to the PCB. The device further includes a first metal workpiece mounted on the printed circuit board and electrically coupled to the contact element of the first semiconductor package.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: October 30, 2018
    Assignee: Infineon Technologies Austria AG
    Inventor: Elvir Kahrimanovic
  • Patent number: 10107568
    Abstract: A back plate includes flat polygonal shaped body and locking assembly located at bottom surface of the flat polygonal shaped body. The locking assembly includes pivotal member, connecting member and protruding portion with connecting hole and locking hole. The connecting hole is located at a side of the locking hole. The locking hole is a curved hole with the connecting hole as a center. The pivotal member has hinge hole hinged with the connecting hole and a fixing hole matching with the locking hole, and the fixing hole is movable with respect to the locking hole with the hinge hole as a center. The connecting member is disposed through the fixing hole and the locking hole, and is connected to the seat. The connecting member is movable in the locking hole in order to make the fixing hole to move with respect to the locking hole.
    Type: Grant
    Filed: July 2, 2017
    Date of Patent: October 23, 2018
    Assignee: COOLER MASTER TECHNOLOGY INC.
    Inventors: Yu-Te Wei, Ling She
  • Patent number: 10109547
    Abstract: A device includes a substrate with a die over the substrate. A molding compound surrounds the die and includes a structural interface formed along a peripheral region of the molding compound.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, LLC
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Shyue-Ter Leu, Shin-Puu Jeng, Chih-Kung Huang, Tsung-Ming Yeh
  • Patent number: 10104806
    Abstract: A semiconductor storage device includes a substrate having a wiring, a first semiconductor memory, a terminal portion, a holder surrounding the terminal portion, a case, and a first plate-shaped member. The first semiconductor memory is disposed on a first principal surface of the substrate and is connected to the wiring. The terminal portion is connected to the substrate at a first end portion of the substrate and has a terminal connected to the wiring. The case houses part of the holder, the substrate, and the first semiconductor memory. Between the first principal surface and a first wall portion of the case facing the first principal surface, the first plate-shaped member is disposed. The first plate-shaped member is connected to the holder and the first principal surface on a second end portion side of the substrate, and has thermal conductivity.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: October 16, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Toshiyuki Hayakawa, Shiro Harashima
  • Patent number: 10104761
    Abstract: A loudspeaker assembly comprises an enclosure having a first end and a second end, the first end including an opening; an acoustic driver at the second end of the enclosure; an acoustic volume between the first end and the second of the enclosure; a circuit board at the first end of the enclosure; a firebox covering the opening at the first end of the enclosure, the firebox providing a convection flow path in the acoustic volume over heat-generating components of the circuit board; and a heat sink extending from the circuit board in a direction away from the acoustic volume for providing a conduction flow path through the circuit board.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: October 16, 2018
    Assignee: BOSE CORPORATION
    Inventors: Thomas E. MacDonald, Kevin Brousseau
  • Patent number: 10062623
    Abstract: A semiconductor package substrate includes an insulating substrate, a circuit pattern on the insulating substrate, a protective layer formed on the insulating substrate to cover the circuit pattern on the insulating substrate, a pad formed on the protective layer while protruding from a surface of the protective layer, and an adhesive member on the pad.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: August 28, 2018
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Sung Wuk Ryu, Dong Sun Kim, Seung Yul Shin
  • Patent number: 10049805
    Abstract: A coil device has a potting resin 60. The potting resin 60 surrounds a bobbin 20 with a coil portion 12. The coil portion 12 is housed in a housing concave portion 42 of an outer case 40. Oblique plate legs 50 arranged obliquely are arranged between an outer peripheral wall 24 of the bobbin 20 and a bottom wall of the housing concave portion 42.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: August 14, 2018
    Assignee: TDK CORPORATION
    Inventor: Katsumi Kobayashi
  • Patent number: 10050015
    Abstract: Embodiments of the present disclosure describe multi-device flexible systems on a chip (SOCs) and methods for making such SOCs. A multi-material stack may be processed sequentially to form multiple integrated circuit (IC) devices in a single flexible SOC. By forming the IC devices from a single stack, it is possible to form contacts for multiple devices through a single metallization process and for those contacts to be located in a common back-plane of the SOC. Stack layers may be ordered and processed according to processing temperature, such that higher temperature processes are performed earlier. In this manner, intervening layers of the stack may shield some stack layers from elevated processing temperatures associated with processing upper layers of the stack. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: August 14, 2018
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Sansaptak Dasgupta, Niloy Mukherjee, Brian S. Doyle, Marko Radosavljevic, Han Wui Then
  • Patent number: 10041645
    Abstract: The light source unit includes: a semiconductor light emitting element; a lighting circuit configured to operate the semiconductor light emitting element; a first heat dissipation plate on which the semiconductor light emitting element is placed; a second heat dissipation plate on which the lighting circuit is placed; a wiring member electrically interconnecting the semiconductor light emitting element and the lighting circuit; and an interconnection member to which the first heat dissipation plate and the second heat dissipation plate are attached. The interconnection member is lower in thermal conductivity than the first heat dissipation plate and the second heat dissipation plate.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: August 7, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masatoshi Ueno, Masahiro Nishikawa, Hiro Aoki
  • Patent number: 10014123
    Abstract: In one embodiment of the invention, a method of forming an energy storage device is described in which a porous structure of an electrically conductive substrate is measured in-situ while being electrochemically etched in an electrochemical etching bath until a predetermined value is obtained, at which point the electrically conductive substrate may be removed from the electrochemical etching bath. In another embodiment, a method of forming an energy storage device is described in which an electrically conductive porous structure is measured to determine the energy storage capacity of the electrically conductive porous structure. The energy storage capacity of the electrically conductive porous structure is then reduced until a predetermined energy storage capacity value is obtained.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: July 3, 2018
    Assignee: INTEL CORPORATION
    Inventors: Eric C. Hannah, Cary L. Pint, Charles W. Holzwarth, John L. Gustafson
  • Patent number: 10015875
    Abstract: The current embodiments provide an assembly for cooling a printed circuit board with at least one electronic component disposed on a first surface of the printed circuit board. The assembly may have a housing with first and second elastic elements and a cooling element configured to cool the at least one electronic component. The printed circuit board may be held between the first and second elastic elements in the housing. The assembly may further have at least one cooling surface region protruding from the cooling element and facing toward a second surface facing opposite the first surface of the printed circuit board in a region opposite of the electronic component.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: July 3, 2018
    Assignee: ZF Friedrichshafen AG
    Inventors: Karl-Heinz Müller, Matthias Heid, Horst Hübner
  • Patent number: 9978723
    Abstract: A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a bonding electrode, and a dummy electrode. The first semiconductor substrate has a first surface and a first wiring, and contains a first semiconductor material. The second semiconductor substrate has a second surface and a second wiring, and contains a second semiconductor material, and the first surface and the second surface face each other. The bonding electrode is arranged between the first surface and the second surface, and is electrically connected to the first wiring and the second wiring. The dummy electrode is arranged between the first surface and the second surface, and is electrically insulated from at least one of the first wiring and the second wiring. The bonding electrode has a bonding bump and a first bonding pad. The dummy electrode has a dummy bump and a first dummy pad.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: May 22, 2018
    Assignee: OLYMPUS CORPORATION
    Inventors: Naohiro Takazawa, Yoshitaka Tadaki
  • Patent number: 9974180
    Abstract: An electronic device may have a printed circuit to which electrical components are mounted. The electrical components may include a thermal sensor and a pressure sensor. A through hole in the printed circuit may receive the shaft of a standoff. The standoff may be soldered to plated metal on the sides of the through hole. A screw or other fastener may secure the printed circuit to a housing for the electronic device. A ring-shaped metal member may be soldered to the printed circuit. The ring-shaped metal member may form a bumper that surrounds the screw or other fastener and the thermal sensor. The pressure sensor may have a port through which ambient pressure measurements are made. A dust protection cover such as a fabric or other porous layer may cover the port.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: May 15, 2018
    Assignee: Apple Inc.
    Inventors: Shayan Malek, David A. Pakula, Gregory N. Stephens, Sawyer I. Cohen, Scott A. Myers, Tyler B. Cater, Eric W. Bates
  • Patent number: 9958406
    Abstract: Methods and systems for measuring and/or estimating a coefficient of thermal expansion (CTE) of a component of a fuel cell system. A CTE measurement technique includes securing a measurement member over a surface of the component via a seal having a melting point, heating the seal above its melting point of the seal, cooling the component, measurement member and seal to a second temperature below the melting point of the seal, and determining the CTE of the component based on the change in the span of the measurement member after cooling. A fuel cell component characterization technique includes measuring an electrical resistivity (ER), conductivity (EC), resistance or conductance of the component, measuring at least one additional property of the component which, together with ER, EC, resistance or conductance, correlates to the CTE of the component, and sorting the component based on the measurements.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: May 1, 2018
    Assignee: BLOOM ENERGY CORPORATION
    Inventors: Cheng-Yu Lin, Daniel Darga, Michael Groesch, Harald Herchen, Vijay Srivatsan
  • Patent number: 9953893
    Abstract: A method of producing a power electronic assembly and a power electronic assembly including a power electronic module incorporating multiple of semiconductor power electronic switch components, the power electronic module including a base plate with a bottom surface, the power electronic assembly includes further a cooling arrangement for cooling the power electronic module, the cooling arrangement including a cooling surface adapted to be attached against the bottom surface of the base plate of the power electronic module, wherein the power electronic assembly includes further a thermal interface material arranged between the bottom surface of the base plate of the power electronic module and the cooling surface of the cooling arrangement to transfer heat from the power electronic module to the cooling arrangement, the thermal interface material includes a metal foil and a solid lubricant coating.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: April 24, 2018
    Assignee: ABB Technology Oy
    Inventors: Jorma Manninen, Pirkka Myllykoski
  • Patent number: 9941292
    Abstract: A semiconductor memory device includes a plurality of first electrode layers stacked in a first direction; a semiconductor layer extending in the first direction in the plurality of first electrode layers; a first insulating layer extending in the first direction along the semiconductor layer between the semiconductor layer and each of the plurality of first electrode layers; a second insulating layer covering the periphery of the plurality of first electrode layers; a resistive body provided on the second insulating layer; and a third insulating layer provided between the resistive body and the second insulating layer, the third insulating layer including the same material as the material of the first insulating layer.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: April 10, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroki Yamashita
  • Patent number: 9943001
    Abstract: Provided is a switch box comprising: a first circuit board; a pair of bus bars provided to the first circuit board; and a first switch portion that is provided to the first circuit board and that opens and closes a circuit between the bus bars. A second circuit board can be attached to and detached from the first circuit board, and the second circuit board comprises: one bus bar; and a second switch portion that opens and closes a circuit between the one bus bar and the bus bar of the first circuit board.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: April 10, 2018
    Assignee: Yazaki Corporation
    Inventors: Hideo Takahashi, Koji Ikegaya, Takuya Nakagawa, Masahide Tsuru
  • Patent number: 9921622
    Abstract: A stand-alone immersion tank datacenter (SITDC) includes: a multi-phase heat transfer immersion cooling tank having external walls surrounding a tank volume within which a dielectric liquid is maintained and heated to a boiling point temperature; a plurality of servers having one or more processing and memory components submerged within the dielectric liquid for cooling of the one or more components via heat dissipation from the one or more components into the dielectric liquid when the one or more components are connected to an electric power supply; and a condenser located vertically above the plurality of servers and in a direct path of rising dielectric vapor created when the dielectric liquid absorbs sufficient heat from the one or more components to reach a boiling point temperature of the liquid. The condenser can be a passive heat exchanger, created by providing a heat conductive material as a top lid of the tank.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: March 20, 2018
    Assignee: Dell Products, L.P.
    Inventors: Austin Michael Shelnutt, James D. Curlee, Jimmy Pike
  • Patent number: 9917040
    Abstract: A package is formed by a thermal base and a leadframe assembly. The thermal base includes a body of thermally conductive material having a top surface, wherein the top surface of the body includes a pedestal. An integrated circuit chip is mounted to the pedestal, the integrated circuit chip including bonding pads. The leadframe assembly includes leads and an encapsulant ring that partially embeds the leads. The leadframe assembly is mounted to the top surface of said body surrounding the pedestal. The pedestal is configured with a thickness that positions the bonding pad at a height substantially coplanar with the leads. Bonding wires extend from the bonding pads to the leads with a shortened length so as to provide for improved electrical characteristics of frequency response, impedance and inductance.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: March 13, 2018
    Assignee: STMicroelectronics, Inc.
    Inventor: Craig J. Rotay
  • Patent number: 9917224
    Abstract: A concentrated photovoltaic receiver and backplane assembly is described herein. A thermally conductive heat spreader is configured between the receiver and the backplane for dissipating at least a portion of the thermal energy in a direction including a horizontal component towards a portion of the heat spreader which is not directly in contact with a receiver portion. In some embodiments, the heat spreader is electrically conductive and is adapted for conducting current from the receiver to the backplane. In some embodiments, a surface area of a receiver substrate is less than 5 times larger than a surface area of a solar cell that is mounted onto the receiver substrate. In some embodiments, the receiver substrate comprises vias for conducting current from a top face to a bottom face of the receiver.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: March 13, 2018
    Assignee: Essence Solar Solutions Ltd.
    Inventors: Slava Hasin, Ron Helfan
  • Patent number: 9911717
    Abstract: A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon. The first package further includes first and second microelectronic elements, each having element contacts electrically connected with the substrate contacts and being spaced apart from one another on the first surface so as to provide an interconnect area of the first surface between the first and second microelectronic elements. A plurality of package terminals at the second surface are electrically interconnected with the substrate contacts for connecting the package with a component external thereto. A plurality of stack terminals are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: March 6, 2018
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Kyong-Mo Bang
  • Patent number: 9907209
    Abstract: A retaining clip is provided for use with a heat sink. The heat sink has a flat bottom surface in heat conducting engagement with an electronic device and fins extending from a top surface of the heat sink, the fins defining a channel. The retainer clip includes a middle section and a first end section and a second end section on either side of the middle section. The middle section fits within the channel and engages the heat sink to hold the bottom surface against the electronic device. The middle section further includes a portion extending above the top surface, within the channel, to limit rotation of the heat sink. Each of the first and second end sections include a pivot end adjacent to the middle section, a distal end to engage an anchor, a first leg adjacent to the distal end, a second leg adjacent to a pivot end, and a bend between the first leg and the second leg, the bend located to form a moment arm from the pivot end.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: February 27, 2018
    Assignee: Verizon Patent and Licensing Inc.
    Inventors: Gregory A. James, Steve S. Chen
  • Patent number: 9907208
    Abstract: At least one implementation provides a hold down for an electronic device. The electronic device includes a support frame, a circuit board coupled to the support frame and having at least one component, a thermal pad thermally coupled to the component, and a heat sink associated with the thermal pad. The hold down includes a generally planar portion adapted to be positioned over a surface of the heat sink. The hold down also includes a plurality of connecting structures extending angularly from the generally planar portion. The connecting structures and configured to engage the support frame to cause the hold down to apply the biasing force to retain the thermal pad against at least one of the heat sink or the component when the heat sink and the thermal pad are positioned between the hold down and the support frame. A method is also provided for attaching the hold down.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: February 27, 2018
    Assignee: THOMSON LICENSING
    Inventors: William Hofmann Bose, Mickey Jay Hunt
  • Patent number: 9893643
    Abstract: In a semiconductor module, at least one snubber circuit module is attachable/detachable to/from an interior communicated with a snubber-circuit-connecting opening; a plurality of snubber-circuit electrodes for electrically connecting with the at least one snubber circuit module are joined with a circuit pattern; the plurality of snubber-circuit electrodes are disposed in the interior of the snubber-circuit-connecting opening; in a state that the snubber circuit module is attached in the interior of the snubber-circuit-connecting opening, the snubber circuit module does not stick out from an outer surface of an outer enclosure member, the plurality of snubber-circuit electrodes are in surface-contact with electrodes in the side of the snubber circuit module, respectively; and the snubber-circuit-connecting opening and the interior are not overlapped with the at least one semiconductor element in a planar view.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: February 13, 2018
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Nobuhisa Honda, Yasuo Kotake
  • Patent number: 9881847
    Abstract: A semiconductor structure includes a semiconductor substrate having a recess disposed beneath a semiconductor device. The semiconductor structure also includes a thermally conductive core disposed in the recess, and a package substrate including a heat sink. The heat sink is in thermal contact with the thermally conductive core.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: January 30, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Nathan Perkins
  • Patent number: 9875992
    Abstract: An embodiment includes a semiconductor package comprising: a substrate; a first semiconductor chip mounted on the substrate; a second semiconductor chip mounted on a top surface of the first semiconductor chip; a connecting bump disposed between the first and second semiconductor chips to electrically connect the second semiconductor chip to the first semiconductor chip; and a first heat dissipation part disposed on the top surface of the first semiconductor chip between the first and second semiconductor chips and spaced apart from a bottom surface of the second semiconductor chip.
    Type: Grant
    Filed: August 9, 2015
    Date of Patent: January 23, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junyeong Heo, Chajea Jo, Taeje Cho
  • Patent number: 9859186
    Abstract: A heat sink for a semiconductor chip device includes cavities in a lower surface thereof for receiving electrical components on a top surface of the semiconductor chip, and a pedestal extending through an opening in the semiconductor chip for contacting electrical components on a bottom surface of the semiconductor chip. A lid may also be provided on the bottom surface of the semiconductor chip for protecting the electrical components and for heat sinking the electrical components to an adjacent device or printed circuit board.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: January 2, 2018
    Assignee: Elenion Technologies, LLC
    Inventor: Nathan A. Nuttall
  • Patent number: 9831190
    Abstract: Between an adhesive surface of a heat spreader lid and a top surface of a semiconductor package, in addition to a spreader adhesive layer, several warpage control adhesive layers are also provided. The warpage control adhesive layers are disposed on corner areas of the adhesive surface of the heat spreader lid to reduce high temperature warpage of the semiconductor device package.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: November 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Chih Yew, Fu-Jen Li, Po-Yao Lin, Kuo-Chuan Liu
  • Patent number: 9831150
    Abstract: According to one embodiment, a semiconductor device includes a first substrate, a second substrate, a first electronic component, a heat-conducting layer, a covering portion, and a heat-transporting portion. The first substrate has a first face and the second substrate has a second face and a third face. The first electronic component has a fourth face and a fifth face. The heat-conducting layer covers the third face and the fifth face. The covering portion covers at least the heat-conducting layer. The heat-transporting portion thermally connects the heat-conducting layer and the first substrate, and is located outside the second substrate and outside the covering portion.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: November 28, 2017
    Assignee: Toshiba Memory Corporation
    Inventor: Tatsuro Hiruta
  • Patent number: 9832876
    Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: November 28, 2017
    Assignee: Intel Corporation
    Inventors: Mani Prakash, Thomas T. Holden, Jeffory L. Smalley, Ram S. Viswanath, Bassam N. Coury, Dimitrios Ziakas, Chong J. Zhao, Jonathan W. Thibado, Gregorio R. Murtagian, Kuang C. Liu, Rajasekaran Swaminathan, Zhichao Zhang, John M. Lynch, David J. Llapitan, Sanka Ganesan, Xiang Li, George Vergis
  • Patent number: 9805979
    Abstract: An electronic package is provided, which includes: an electronic element having an active surface with a plurality of electrode pads, an inactive surface opposite to the active surface, and a side surface adjacent to and connecting the active and inactive surfaces; a plurality of conductive elements formed on the electrode pads of the electronic element; and an encapsulant covering the active and side surfaces of the electronic element and portions of side surfaces of the conductive elements and exposing the inactive surface of the electronic element. Therefore, the invention enhances the structural strength of the active surface of the electronic element so as to prevent cracking of the electronic element and hence avoid delamination of the conductive elements from the electronic element.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: October 31, 2017
    Assignee: Siliconware Precision Industires Co., Ltd.
    Inventors: Shao-Tzu Tang, Chang-Yi Lan, Ying-Chou Tsai
  • Patent number: 9806010
    Abstract: A method of fabricating a package module includes placing a pin frame having plural pins on a circuit substrate; bonding the pins to corresponding bonding areas on a circuit substrate, thereby connecting the pins to the bonding areas; cutting off a connecting portion of the pin frame; and bending the pins to be vertical to the circuit substrate. By placing the pins on the corresponding bonding areas on the circuit substrate through the pin frame, and then cutting off the connecting portion of the pin frame and bending the pins, the efficiency of assembling the package module can be greatly promoted.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: October 31, 2017
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Kai Lu, Zhen-Qing Zhao, Tao Wang
  • Patent number: 9793191
    Abstract: A semiconductor device packaging system includes a substrate, a heat spreader, a stiffener attached to the substrate, and at least one die electrically coupled to the substrate and thermally coupled to the heat spreader. The semiconductor device packaging system further includes at least one stud coupled to one of the stiffener and the heat spreader and at least one orifice formed through one of the stiffener and the heat spreader. In addition, the at least one orifice is aligned with the at least one stud.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: October 17, 2017
    Assignee: General Electric Company
    Inventor: Gamal Refai-Ahmed
  • Patent number: 9788428
    Abstract: The invention provides a stacked structure comprising a master circuit board and at least two slave circuit boards. The master circuit board comprises a plurality of connecting seats. Each slave circuit board is equipped with a connector, and defined with a plurality of post-production process areas. Wherein the connector of each slave circuit board is disposed on one of post-production process areas, and inserted into the corresponding connecting seat. When the connector of the slave circuit board must be through other slave circuit boards in order to insert the corresponding connecting seat, the post-production process areas that are disposed on other slave circuit boards and impede the connection between the connector and the corresponding connecting seat will be cut into hollow areas. Accordingly, the connector of the slave circuit board is capable of inserting the corresponding connecting seat through the hollow areas of other slave circuit boards.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: October 10, 2017
    Assignee: INNODISK CORPORATION
    Inventors: Chih-Hsing Chen, Hsiao-Yu Wang
  • Patent number: 9780014
    Abstract: A method of mounting a plurality of semiconductor or microelectronic chips or dies, the method including providing a carrier, temporarily adhering the plurality of semiconductor or microelectronic chips or dies to the carrier with active faces of the chips or dies facing towards the carrier, covering backsides of the chips and filling empty spaces between the chips or dies with a metallic material to thereby define an assembly of the chips or dies and the metallic material, and releasing the assembly from the carrier, wherein each chip or die comprises at least one bonding ring higher than a height of the active face of the respective chip or die or any connections on the active face of the respective chip or die.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: October 3, 2017
    Assignee: HRL Laboratories, LLC
    Inventors: Alexandros D. Margomenos, Miroslav Micovic
  • Patent number: 9781850
    Abstract: An electronic controller which includes a cover connected to a base plate, a housing, and a printed circuit board disposed in the housing. The base plate includes a press-fit inspection opening or aperture, and a cover is placed on the base plate over the opening, creating a seal path between the cover and the edge of the opening in the base plate. In one embodiment, there is a sealant, such as room temperature vulcanization (RTV) or heat cured sealant, dispensed on the sheet metal base plate around the perimeter of the opening, and the sealant is cured to prevent the formation of a leak path. Prior to the curing process, the cover is held in place by a pressure sensitive adhesive (PSA), as the sealant is cured. The controller is treated to a curing process to cure the sealant between the cover and the base plate.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: October 3, 2017
    Assignee: Continental Automotive Systems, Inc.
    Inventors: David Wayne Currier, Donald J Zito, Keith A Meny, James D Baer
  • Patent number: 9775265
    Abstract: A heatsink to be mounted on a circuit board including a plurality of electronic parts is constituted of a conductive and rectangular plate-shaped member, and mounted on the circuit board such that a main surface of the heatsink blocks an airflow generated on the circuit board, the heatsink being electrically grounded. The main surface includes a contacting portion disposed in contact with the circuit board and an isolated portion separated from the circuit board, the isolated portion being cut into two parts along a straight line extending in a direction away from the circuit board. The two parts are each bent such that an end portion on a side of the straight line is oriented to a downstream side of the airflow, so that an opening is defined between the respective end portions of the two parts on the side of the straight line.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: September 26, 2017
    Assignee: KYOCERA Document Solutions Inc.
    Inventor: Shogo Yoneda
  • Patent number: 9754868
    Abstract: A substrate structure is provided, which includes: a substrate body having a first surface and a second surface opposite to the first surface; and a plurality of conductive posts disposed on the first surface of the substrate body and electrically connected to the substrate body. By replacing conventional through silicon vias (TSVs) with the conductive posts, the present disclosure greatly reduces the fabrication cost. The present disclosure further provides an electronic package having the substrate structure and a method for fabricating the electronic package.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: September 5, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Ching-Wen Chiang, Hsin-Chih Wang, Chih-Yuan Shih, Shih-Ching Chen
  • Patent number: 9735826
    Abstract: An electronic device may include a noise shielding device that may include: a substrate including at least one heat generating component; a metallic shield cover that is disposed on the substrate to enclose the at least one heat generating component; a metal housing disposed around the shield cover; and a heat transfer member that is configured to transfer heat emitted from the heat generating component through an opening formed at a position corresponding to the heat generating component to the metal housing, wherein the metallic shield cover includes a plurality of tension fingers that protrude at predetermined intervals and contact a bottom face of the metal housing, and noise emitted from the heat generating component is shielded by a shielding region that is formed by the tension fingers and the metal housing.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: August 15, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongryul Sohn, Cheolwoong Park, Hosoo Seo
  • Patent number: 9713293
    Abstract: An electric power converter includes a semiconductor module constituting a power conversion circuit, a capacitor electrically connected to the semiconductor module, and a cooling member for cooling the capacitor. The capacitor includes an element body provided with internal electrode, and a pair of end-face-electrodes provided on both end faces of the element body and connected to the internal electrode. The pair of end-face-electrodes are connected with a pair of bus bars, respectively, in a manner of surface contact. The capacitor is disposed in a state where one of the pair of end-face-electrodes is facing the cooling member. The end-face-electrode facing the cooling member is in contact with the cooling member via the bus bar.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: July 18, 2017
    Assignee: DENSO CORPORATION
    Inventors: Kazuya Takeuchi, Makoto Okamura, Yuuichi Handa, Naoki Hirasawa, Hiromi Ichijo, Ryota Tanabe, Tetsuya Matsuoka
  • Patent number: 9704776
    Abstract: The present invention provides a semiconductor device that is reduced in size by changing the structure of a fixing portion used for fixing a semiconductor module to a cooler. Bolts 17 are inserted through first through-holes 4 of external conductive terminals 3, second through-holes 6 formed in a resin frame 5, and third through-holes 10 formed in a top plate 9, and the ends of the bolts 17 are screwed to resin nuts 16. External wiring 25, the external conductive terminals 3, a semiconductor module 1, and a cooler 2 are fastened by the bolts 17, thereby fixing the whole members.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: July 11, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Ryuichi Sawagashira
  • Patent number: 9693456
    Abstract: This substrate includes an insulating substrate having a first surface and a second surface, and a metal layer of a metal plate bonded to the first surface. The insulating substrate has a through hole. The metal layer includes: a bent section that is inserted through the through hole and bulges from the first surface toward the second surface; and outer periphery sections that are positioned around the bent section and are bonded to the first surface. The bent section has a first end and a second end positioned on opposite sides, and is bent with respect to the outer periphery sections at the first end and the second ends. The outer periphery sections are divided into a first outer periphery section and a second outer periphery section, which are respectively continuous with the first end and the second end of the bent section.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: June 27, 2017
    Assignee: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Kiminori Ozaki, Yasuhiro Koike, Hiroaki Asano, Hitoshi Shimadu, Shigeki Kawaguchi, Tomoaki Asai
  • Patent number: 9661689
    Abstract: A cooling and holding device for heating-elements, more particularly PTC heating-elements, including a flat housing having at least one heating shaft in which there is at least one heating-element, wherein the heating shaft has opposing shaft walls between which the heating-element is clamped, and at least one side slit that separates the shaft walls such that the distance between the shaft walls can be varied for installation of the heating-element, wherein at least one clamping section outwardly protruding from the flat housing, grips the flat housing, spanning the side slit, and is elastically deformed in the mounted state of the heating-element so as to provide a pressing force of the shaft walls on the heating-element in the assembled state.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: May 23, 2017
    Assignee: STEGO-HOLDING GMBH
    Inventors: Robert Dent, Elmar Mangold