Abstract: A circuit board includes a substrate, a build-up circuit structure, a graphene oxide layer, a graphene layer, and an insulating material layer. The build-up circuit structure is disposed on the substrate, including at least one inner circuit, at least one dielectric layer, an outer circuit, and multiple conductive vias. The dielectric layer is disposed on the inner circuit. The outer circuit is disposed on the dielectric layer. The conductive vias penetrate the dielectric layer and electrically connect the inner circuit and the outer circuit. The graphene oxide layer and the graphene layer are disposed on the build-up circuit structure at an interval. The graphene oxide layer and the graphene layer are respectively disposed in correspondence to the dielectric layer and the outer circuit. The insulating material layer is disposed on the graphene oxide layer and the graphene layer. The insulating material layer has an opening, which exposes the graphene layer.

Abstract: Provided is a plating lamination technology for providing a highly adhesive inner layer of a printed circuit board. The plating lamination technology is effective in providing an electroless plated laminate, including a non-etched/low-roughness pretreated laminate or a low-roughness copper foil, and a printed circuit board including the plated laminate.

Abstract: An information handling system printed circuit board includes solder pads that accept footprint compatible integrated circuits, such as charger integrated circuits that provide power with different choke circuit supporting components. Solder pads for supporting components include first and second conductive areas sized to accept a first supporting component, each of the first and second conductive areas including an intervening non-conductive area that manages positioning of a smaller second supporting component at solder reflow.

Abstract: According to various examples, a device is described. The device may include a printed circuit board. The device may also include a first recess in the printed circuit board, wherein the first recess comprises a circular side surface and a bottom surface. The device may also include a first solder ball disposed in the first recess. The device may also include a first conductive wall positioned behind the circular side surface of the first recess, wherein the first conductive wall surrounds a side surface of the first solder ball.

Abstract: A circuit board is a circuit board on which a predetermined circuit unit that causes heat and electromagnetic noise is disposed, and which is to be fixed to a conductive housing with a conductive screw. The circuit board includes: an insulator layer including an insulating plate-shaped base material; a conductor layer having a circuit pattern including a ground portion, which is disposed on at least one surface of the insulator layer; and a screw insertion hole that penetrates the insulator layer and the ground portion, and through which the conductive screw is to be inserted. The ground portion has a slit disposed between the screw insertion hole and the predetermined circuit unit. The ground portion has a ground bridge that electrically connects a portion of the ground portion between the slit and the screw insertion hole and a portion of the ground portion between the slit and the predetermined circuit unit.

Abstract: Bus bars are soldered to a wiring pattern of a printed board to which the bus bars are connected, and the bus bars are screwed to the printed board. Tips of bolts passing through holes in the bus bars and holes in the punted board may be tightened using nuts. The holes in the printed board may be electrically connected to the wiring pattern.

Abstract: According to one embodiment, a printed circuit board includes a base substrate, a first pad located on the base substrate, a second pad located on the base substrate alongside the first pad with respect to a first direction X with a gap therebetween and a solder resist covering the base substrate and including a cavity portion in a position overlapping the first pad and the second pad, the solder resist including a first protruding portion projecting in a second direction crossing the first direction and a second protruding portion projecting in the second direction on an opposite side to the first protruding portion, and the first protruding portion and the second protruding portion each overlap the gap, an end of the first pad on a gap side, and an end of the second pad on a gap side.

Abstract: A method includes forming an under bump metallization (UBM) layer over a dielectric layer, forming a redistribution structure over the UBM layer, disposing a semiconductor device over the redistribution structure, removing a portion of the dielectric layer to form an opening to expose the UBM layer, and forming a conductive bump in the opening such that the conductive bump is coupled to the UBM layer.

Abstract: The present invention relates to a single board computer system with an improved memory and layout. The unique layout of the printed circuit board of the present invention allows for different parts to be placed in a back-to-back configuration to minimize the dimensions of the printed circuit board. This includes a high-performance radiation-hardened reconfigurable FPGA, for processing computation-intensive space systems, disposed on both sides of the printed circuit board. Four dual double data rate synchronous dynamic random-access memories (DDR2 SDRAMs) disposed on both the top side and on the bottom side of the printed circuit board reduce an operating voltage of said printed circuit board. A layout stack-up of the printed circuit board includes twenty-two symmetrical layers including ten ground layers, four power layers, six signal layers, a top layer, and a bottom layer.

Abstract: Provided is a screen printing device. A screen printing device according to an embodiment of the present invention includes: a screen disposed adjacent to an upper portion of a substrate on which a printing process is performed, and having a pattern to be printed on the substrate; a printing unit disposed on an upper portion of the screen and configured to discharge ink supplied from the outside to the screen and to print the pattern on the substrate; a driver connected to at least one of the screen and the printing unit and configured to drive at least one of the screen and the printing unit; and a controller connected to the printing unit and the driver and configured to control operations of the printing unit and the driver, wherein, when at least one of the screen and the printing device moves in a state in which the printing unit contacts the screen, the controller controls the printing device to perform printing on the substrate by using discharge pressure of the ink.

Abstract: A semiconductor device includes: a first semiconductor chip; plural redistribution lines provided on a main face of the first semiconductor chip, the plural redistribution lines including a redistribution line that includes a first land and a redistribution line that includes a second land; a first electrode provided within the first land, one end of the first electrode being connected to the first land, and another end of the first electrode being connected to an external connection terminal; and a second electrode provided within the second land, one end of the second electrode being connected to the second land, wherein a shortest distance between an outer edge of the second land and an outer edge of the second electrode, is less than, a shortest distance between an outer edge of the first land and an outer edge of the first electrode.

Abstract: Couplers for ultrasound probes can have a solid coupler body and a probe attachment member that is secured to a coupler body. The probe attachment member may extend upwardly from the coupler body. The probe attachment member may frictionally and/or adhesively engage with an ultrasound probe, thereby attaching and/or holding the coupler body to an end of the ultrasound probe. The coupler body may include at least one open channel that that extends through the coupler body to define a fluid path. The at least one open channel may be sized to hold and/or contain a fluid and/or gel in and/or on the coupler body and only release the fluid and/or gel when a force is exerted at a top surface of the coupler body. A coupler may be provided in a package in an orientation and easy to use fashion that may aid in attaching the coupler to an end of an ultrasound probe.

Abstract: A method of forming a multi-layered printed circuit board (PCB) may include, with a printing device, delivering a flexible medium to at least one fluid jet printhead. Printing an electrically conductive fluid on the flexible medium may be performed with at least one fluid jet printhead, to form a first conductive layer on the flexible medium. With the at least one fluid jet printhead, an electrically insulating fluid may be printed on the first conductive layer to form at least one insulating layer on the first conductive layer. With the at least one fluid jet printhead, the electrically conductive fluid may be printed on the at least one insulating layer to form a second conductive layer.

Abstract: A wiring board, a multilayer wiring board, and a method of manufacturing a wiring board adapted to make the filling of through holes and the formation of fine wiring patterns. The wiring board comprises an insulator; a through hole between front and back surfaces of the insulator; a through hole conductor for electrically connecting front and back surface side openings; through hole lands around the front and the back surface side openings, and connected to the through hole conductor; lid plating conductors on the front and the back surface sides, and placed on the respective through hole lands; and wiring patterns formed on the front are compatible and the back surface of the insulator. The thickness of the through hole lands is 1.0 ?m or more and 10.0 ?m or less, and the area of each lid plating conductor is less than the area of each through hole land.

Abstract: A printed circuit board includes an insulating layer having a first surface and a second surface opposing the first surface; and a first wiring including a first line pattern disposed on the first surface of the insulating layer, and a plurality of first protruding patterns penetrating a portion of the insulating layer from the first surface and connected to the first line pattern, respectively, such that the plurality of first protruding patterns overlap the first line pattern in a plan view of the printed circuit board.

Abstract: A press-fit pin for a semiconductor package includes a shaft terminating in a head. A pair of arms extends away from a center of the head. Each arm includes a curved shape and the arms together form an s-shape. A length of the s-shape is longer than the shaft diameter. An outer extremity of each arm includes a contact surface configured to electrically couple to and form a friction fit with a pin receiver. In implementations the press-fit pin has only two surfaces configured to contact an inner sidewall of the pin receiver and is configured to contact the inner sidewall at only two locations. The shaft may be a cylinder. The s-shape formed by the pair of arms is visible from a view facing a top of the press-fit pin along a direction parallel with the longest length of the shaft. Versions include a through-hole extending through the head.

Abstract: Disclosed is a composite printed circuit board including a first printed circuit board (PCB) having a first circuit pattern mounted thereon, and a second PCB having a second circuit pattern mounted thereon, and the first PCB penetrates and is coupled to the second PCB so that the first circuit pattern is electrically connected to the second circuit pattern.

Abstract: The present invention relates to a single board computer system with an improved memory and layout. The unique layout of the printed circuit board of the present invention allows for different parts to be placed in a back-to-back configuration to minimize the dimensions of the printed circuit board. This includes a high-performance radiation-hardened reconfigurable FPGA, for processing computation-intensive space systems, disposed on both sides of the printed circuit board. Four dual double data rate synchronous dynamic random-access memories (DDR2 SDRAMs) disposed on both the top side and on the bottom side of the printed circuit board reduce an operating voltage of said printed circuit board. A layout stack-up of the printed circuit board includes twenty-two symmetrical layers including ten ground layers, four power layers, six signal layers, a top layer, and a bottom layer.

Abstract: A package substrate structure includes a first substrate, a second substrate, a plurality of conductive pillars and an adhesive layer. The first substrate includes a plurality of vias and a plurality of pads. The vias and the pads are disposed on the first substrate, and fills the vias. The second substrate is disposed opposite to the first substrate. Each conductive pillar is disposed between the first substrate and the second substrate, where each conductive pillar electrically connects each pad and the second substrate, and the adhesive layer fills the gaps between the conductive pillars. A bonding method of the package substrate structure is also provided.

Abstract: A method for mounting SMD components on contact springs in electric motors. In a first method variation, the SMD component is mounted on the base of a carrier of the electric motor, which has already been provided with a contact spring protruding into a cavity. As the SMD component is installed, the contact spring is pressed back such that no frictional or sliding contact arises during installation. In a second variation, the SMD component is mounted first and then a contact spring is inserted using a press tool. As the contact spring is inserted, the spring is held back such that likewise no frictional or sliding contact arises with the SMD component that has already been installed. This avoids damage to the SMD component caused by the contact spring during installation.

Abstract: A heat radiating member includes: a composite portion composed of a composite material which contains particles of a satisfactorily thermally conductive material in a metal matrix; and a metal layer formed on at least one surface of the composite portion and composed of a metal. A method for producing a heat radiating member includes: a preparation step to prepare a composite material which contains particles of a satisfactorily thermally conductive material in a metal matrix; a powder arrangement step to dispose a metal powder composed of metal particles on at least one surface of the composite material; and a heating step to heat the composite material and the metal powder, with the metal powder disposed on the composite material, to form a metal layer composed of a metal of the metal powder on a composite portion composed of the composite material.

Abstract: An electronic breadboard system may include a computing device including a display screen. The display screen has a first portion to display an electronic circuit model and a second portion directly adjacent to the first portion. The electronic breadboard system also includes a translucent breadboard on the second portion of the display screen. The translucent breadboard includes a translucent face plate having a rectangular grid of openings exposing a plurality of contacts. The plurality of contacts are arranged lengthwise along each row of the rectangular grid of openings and orthogonal to a transparent back plate coupling the plurality of contacts to the translucent face plate. The electronic breadboard system includes a graphics controller. The graphics controller may illuminate a row opening and/or a column opening of the translucent breadboard to direct placement of electrical components of a computer model in response to user interaction with the electronic circuit model.

Abstract: Embodiments of the present disclosure are directed towards package assemblies, as well as methods for forming package assemblies and systems incorporating package assemblies. A package assembly may include a substrate including a plurality of build-up layers, such as bumpless build-up layer (BBUL). In various embodiments, electrical routing features may be disposed on an outer surface of the substrate. In various embodiments, a primary logic die and a second die or capacitor may be embedded in the plurality of build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power or a ground signal between the second die or capacitor and the electrical routing features, bypassing the primary logic die.

Abstract: Apparatuses and methods including an apparatus for an electronics package are disclosed. According to one embodiment, the apparatus can include one or more magnetic inductors, one or more capacitors positioned one of above or below to the one or more magnetic inductors and a plurality of electrical conductors comprising pillars. The pillars can extend substantially vertically to electrically connect the one or more magnetic inductors and the one or more capacitors to the electronics package and the one or more magnetic inductors, the one or more capacitors and the plurality of conductors are disposed one of above or below the electronics package; and at least one electrical conductor comprising a pillar extending substantially vertically to electrically connect the one or more magnetic inductors and the one or more capacitors.

Abstract: Semiconductor packages with embedded bridge interconnects, and related assemblies and methods, are disclosed herein. In some embodiments, a semiconductor package may have a first side and a second side, and may include a bridge interconnect, embedded in a build-up material, having a first side with a plurality of conductive pads. The semiconductor package may also include a via having a first end that is narrower than a second end. The bridge interconnect and via may be arranged so that the first side of the semiconductor package is closer to the first side of the bridge interconnect than to the second side of the bridge interconnect, and so that the first side of the semiconductor package is closer to the first end of the via than to the second end of the via. Other embodiments may be disclosed and/or claimed.

Abstract: An electric conduction component fixation structure includes: a fixed member which has electrically conductive properties and on which an electric conduction component is arranged; and a press member that presses and fixes the electric conduction component, which is arranged on the fixed member, to the fixed member, wherein the fixed member includes a pressed surface that is pressed when the electric conduction component is fixed by the press member, and the pressed surface is covered by a rustproof coating film having a plurality of metal flakes which are layered and a binder which joins the plurality of metal flakes.

Abstract: An electronic device has a control board having a plurality of wiring layers, a metal-made housing supporting the control board, and a fixing screw for fixing the control board to the housing through a washer. The control board includes a through hole penetrating from a third surface to a fourth surface, a through electrode formed inside the through hole, and a power system GND pattern formed on any wiring layer of the wiring layers. The power system GND pattern and the housing are electrically coupled through the through electrode, the washer, and the fixing screw.

Abstract: A wiring substrate includes a first wiring layer, an insulation layer arranged on the first wiring layer and formed of a photosensitive resin, a via hole formed in the insulation layer and reaching the first wiring layer, and a second wiring layer formed in the via hole and on the insulation layer and connected to the first wiring layer. A surface of the first wiring layer in the via hole is formed as a roughened surface.

Abstract: Systems and methods for grooved vias are described. For example, a method may include: drilling a via hole in a Printed Circuit Board (PCB), where the PCB comprises a first layer having a first trace and a second layer having a second trace, the via hole includes a first portion between the first layer and the second layer and a second portion between the second layer and a bottom surface of the PCB, and the via hole is configured to couple the first trace to the second trace through the first portion; after drilling the via hole, creating a rough internal surface in at least the second portion of the via hole that is configured to reduce a resonance of a signal transmitted from the first trace to the second trace; and forming a via by filling the first and second portions of the via hole with conductive material.

Abstract: Plugs, receptacles, and assemblies including same. The plug can include an interface having a plurality of pins extending therefrom. The plug can have a plug density of at least 280 pins/in2. The plurality of pins can be positioned in at least three rows along a longitudinal axis of the interface. The receptacle can have an interface having a plurality of sockets disposed therein. The receptacle can have a receptacle density of at least 280 sockets/in2. The plurality of sockets can be positioned in at least three rows along a longitudinal axis of the interface.

Abstract: A semiconductor package includes: a substrate including a conductive pad; a semiconductor device including a conductive member; and a connection element between the conductive pad and the conductive member, wherein the connection element has a sidewall, and an angle of the sidewall relative to the conductive pad is equal to or less than about 90 degrees.

Abstract: An adapter apparatus and methods for using in providing such adapter apparatus include providing a substrate having a plurality of openings defined therethrough. A plurality of conductive elements are mounted within corresponding openings thereof using a flowable and curable laminate material.

Abstract: According to exemplary embodiments, a tapered surface interconnect is formed on a printed circuit board (PCB). A compliant pin of an electrical connector may be coupled to the tapered surface interconnect and soldered thereto. The surface interconnect may be formed by drilling through one or more layers of the PCB. The depth of the surface interconnect may be shorter than a height or a thickness of the PCB. The surface interconnect may have a tapered side wall to allow for a better fit with a tapered compliant pin. The inclination of the side wall of the surface interconnect may be linear or concave. The intersection between the tapered sidewall and the bottom of the surface interconnect may be rounded to minimize pin insertion issues and may allow for easier solder flux evacuation. The compliant pin may be soldered into place upon being coupled to the tapered surface interconnect.

Abstract: An electronic control module for a gear mechanism controller in motor vehicles includes a printed circuit board and an electrical component. The printed circuit board has a mounting side and includes conductor tracks. The electrical component has an electrically conductive connection section. The control module further includes a press contact that is pressed into an opening in the printed circuit board such that it is mechanically fixed to the printed circuit board. The press contact forms an electrical contact with a conductor track of the printed circuit board via an electrically conductive mating connection section of the press contact. The connection section of the electrical component is connected to the mating connection section of the press contact by a welded connection. The connection technique enables soldered connections to be dispensed with and replaced by cold pressing of press contacts and subsequent welding by, for example, a copper/copper laser welding process.

Abstract: Surface-mount technology (SMT) devices and related methods. In some embodiments, an SMT device can include an electrical element and a plurality of terminals connected to the electrical element. The SMT device can further include a body configured to support the electrical element and the plurality of terminals. The body can have a rectangular cuboid shape with a length, a width, and a height that is greater than the width. The body can include a base plane configured to allow surface mounting of the SMT device. In some embodiments, the SMT device can be, for example, a capacitor, an inductor, or a resistor.

Abstract: A semiconductor device includes a molding compound and a through via extending through the molding compound. A via connection is disposed over the through via and a cap is disposed over the via connection. A plurality of holes are formed in a section of the cap.

Abstract: The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy stack resists Sn migration toward the upper metallization of the device.

Abstract: A method for producing a stack of semiconductor devices and the stacked device obtained thereof are disclosed. In one aspect, the method includes providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material. The method also includes providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. The method further includes mounting the devices by landing the metal protrusion in the hole, where the compliant layer is spaced from the dielectric layer. The method includes thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.

Abstract: The present disclosure provides a semiconductor package that prevents a bump bridge from being formed between adjacent conductive bumps to realize a fine bump pitch when each unit circuit part is directly stacked without using a printed circuit board and a method for manufacturing the same. The semiconductor package includes a first semiconductor chip structure including a first unit circuit part, a first passivation layer disposed on the first unit circuit part, and a conductive bump electrically connected to the first unit circuit part, and a second semiconductor chip structure including a second unit circuit part, a second passivation layer having a stepped portion that is recessed inward and disposed on the second unit circuit part, and a bump pad provided in the stepped portion. The first semiconductor chip structure and the second semiconductor chip structure are stacked to allow the conductive bump to be bonded to the bump pad within the stepped portion.

Abstract: A mechanical and electrical connection system including a printed circuit board, a busbar and an electrical component, wherein the board includes a first orifice in which a bottom foot of the bar is received and includes a second orifice in which a lug of the component is received, and wherein the bar includes an elastically deformable clamp which receives the lug of the component.

Abstract: Perforating graphene and other two-dimensional materials with holes inclusively having a desired size range, a narrow size distribution, and a high hole density can be difficult to achieve. A layer in continuous contact with graphene, graphene-based materials and other two-dimensional materials can help promote hole formation. Processes for perforating a two-dimensional material can include exposing to an ion source a two-dimensional material in continuous contact with at least one layer, and interacting a plurality of ions from the ion source with the two-dimensional material and with the at least one layer. The ion source may be a broad ion beam.

Abstract: A multilayer resin substrate includes resin substrates laminated together, an overlapping portion in which a signal line as a conductor pattern and another conductor pattern overlap each other in a laminating direction of the resin substrates, and a non-overlapping portion in which the signal line and the other conductor pattern do no overlap each other in the laminating direction. A thin portion is provided at a position in the non-overlapping portion near the overlapping portion. The thin portion is a portion of the multilayer resin substrate which has a thickness smaller than the thickness in the overlapping portion in the laminating direction of the resin substrates.

Abstract: An electronic component unit and a wire harness are provided with a bus bar plate. The bus bar plate is provided with a metallic bus bar that is built in a resin material, and including a through-hole in which a terminal of a relay mounted on a mounting surface is soldered. The through-hole is provided with a bus bar through-hole which penetrates the bus bar, and a resin material through-hole which penetrates the resin material and is formed to be larger than the bus bar through-hole to expose the surface of the bus bar. When an inner diameter of the bus bar through-hole is defined as r and an inner diameter of the resin material through-hole is defined as R, 1.5r?R is satisfied.

Abstract: When soldering a package having an electrode on which Ni/Au or Ag—Pd alloy is plated, to a printed circuit board having a Cu electrode or an electrode on which Cu is plated, a solid-phase diffusion layer is formed within a layered solder material for bonding different species of electrodes. The layered solder material is composed of a solder material of Sn—Ag—Cu series or Sn—Sb series and a solder material of Sn—Ag—Cu—Ni series or Sn—Pb series. The electrode on which Ni/Au or Ag—Pd alloy is plated and the Cu electrode or the electrode on which Cu is plated are soldered with the solder material of Sn—Ag—Cu series or Sn—Sb series being attached to the Cu electrode and the solder material of Sn—Ag—Cu—Ni series or Sn—Cu series being attached to the electrode on which Ni/Au or Ag—Pd alloy is plated. This restrains formation of intermetallic compounds and provides high bonding reliability.

Abstract: A carrier substrate includes an insulation layer, conductive towers and a circuit structure layer. A diameter of each of the conductive towers is increased gradually from a top surface to a bottom surface, and the conductive towers include first conductive towers and second conductive towers surrounding the first conductive towers. The circuit structure layer is disposed on the insulation layer and includes at least one dielectric layer, at least two circuit layers and first conductive vias. Each of the second conductive towers correspondingly connects to at least two of the first conductive vias, and each of the first conductive towers correspondingly connects to one of the first conductive vias. An interface exists between the first conductive vias and the first and the second conductive towers.

Abstract: A method of manufacturing a semiconductor device according to the present invention comprises: a bump forming step of forming a bump electrode 100 on a semiconductor chip 1, the bump electrode 100 protruding in a substantially conical shape; a pad forming step of forming a pad electrode 200 on a substrate 10, the pad electrode 200 having a recess 210 with inner lateral surfaces thereof defining a substantially pyramidal shape or a prism shape; a pressing step of pressing the bump electrode 100 and the pad electrode 200 in a direction which brings them closer to each other, with the bump electrode 100 being inserted in the recess 210 so that the central axis of the bump electrode 100 and the central axis of the recess 210 coincide with each other; and an ultrasonic joining step of joining the bump electrode 100 and the pad electrode 200 by vibrating at least one of the bump electrode 100 and the pad electrode 200 using ultrasonic waves.

Abstract: Disclosed substrate with embedded component includes: an insulating base member; a conductive pad formed on the insulating base member; a component connected to the conductive pad with a solder; and a resin covering the component, wherein a hole is provided in the insulating base member and the conductive pad, and the insulating base member is exposed on a side surface of the hole.

Abstract: A connecting pin for an electronic circuit board electrically connects a lead of a component to be surface-mounted to the electronic circuit board to a coating layer on an inner wall of a through-hole of the electronic circuit board. The connecting pin includes a cylindrical body formed of an electrically conductive metal, which is inserted into the through-hole of the electronic circuit board. The lead of the component is press-fitted, and inner surface of the cylindrical body is provided with a plurality of small protrusions deformable when contacting protrusions of the press-fitted lead.

Abstract: Various methods for preparing and/or processing electrically conductive aluminum members such as used in electronic circuits and components are described. Also described are various sheet assemblies using patterned aluminum conductive elements as components of electric circuitry. The sheet assemblies can be used as backsheets for back contact photovoltaic cells or as antennas for RFID tags.

Abstract: A solid state drive (SSD) assembly and an assembly method for solid state drives, which does not require using screws. The assembly method includes aligning a printed circuit board with a first cover and a second cover, the first cover having pre-installed standoffs on an inner surface thereof. The printed circuit board and the second cover respectively having a first set of through-holes, and the first set of through-holes correspond to the standoffs. The assembly method further includes placing the printed circuit board between the first and second covers, thereby exposing an end portion of each of the standoffs in the through-holes of the second cover, and deforming the end portion of each of the standoffs about the through-holes, thereby fastening the first and second covers with one another.