Abstract: A smooth layer of a metal is electroplated onto a microrough electrically conducting substrate by immersing the substrate and a counterelectrode in an electroplating bath of the metal to be electroplated and passing a modulated reversing electric current between the electrodes. The current contains pulses that are cathodic with respect to said substrate and pulses that are anodic with respect to said substrate. The cathodic pulses have a duty cycle less than about 50% and said anodic pulses have a duty cycle greater than about 50%, the charge transfer ratio of the cathodic pulses to the anodic pulses is greater than one, and the frequency of said pulses ranges from about 10 Hertz to about 5000 Hertz.

Abstract: A process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer having a thickness of less than or equal to about 500 Angstroms. The ultra-thin seed layer is then enhanced by depositing additional metal thereon to provide an enhanced seed layer. The enhanced seed layer has a thickness at all points on sidewalls of substantially all recessed features distributed within the workpiece that is equal to or greater than about 10% of the nominal seed layer thickness over an exteriorly disposed surface of the workpiece.

Abstract: A process for fabricating a nanofilament field emission device in which a via in a dielectric layer is self-aligned to gate metal via structure located on top of the dielectric layer. By the use of a hard mask layer located on top of the gate metal layer, inert to the etch chemistry for the gate metal layer, and in which a via is formed by the pattern from etched nuclear tracks in a trackable material, a via is formed by the hard mask will eliminate any erosion of the gate metal layer during the dielectric via etch. Also, the hard mask layer will protect the gate metal layer while the gate structure is etched back from the edge of the dielectric via, if such is desired. This method provides more tolerance for the electroplating of a nanofilament in the dielectric via and sharpening of the nanofilament.

Abstract: A method for plating gold to a plurality of bond leads on a substrate is disclosed. The method first extends a plating line from a plating loop on the edge of the substrate to a bond area in the center portion of the substrate to electrically connect the plurality of bond leads in series. The plating line further extends to connect to the plating loop after connecting the plurality of bond leads together. Then, electricity is applied to the plurality of bond leads via the plating loop and the plating line thereby plates gold to the plurality of bond leads. Finally, a bonding tool is used to cut off and remove the plating line when the bonding tool is provided to bond the plurality of bond leads to a die that is attached to the substrate, whereby the residual plating line remaining on the substrate does not affect the performance of the semiconductor chip.

Abstract: Novel arrays of nanowires made of semi-metallic Bismuth (Bi) is disclosed made by unique electrodeposition techniques. Because of the unusual electronic properties of the semi-metallic Bi and the nanowire geometry, strong finite size effects in transport properties are achieved. In addition, very large positive magnetoresistance, 300% at low temperatures and 70% at room temperature, with quasilinear field dependence have been attained.

Abstract: An electrochemical deposition and testing system consisting of individually addressable electrode arrays, a fully automated deposition head, and a parallel screening apparatus is described. The system is capable of synthesizing and screening millions of new compositions at an unprecedented rate.

Abstract: An electroplating system (30) and process makes electrical current density across a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that electrical current density modifier portions (364) on structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.

Abstract: An apparatus and method is disclosed; both of which use electrochemistry to selectively grow and remove hard oxide coatings on metals, and capacitive double layers on non-metals and semiconductors in order to predict and control the rate of surface abrasion during planarization of the surface of such materials.

Abstract: A method for forming a metallization layer (30). A first layer (14) is formed outwardly from a semiconductor substrate (10). Contact vias (16) are formed through the first layer (14) to the semiconductor substrate (10). A second layer (20) is formed outwardly from the first layer (14). Portions of the second layer (20) are selectively removed such that the remaining portion of the second layer (20) defines the layout of the metallization layer (30) and the contact vias (16). The first and second layers (14) and (20) are electroplated by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the layers in a solution containing metal ions. The voltage and surface potentials are selected such that the metal ions are deposited on the remaining portions of the second layer (20). Further, metal ions deposited on the first layer (14) during a positive duty cycle are removed from the first layer (14) during a negative duty cycle.

Abstract: An improved fill of high aspect ratio trenches by copper is obtained by first sputtering a thin nucleating film of copper deposited by physical vapor deposition, then depositing a thin seed layer of copper by chemical vapor deposition, and then completing the fill by electroplating. Stress migration of the fill is improved if the copper deposition is preceded by the deposition by CVD of a layer of titanium nitride either alone or preceded and/or followed by the deposition of tantalum by an ionized PVD source.

Abstract: Simultaneous non-contact plating and planarizing of copper interconnections in semiconductor wafer manufacturing is performed by providing relative motion between a bipolar electrode and a metallized surface of a semiconductor wafer without necessary physical contact with the wafer or direct electrical connection thereto.

Abstract: The present invention provides a method of forming a thin film of zinc oxide on a conductive substrate by electrodeposition from an aqueous solution, which is capable of preventing film deposition on the back surface of the substrate. More specifically, a film deposition-preventing electrode for preventing film deposition on the back surface of the substrate is provided in an aqueous solution containing nitrate ions, and a current is supplied in such a manner that a potential relationship of "a counter electrode>the substrate>the film deposition-preventing electrode" is obtained. This method can be applied to a process for preparing a solar cell, thereby improving short circuit current density, photoelectric conversion efficiency, production yield and durability of the solar cell.

Abstract: Plating of metal interconnections in semiconductor wafer manufacturing is performed by providing relative motion between a bipolar electrode assembly a single metallized surface of a semiconductor wafer without necessary physical contact with the wafer or direct electrical connection thereto.

Abstract: The present invention aims to provide a highly reliable semiconductor element with high performance, and a fabrication method for such highly reliable semiconductor with excellent mass producibility. The photovoltaic elements comprise an electric conductor, semiconductor regions and a transparent conductor layer, which are sequentially formed on a substrate. The shunt resistance in the semiconductor element is rendered in the range from 1.times.10.sup.3 .OMEGA.cm.sup.2 to 1.times.10.sup.6 .OMEGA.cm.sup.2 by performing a forming treatment and a short circuit passivation treatment after forming the transparent conductor layer, and then selectively covering with insulation the defective portions with a cationic or anionic electrodeposited resin, or performing a forming treatment, after forming the semiconductor layers, then selectively covering with insulation the defective portions with a cationic or anionic electrodeposited resin, and then forming the transparent conductor layer.

Abstract: The non-uniformity of electroplating on wafers is due to the appreciable resistance of the thin seed layer and edge effects. Mathematical analysis of the current distribution during wafer electroplating reveals that the ratio between the resistance of the thin deposited seed layer and the resistance of the electrolyte and the electrochemical reaction determines the uniformity of the electroplated layer. Uniform plating is critical-in-wafer metallization for the subsequent step of chemical mechanical polishing of the wafer. Based on the analysis, methods to improve the uniformity of metal electroplating over the entire wafer include increasing the resistance of the electrolyte, increasing the distance between the wafer and the anode, increasing the thickness of the seed layer, increasing the ionic resistance of a porous separator placed between the wafer and the anode, placement of a rotating distributor in front of the wafer, and establishing contacts at the center of the wafer.

Abstract: The present invention relates to a bipolar electrochemical process for toposelective electrodeposition of a substance on a substrate comprising (a) placing the substrate and at least one of the substance and a source of the substance into an environment capable of conducting electricity and containing electrodes; (b) aligning the substrate on which the substance is to be deposited with respect to the electrodes such that the electrodes are not in contact with the substrate and the substance will be deposited in a predetermined location on the substrate when an electric field is applied; and (c) applying a voltage to the electrodes to create an electric field of a sufficient strength between the electrodes and for a time sufficient to deposit the substance on the substrate at the predetermined location in substantial alignment with the electric field.

Abstract: Methods of electroplating solder bumps of uniform height on integrated circuit substrates include the steps of drawing plating current through an integrated circuit wafer by electrically shorting an integrated circuit's ground, power and signal pads together using an ultra-thin plating base layer (e.g., <0.075 .mu.m thick) and then using a backside wafer contact to draw electroplating current along parallel paths which extend through the ground and signal pads and into the substrate. The ground pads are preferably electrically coupled to the substrate at substrate contact regions (e.g., N + or P + diffusion regions) and the signal pads are preferably electrically coupled to the substrate through active semiconductor devices (e.g., FETs, BJTs, . . . ) to which the signal pads are attached. Plating current is preferably drawn in parallel through an integrated circuit's active semiconductor devices and substrate contact regions.

Abstract: The present invention provides plating solutions, particularly metal plating solutions, designed to provide uniform coatings on substrates and to provide substantially defect free filling of small features, e.g., micron scale features and smaller, formed on substrates with none or low supporting electrolyte, i.e., which include no acid, low acid, no base, or no conducting salts, and/or high metal ion, e.g., copper, concentration. Additionally, the plating solutions may contain small amounts of additives which enhance the plated film quality and performance by serving as brighteners, levelers, surfactants, grain refiners, stress reducers, etc.

Abstract: Process and apparatus controlling the cross-sectional flow distribution within a flowing stream such as a copper flux in an electrolytic copper deposition process. The flow distribution is controlled by a baffle comprised of two plates overlying one another, each having a set of openings, wherein the openings in the two plates generally correspond to one another but are slightly offset therefrom or varied in size in a non-uniform way along the radius of the plates such as to effect a modification of the uniformity or non-uniformity of the velocity flow rates across the cross section of the flowing stream in which the baffle is interposed.

Abstract: Erosion of high density metallization areas associated with conventional damascene-CMP processing is avoided and greater planarity achieved by selectively increasing the metal overburden layer thickness at high density metallization regions. Embodiments include initially filling recesses formed in the substrate surface with a metal forming a blanket or overburden layer of the metal thereon. Regions of the blanket or overburden layer overlying regions of high density metallization are selectively electroplated to a greater thickness. The surface is then planarized by CMP, with the selectively increased thickness areas of the overburden layer compensating for greater erosion rates thereat during CMP, thereby resulting in greater planarity of the polished surface.

Abstract: Workpieces, such as semiconductor wafers, are electroplated with improved thickness uniformity by providing a diffuser member intermediate the cathode and anode of a fountain-type electroplating apparatus. The diffuser or member has a pattern of openings specifically designed to prevent channeling and/or selective directing of electrolyte towards the workpiece. In one embodiment, the diffuser member comprises a spiral-shaped pattern of openings originating at the center of the diffuser member and extending to the periphery thereof.

Abstract: A semiconductor plating bowl which includes a shield on a consumable anode. The shield is preferably made from a dielectric material, such as a plastic. The shield is placed in the area upon which flowing plating fluid would otherwise impinge upon the processing workpiece. The shield has the surprising benefit of reducing the amount of organic additives consumed in the plating process. This is believed to occur because films that otherwise may form on the anode are not disrupted by the flow of plating liquids thereover.

Abstract: A method of removing a seed layer 30 from areas over an insulting layer 20 where metal lines and pads will not be formed so that electroplated metal 50 can be chemical-mechanical polished without metal residue problems 151 and dishing problems. A key step of the invention is the patterning of the seed layer 30 to remove areas 40 of seed layer 30 that are not near the trenches 24. The method is as follows. An insulating layer 20 is formed having a plurality of trenches 24. A seed layer 30 is formed over the insulating layer 24. The seed layer 30 is comprised of a trench seed layer 30B and a top seed layer 30A on the top surface of the first insulating layer. We pattern the top seed layer 30A by removing selected portions of the top seed layer 30A to form a seed layer "lip" 30C around the trenches 24 so that the remaining seed layer 30B 30C electrically connects the trench seed layers 30B in the plurality of trenches 24. Metal is plated on the trench seed layer 30B filling the trenches 24.

Abstract: A method for forming a transmission line arrangement providing control of signal losses through the use of conductor cross-sectional surface area-increasing and skin effect-considered bulbous additions to the rectangular conductor cross-sectional shape frequently used in semiconductor device transmission line conductors. The achieved transmission line is especially suited for use in radio frequency integrated circuit assemblies where it also includes a backplane member, encounters signals in the microwave and millimeter wavelength range and involves conductor dimensions measured in micrometers. Control of transmission line characteristic impedance at, for example, 50 ohms is disclosed as is use of semiconductor device-compatible materials and loss comparisons data.

Abstract: A method which protects the region between a component and the substrate onto which the components is bonded using an electrically insulating fillet of photoresist. The fillet protects the regions from subsequent plating with metal and therefore shorting the plated conductors which run down the sides of the component and onto the substrate.

Abstract: A process for fabricating a nanofilament field emission device. The process enables the formation of high aspect ratio, electroplated nanofilament structure devices for field emission displays wherein a via is formed in a dielectric layer and is self-aligned to a via in the gate metal structure on top of the dielectric layer. The desired diameter of the via in the dielectric layer is on the order of 50-200 nm, with an aspect ratio of 5-10. In one embodiment, after forming the via in the dielectric layer, the gate metal is passivated, after which a plating enhancement layer is deposited in the bottom of the via, where necessary. The nanofilament is then electroplated in the via, followed by removal of the gate passification layer, etch back of the dielectric, and sharpening of the nanofilament. A hard mask layer may be deposited on top of the gate metal and removed following electroplating of the nanofilament.

Abstract: A method and device for the electrolytic formation of a deposit on a group of electrodes of an electrolysis support. The support has a plurality of electrodes. Electric charges are selectively deposited on chosen electrodes. The support is placed in the presence of an electrolyte to produce the deposit on the chosen electrodes by electrolysis. The electric charges deposited on the electrodes provide an electrolysis current for each chosen electrode. The formed device may be used as a biological sensor.

Abstract: An electroplating system includes a standard electroplating apparatus using an acid copper bath with an additive for leveling. The additive is chosen to have molecules of a size that is about the size of the features to be filled by the electroplating process. The relatively large size of these additive molecules tends to hinder the mass transfer of the additive molecules into the features. Consequently, the additive molecules are preferentially absorbed by the surface of the plating surface relative to the inner surfaces of the features. Accordingly, the electroplating process tends to fill the features relatively quickly compared to the other parts of the target surface so that all of the surface area of the target is equivalent in height. Because little or no additive molecules are within the features, the features tend to be filled without the voids often produced using conventional systems.

Abstract: An apparatus and method for customizing electrode contact placement on a semiconductor wafer while depositing and/or removing a material on a semiconductor wafer. The present invention is a adapter having at least one opening through which at least one electrode contacts the semiconductor wafer. The adapter may be designed to have multiple openings at specified locations on the adapter, thus allowing multiple electrode contacts with the semiconductor wafer at pre-specified locations. A conductive sheet may couple with the adapter to carry an electrical current from an electrical conductor to the electrode contacts placed within the openings of the adapter.

Abstract: The invention relates to a process for the production of an electro-chemical deposit (8-1, . . . , 8-4) with the aid of a substrate (2) having connection pieces (4-1, . . . , 4-5), said pieces being used as electrodes, the deposit taking place on the surface of a removable support (6) and which can be subsequently separated from the substrate on areas of said surface in electrical contact with the pieces of the substrate.

Abstract: Methods used in semiconductor electroplating systems, such as for plating copper, onto a semiconductor wafer or other semiconductor workpiece. The methods apply to patterned metal layers plated onto a seed layer which is partially protected by an overlying photoresist or other coating. The methods employ an electrode assembly which has a boot which seals about a contact face of the electrode. The sealing is performed by engaging the seal against photoresist to prevent corrosion of the seal layer. The area enclosed by the sealing includes a via which is surrounded by the seal. The electrode contact extends through the via to provide electrical contact with the metallic seed layer. Plating of copper or other metal proceeds at exposed seed layer areas.

Abstract: A first pattern of bumps and a second pattern of bumps are formed on a substrate (10) with bumps (14,15). During a transfer process, only the bumps (14) of the first pattern of bumps are transferred to pad extensions (20) of a device (17). The bumps (15) of the second pattern of bumps are not affected by this process and can be later transferred to a second device.

Abstract: A selective copper deposition method, comprising the steps of: forming barrier metal patterns on a wafer; and depositing copper only on the barrier metal patterns by electrochemistry, by which high pure copper film patterns can be formed simultaneously with deposition of copper, with ease.

Abstract: A semiconductor workpiece holder used in electroplating systems for plating metal layers onto a semiconductor workpieces, and is of particular advantage in connection with plating copper onto semiconductor materials. The workpiece holder includes electrode assemblies which have a contact part which connects to a distal end of an electrode shaft and bears against the workpiece and conducts current therebetween. The contact part is preferably made from a corrosion resistant material, such as platinum. The electrode assembly also preferably includes a dielectric layer which covers the distal end of the electrode shaft and seals against the contact part to prevent plating liquid from corroding the joint between these parts.

Abstract: A semiconductor workpiece holder for use in processing a semiconductor workpiece includes a workpiece support operatively mounted to support a workpiece in position for processing. A finger assembly is operatively mounted upon the workpiece support and includes a finger tip. The finger assembly is movable between an engaged position in which the finger tip is engaged against the workpiece, and a disengaged position in which the finger tip is moved away from the workpiece. Preferably, at least one electrode forms part of the finger assembly and includes an electrode contact for contacting a surface of said workpiece. At least one protective sheath covers at least some of the electrode contact. According to one aspect of the invention, a sheathed electrode having a sheathed electrode tip is positioned against a semiconductor workpiece surface in a manner engaging the workpiece surface with said sheathed electrode tip.

Abstract: Methods of treating wafers for analyzing defects present therein comprise providing wafers having front side surfaces comprising defective portions and a back side surfaces opposite thereto; and decorating the defective portion of the front side of the wafer with copper.

Abstract: High aspect ratio openings in excess of 3, such as trenches, via holes or contact holes, in a dielectric layer are voidlessly filled employing a pulse or forward-reverse pulse electroplating technique to deposit copper or a copper-base alloy. A leveling agent is incorporated in the electroplating composition to ensure that the opening is filled substantially sequentially from the bottom upwardly.

Abstract: Copper or a copper alloy is electroplated to fill via/contact holes and/or trenches in a dielectric layer. A barrier layer is initially deposited on the dielectric layer lining the hole/trench. A thin conformal layer of copper or a copper alloy is sputter deposited on the barrier layer outside the hole/trench. Copper or a copper alloy is then electroplated on the conformal copper or copper alloy layer and filling the hole/trench. During electroplating, the barrier layer functions as a seed layer within the hole/trench while the sputter deposited conformal copper or copper alloy layer enhances the flow of electrons from the wafer edge inwardly to provide a favorable deposition rate.

Abstract: A method for electroplating a silicon substrate in manufacturing a semiconductive device is provided. Electroplating process chamber contacts or fingers used in positioning a silicon substrate or wafer during an electroplating process are plated with a metal layer to prevent oxidation of the contacts. Oxidation of the contacts may result in increased and varying resistance of the contacts and thus nonuniform plating of the silicon wafer and possibly even deplating of a seed layer. A 20 mA/cm.sup.2 current is applied to the contacts which are immersed in an electrolyte solution before loading a silicon wafer. A silicon wafer is then loaded into the electroplating process chamber containing the electrolyte solution. The preplating of the contacts enables the formation of a uniform metal layer on the silicon substrate. Additionally, voltage then may be applied to the contacts after unloading the silicon wafer to reduce oxidation.

Abstract: A fabrication method for a chip size semiconductor package includes the steps of bonding conductive wires on bonding pads formed on an upper surface of a semiconductor chip, putting the semiconductor chip including the bonded conductive wires in an electrolyzer containing an electrolytic solution in such a manner that one end of each of the conductive wires is exposed outside of the electrolytic solution, attaching a plating electrode to an inner wall of the electrolyzer, attaching a conductive plate to serve as a common electrode to the exposed one end of each of the conductive wires; and connecting the conductive plate and the outer wall of the electrolyzer to an electric current source.

Abstract: A transmission line arrangement providing control of signal losses through the use of conductor cross-sectional surface area-increasing and skin effect-considered bulbous additions to the rectangular conductor cross-sectional shape frequently used in semiconductor device transmission line conductors. The achieved transmission line is especially suited for use in radio frequency integrated circuit assemblies where it also includes a backplane member, encounters signals in the microwave and millimeter wavelength range and involves conductor dimensions measured in micrometers. Control of transmission line characteristic impedance at, for example, 50 ohms is disclosed as is use of semiconductor device-compatible materials and loss comparisons data.

Abstract: The invention relates to a method and an apparatus for forming bonding bumps on wafers (5) to be plated in an electroless process (not requiring an externally applied voltage). According to the method, the object to be plated is immersed in a vessel (2) containing a desired solution (10) of metal salts thermostatted at a desired temperature. According to the invention, the wafer (5) to be plated is fixed to a filler block (4) which has a volume essentially equal to the volume of the process vessel (2) to the end of reducing the required filling volume of the vessel (2), and said filler block (4) is moved in the vessel (2) for improving the mixing of the solution of metal salts contained therein.

Abstract: Methods of forming high-aspect ratio blind apertures and thereafter filling the apertures with a plating solution are disclosed. A layer of photosensitive material is pattern exposed to actinic radiation to define the apertures, and thereafter exposed to aqueous developer solution. The apertures are then rinsed with water and thereafter exposed to plating solution without drying the aperture of water or developer solution. This is contrary to conventional practice where photoresist layers are dried, and usually post-baked after the development step in order to improve dimensional integrity and reduce swelling of the photoresist material.

Abstract: A method for manufacturing a porous blue light emitting diode comprising the steps of preparing a silicon substrate having a back surface, applying a conducting layer on the back surface, annealing the substrate coated with the conducting layer in an inert gas atmosphere, applying an anti-corrosion layer on the conducting layer, immersing the anti-corrosion layer-applied substrate in a hydrofluoric acid aqueous solution with a concentration of about 5% by volume, applying a voltage to the resulting layers for eroding the anti-corrosion layer-applied substrate to form a porous layer having Si wires on a top surface of the substrate, and oxidizing the porous layer for making sizes of the Si wires small enough for emitting light having a peak occuring at a wavelength shorter than about 520 nm. This method offers a simple and feasible way to fabricate a porous blue light emitting diode.

Abstract: A sensor arrangement having a substrate of doped silicon with channels in a principal face, a selective means for detecting a material, the selective means covering the principal face without filling the channels, and a measuring instrument for registering a physical quantity dependent on the influence of a material is provided. A catalytic layer is particularly used as selective means and a temperature sensor is particularly used as measuring instrument. Alternatively, the sensor arrangement is fashioned as a capacitor having a porous cooperating electrode. The channels are preferably produced by electrochemical etching.

Abstract: A mask layer is formed on a conductive layer covering not only a central area assigned to integrated circuits but also a vacant peripheral area of a semiconductor wafer, and an electroplating system allows metallic miniature patterns to grow on the conductive layer over the vacant peripheral area as well as extremely small areas of the conductive layer over the central area so as to make current fluctuation negligible.

Abstract: According to a face-down-mounting semiconductor device wherein electrode pads on a semiconductor chip and lead terminals are electrically connected to each other by plating bonding, and a method of manufacturing the semiconductor device, a guide tool is placed on the surface of a semiconductor chip. The guide tool includes guide holes corresponding in position to electrode pads. Columnar lead terminals are inserted into the guide holes of the guide tool. In this state, the semiconductor chip is soaked in a plating solution, together with the guide tool, to execute plating bonding. Since, therefore, the lead terminals can be brought into reliable contact with the electrode pads, metal plating layers can be grown sufficiently between them, thereby improving in reliability of melting bonding.

Abstract: A method for forming a metallization layer (30). A first layer (14) is formed outwardly from a semiconductor substrate (10). Contact vias (16) are formed through the first layer (14) to the semiconductor substrate (10). A second layer (20) is formed outwardly from the first layer (14). Portions of the second layer (20) are selectively removed such that the remaining portion of the second layer (20) defines the layout of the metallization layer (30) and the contact vias (16). The first and second layers (14) and (20) are electroplated by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the layers in a solution containing metal ions. The voltage and surface potentials are selected such that the metal ions are deposited on the remaining portions of the second layer (20). Further, metal ions deposited on the first layer (14) during a positive duty cycle are removed from the first layer (14) during a negative duty cycle.

Abstract: A technique for utilizing an electric field to initiate electroless deposition of a material to form layers and/or structures on a semiconductor wafer. The wafer is disposed between a positive electrode and a negative electrode and disposed so that its deposition surface faces the positive electrode. A conductive surface on the wafer is then subjected to an electroless copper deposition solution. When copper is the conductive material being deposited, positive copper ions in the solution are repelled by the positive electrode and attracted by the negatively charged wafer surface. Once physical contact is made, the copper ions dissipate their charges by accepting electrons from the conductive surface, thereby forming copper atoms on the surface. The deposited copper have the catalytic properties so that when a reductant in the solution is absorbed at the copper sites and then oxidized, additional electrons are released into the conductive surface.

Abstract: In an SOI substrate having a base substrate, an insulating film and a semiconductor active layer, a potential difference is given between the base substrate and an etching solution or among the base substrate, the semiconductor active layer and the etching solution to form a uniform depletion layer on the active layer side from the interface between the insulating film and the active layer. The semiconductor active layer is uniformly thinned down by etching using a solution or by the combination of chemical or electro-chemical surface and etching with the resultant reaction product. In this case, the individual electrodes are provided with seal members to prevent the base substrate electrode and the active layer electrode from contacting the etching solution or the reaction solution due to the etching using the etching solution or the chemical reaction using the reaction solution.