Abstract: A method of providing a semiconductor device with an inorganic electrically insulative layer, the device having exposed semiconductor surfaces and electrically conductive metal end terminations, in which the device is reacted with phosphoric acid to form a phosphate on the exposed surfaces of the semiconductor but not on the metal end terminations, and in which the device is thereafter barrel plated in a conventional electrical barrel plating process and the plating is provided only on the end terminations because the phosphate is not electrically conductive.

Abstract: A method for providing a flexible lead for a microelectronic device. A lead such as nickel or a nickel alloy is provided in elongated strips on a base material such as copper, which in turn overlies a dielectric sheet. The base material is etched from beneath bond regions of the lead material strips and a cover layer of a bondable material such as gold selectively provided around the lead material strips. The lead material strips act as plating mandrels, and allow rapid deposition of the cover material. A detachment area may be provided in each lead so that the leads may be detached and displaced within a bonding window in the dielectric sheet for attachment to chip contacts.

Abstract: A photoelectrochemical method and apparatus are disclosed for fabricating electronic circuits. An electroplating solution is applied to the surface of a reverse biased p-type semiconductor material, such as NiO. The solution-covered NiO surface is illuminated with a light beam directed by computer aided design data to photoelectrochemically deposit a seed layer of metal in an electronic circuit pattern. The seed layer may be thickened by further deposition in a plating bath to form metallic circuit traces on the NiO. If desired, the metallic circuitry may be transferred from the NiO to an alternate substrate having a low dielectric constant. The porosity of the NiO surface can be adjusted to optimize the metallic circuit adhesion for image retention or ease of transfer. The metallic traces may also be treated to reduce adhesion of subsequently deposited metal that can be transferred readily.

Abstract: Disclosed is a method of producing an integrated circuit package, wherein portions of the package are electroplated by getting a direct electrical connection with each of lead pins joined to a package substrate. The electrical connection is obtained by force-fitting each of the lead pins in corresponding one of openings formed in a plating jig made of an electrically conductive material for thereby bringing a side surface of each of the lead pins in contact with the jig. The portions of the package are electroplated under the condition where each of the lead pins is held in conduction. After the electroplating, each of the lead pins is separated from the jig through movement in the direction differing from an axial direction of each of the lead pins. Various jigs used for carrying out the above method are also disclosed.

Abstract: A method is provided for creating gated filament structures for a field emission display. A multi-layer structure is provided that includes a substrate, an insulating layer, a metal gate layer positioned on a top surface of the insulating layer and a gate encapsulation layer positioned on a top surface of the metal gate layer. A plurality of gates are provided and define a plurality of apertures on the top of the insulating layer. A plurality of spacers are formed in the apertures at their edges on the top surface of the insulating layer. The spacers are used as masks for etching the insulating layer and form a plurality of pores in the insulating layer. The pores are plated with a filament material to create a plurality of filaments. The pores can be overplated to create the plurality of filaments. The filaments are vertically self-aligned in the pores.

Abstract: An array of electrodes for use in a flat panel display includes a plurality of electron emitters formed of polycrystalline or single crystalline silicon which has been selectively etched to form pores in the emitters. The electrode array is then electroplated in a methane plasma to deposit a carbon compound such as silicon carbide on the surfaces of the emitters and in the pores of the emitters. Each emitter has a generally flat electron emitting surface which facilitates a longer life for the electrode array, the porous structure of the emitters increasing the electron emission efficiency of the emitters in relatively low electric fields. The electrode array can be integral with a support substrate by anisotropically etching the substrate to form the emitters. A layered interconnect structure can be formed on a surface of the silicon substrate for providing the interconnect structure for the electrode array.

Abstract: The present invention relates generally to a new structure and method for capped copper electrical interconnects. More particularly, the invention encompasses a novel structure in which one or more of the copper electrical interconnects within a semiconductor substrate are capped to obtain a robust electrical interconnect structure. A method for obtaining such capped copper electrical interconnect structure is also disclosed. These capped interconnects can be a single layer or multi-layer structures. Similarly, the interconnect structure that is being capped can itself be composed of single or multi-layered material.

Abstract: A method for use with semiconductor devices (47) that have leads (49) electroplated with a solderable metal (53) includes exposing the solderable metal (53) to an elevated temperature sufficient to flow or melt the solderable metal (53). In a preferred embodiment, the solderable metal (53) is exposed to the elevated temperature before the leads (49) are severed from the leadframe (48).

Abstract: An apparatus and a method for electroplating pin grid array (PGA) packaging modules by utilizing a compressible member and an electrically conductive foil for providing electrical connections to the pins such that all the critical areas of the pins, the wire bond pads, the seal band and the die cavity are electroplated simultaneously through the connection to the pins.

Abstract: A method for stopping a polish planarization wherein an etch-stop layer (13, 21, 31) is formed. The etch-stop layer (13, 21, 31) may be formed on a substrate (11) or on a conductive layer (12). The etch-stop layer (13, 21, 31) includes a metal and a grit material (17, 25, 35) such as a diamond powder. The etch-stop layer (13, 21, 31) serves as a stop to a mechanical polishing apparatus. The mechanical polishing apparatus removes a planarization layer (14, 22, 33) by polishing, but is unable to remove the etch-stop layer (13, 21, 31) because the etch-stop layer is able to withstand a polishing action of the mechanical polishing apparatus. The etch-stop layer (13, 21, 31) provides protection for the metal from mechanical damage during polish planarization and allows formation of a planar surface.

Abstract: The invention is a method for making a metal containing article, comprising the steps of: providing a layer of a porous ground in a selected area; exposing selected regions of the layer of porous ground to light, thereby metallizing the selected regions; repeating the foregoing steps a selected number of times to produce a selected number of layers; and selectively modifying the metallized regions of the layers. The initial metallization can be by electroless or semiconductor photo deposition plating. The subsequent modification of the metallized regions can be by electroless plating, electroplating or sintering. It is also possible, in some instances, to forego the second phase modification, the initial phase having provided the desired parameters. In a third preferred embodiment, the invention is a method using an initial metallization phase effected by exposure of a metal salt, such as a metal halide, to light, thereby inducing activation of the halide.

Abstract: A first pair electrodes consisting of an anode to which a plurality of wiring lines to be anodized are connected and a cathode that is opposed to the anode, and a second pair electrodes for collecting impurities in a forming solution are immersed in a forming solution. A voltage is applied to the plurality of wiring lines in such a manner that at least one of the plurality of wiring lines receives the voltage for a different period than the other wiring lines.

Abstract: A tool and process for electroetching metal films or layers on a substrate employs a linear electrode and a linear jet of electrolyte squirted from the electrode. The electrode is slowly scanned over the film by a drive mechanism. The current is preferably intermittent. In one embodiment a single wafer surface (substrate) is inverted and the jet is scanned underneath. In another embodiment wafers are held vertically on opposite sides of a holder and two linear electrodes, oriented horizontally and on opposite sides of the holder, are scanned vertically upward at a rate such that the metal layers are completely removed in one pass. The process is especially adapted for fabricating C4 solder balls with triple seed layers of Ti-W (titanium-tungsten alloy) on a substrate, phased Cr-Cu consisting of 50% chromium (Cr) and 50% copper (Cu), and substantially pure Cu. Solder alloys are through-mask electrodeposited on the Cu layer. The seed layers conduct the plating current.

Abstract: An apparatus (10) for electrolytic plating of a substrate (44) includes a tank (14) in which a shaft (30) is centrally mounted for rotation about a first axis (28). The shaft carries an arm (40), on the distal end (112) of which is rotatably mounted a fixture wheel (44). The substrate to be plated is carried on the fixture wheel, which rides on an annular track (50) formed on the bottom of the tank around the shaft. A plurality of spaced pins (52) projecting upwardly from the track engage with a plurality of spaced recesses (56) formed about the perimeter (54) of the wheel, so that the wheel rotates about a second axis (64) while revolving around the first axis. The fixture carries a plurality of electrical contact members (46) that contact the substrate. Each contact member is separately supplied with current from a multichannel power supply (22).

Abstract: A ceramic substrate is provided with filled via holes for electrical or thermal feedthrough to or from an electronic device, each via hole having at least one dimension from about 4 to about 50 mils. The via holes are filled with copper, silver or gold for high conductivity and the filling is without visible voids at a magnification of 1000 diameters. The filling is preferably hermetic and is achieved by first electrodepositing metal into the holes and extending therefrom as dumbbell shaped plugs and then heating the substrate to the melting point of the metal so that metal from the dumbbell ends enters the connecting portion within the via hole to seal any aperture therein.

Abstract: The invention uses transferable solder bump connection techniques in combination with a disposable test board to test and burn-in "as received" (i.e., untested) dies. Using transferable solder bumps, a die is first attached to the top of a disposable test board. The test board can be designed to allow 100% functional testing of the die as well as burn-in. Dies that successfully complete the test and burn-in process are considered to be "known good dies." Next, heat is applied to remove the known good die from the test board. A property of the invention is that solder bumps transfer with the die such that it can be used immediately in a flip-chip configuration and affixed to a MCM or other circuit board.

Abstract: A semiconductor product plating apparatus includes housings having a first mask portion for masking both the surfaces of a resin package of a semiconductor device and a second mask portion for masking the peripheral portion of a lead frame, when clamping a semiconductor product from both surface sides of the lead frame, and hollow portions surrounding outer leads between the semiconductor device and the peripheral portion of the lead frame. Electrolytic solution supply slits and electrolytic solution drainage slits are formed in the housings so as to communicate with the hollow portions. The apparatus also includes electrodes formed on portions of the inner wall surfaces of the hollow portions. The first mask portion has a tapered side surface which widens toward the end. The electrolytic solution supply slits have opening portions formed in a direction to cross the proximal end portions of the outer leads and communicating with the side surface of the first mask portion.

Abstract: An apparatus plates metal bumps of uniform height on one surface of a semiconductor wafer (32). A plating tank (12) contains the plating solution. The plating solution is filtered (16) and pumped (14) through an inlet (22) to an anode plate (24) within plating cell (20). The anode plate has a solid center area to block direct in-line passage of the plating solution, and concentric rings of openings closer to its perimeter to pass the plating solution. The distance between the inlet and the anode plate is adjustable with supports to create a uniform flow of the plating solution to the surface of the semiconductor wafer for uniform plating of the array of metal bumps (30). The plating cell contains an adjustable sidewall extension (26) to set the proper distance between the anode plate and the semiconductor wafer.

Abstract: An integrated circuit chip having solder bumps thereon may be tested using a temporary substrate having substrate pads corresponding to locations of the input/output pads on the chip and having a sacrificial conductor layer on the temporary substrate pads. The solder bumps are placed adjacent the corresponding sacrificial metal layer and heated to form an electrical and mechanical connection between the chip and the temporary substrate. The chip is then tested and/or burned-in on the temporary substrate. After testing/burn-in, the sacrificial metal layer is dissolved into the solder bumps by heating. The integrated circuit chip, including a solder bump having the dissolved sacrificial metal layer therein, may be easily removed from the temporary substrate. Solder bumps may also be formed on the temporary substrate and transferred to unbumped chips.

Abstract: A process and apparatus for advanced semiconductor applications which involves the selective electrodeposition of metal on a semiconductor wafer is described. The present invention has significant economic and performance advantages over the current state of the art. It addresses problems associated with cleanliness (a major issue with sub-micron processing), metal thickness uniformity, step coverage and environmental concerns.A metal with better device performance capabilities compared to the standard aluminum is also employed. The hardware allows the selective deposition to occur without allowing the electrolyte to contact the rear of the wafer or the electrodes contacting the front wafer surface. A virtual anode improves the primary current distribution improving the thickness uniformity while allowing optimization of other film parameters with the remaining deposition variables.

Abstract: A procedure for producing printed circuit boards with pads for insertion of SMDs. A copper lined base plate is provided with a positive photoprotective layer with a coating thickness lesser or equal to the depth of the pads to be built up for the connection of SMD components. The positive photoprotective layer is exposed using a primary film with a window mask corresponding to the desired pad arrangement, and the exposed base plate is developed in a developing bath such that the photoprotective layer is removed in the area of the exposed windows, exposing open copper areas there. The base plate developed in this way is exposed with a secondary film with a mask for the strip conductors, whereby the strip conductors are modeled as opaque areas.

Abstract: In a semiconductor device having multi-layer lead conductors, lead conductors of each layer and through connections are generated by electro chemical plating process. A flat and smooth surface is provided for each layer on which lead conductor base patterns are formed. Plating lead conductors on a layer and plating through connections are executed in a separate process. And, in these platings, electrolytic current is so controlled that the growth of plating is always from the base of the plating.

Abstract: A new metallization is described which is a composite of subsequent metal layers beginning with a layer of titanium and having in an ascending order the following composition: Ti--TiPd--Cu--Ni--Au. TiPd is an alloy of titanium and palladium containing from 0.3 to 14 weight percent Pd, by the weight of the alloy. The TiPd alloy is etchable in an aqueous HF solution containing from 0.5 to 2.0 and higher, preferably from 0.5 to 1.2 weight percent HF. The use of the TiPd alloy avoids the occurrence of Pd residues remaining after the etching of Ti layer and lift-off (rejection etching) of Pd layer in a prior art Ti--Pd--Cu--Ni--Au metallization. Ti and TiPd layers are present in a thickness ranging from 100 to 300 nm and from 50 to 300 nm, respectively, and in a total minimum thickness needed to maintain bonding characteristics of the metallization.

Abstract: A lightweight corrosivity sensor is provided which is thin enough to be edded between the layers of a composite structure or placed on a surface beneath a coating. It comprises a thin non-conductive base and two electrically isolated conductive elements fixed to the surface thereof. Each conductive element comprises a bus bar and a plurality of strips extending from the bus bar and interdigitated with the strips of the other conductive element. The corrosivity sensor is connectable to a current measuring means for measuring the current across the two conductive elements as an indicator of the presence of a corrosive environment. A masking method of manufacturing such a sensor is also provided.

Abstract: A graphite path is formed along the surface of a diamond plate, preferably a CVD diamond plate, by means of a laser or ion-implantation induced conductivity. The path advantageously can be the surface of a sidewall of a via hole drilled by the laser through the plate or a path running along a side surface of the plate from top to bottom opposed major surfaces of the plate. The graphite path is metallized, as by electroplating or electroless plating. In this way, for example, an electrically conducting connection can be made between a metallized backplane located on the bottom surface of the plate and a wire-bonding pad located on the top surface of the plate.

Abstract: Processes for fabricating electrochemical interconnections between semiconductor chip pads and substrate pads. First, pads on a substrate are electrically shorted by depositing a film of conductive metal, conductive bumps are created on the substrate pads, and the pads on the substrate are aligned with pads on a semiconductor chip. Then, by electrochemically depositing metal to the bumps, electrical interconnections are formed between the semiconductor chips pads and the substrate pads. Finally, the film of conductive metal is removed to eliminate the electrical shorting. The resulting electrochemical interconnections are highly reliable and have high tensile strengths.

Abstract: Highly conformal layers of either titanium, Ti, titanium nitride, TiN, or titanium oxide, TiO.sub.x, are formed on exposed surfaces of silicon substrates by first forming a very thin chemical vapor deposition (CVD) layer of either doped polysilicon or a chosen metallic silicide, such as titanium silicide, tungsten silicide, tantalum silicide, or molybdenum silicide on the exposed silicon surfaces and any masking material remaining thereon. Thereafter, the layered structure is transferred to an electroplating bath wherein a layer of titanium is plated on the surfaces of the metallic silicide film using either an aqueous electroplating solution, a non-aqueous solution or a molten salt solution. Then, the structure is transferred to either an anneal furnace or to a rapid thermal processor (RTP) and heated to a predetermined elevated temperature for a predetermined time in the presence of nitrogen, using either nitrogen gas, N.sub.2, or ammonia, NH.sub.

Abstract: A nickel plug (31) filling an aperture in an insulating layer (30), such as polyimide, separating two metallization levels of copper wires (28, 25) is formed by an electroless process in a plating bath (solution) containing ions of hypophosphite and of nickel. In preparation for this electroless process, the copper wires (28, 25) are first plated with a nickel layer (29) by a pseudo-electroless process-that is, a process in which the copper wires (28, 25) are located in contact with an underlying extended chromium layer (14) that is placed in electrical contact (including intimate physical contact) with an auxiliary metallic member (41) that contains nickel, while both the copper wires (28, 25), the chromium layer (14), and at least a portion of the external metallic layer (41) are immersed in a plating solution likewise containing ions of hypophosphite and of nickel.

Abstract: A process and apparatus for advanced semiconductor applications which involves the selective electrodeposition of metal on a semiconductor wafer is described. The present invention has significant economic and performance advantages over the current state of the art. It addresses problems associated with cleanliness (a major issue with sub-micron processing) , metal thickness uniformity, step coverage and environmental concerns.A metal with better device performance capabilities compared to the standard aluminum is also employed. The hardware allows the selective deposition to occur without allowing the electrolyte to contact the rear of the wafer or the electrodes contacting the front wafer surface. A virtual anode improves the primary current distribution improving the thickness uniformity while allowing optimization of other film parameters with the remaining deposition variables.

Abstract: A contact member for thermocompression bonding in integrated circuit packaging has on a conductor end a uniform texture deformable layer with a hardness value in the range of that of soft gold which is approximately 90 on the Knoop scale and with a rough surface morphology having ridges with approximately 1 micrometer modulation frequency and a depth between ridges of from 1/4 to 1/2 that of the average integrated circuit pad. The deformable layer is produced by plating gold in a strong electronegative plating bath within a range of 0.03 to 0.05 mA/sq.mm. current density. Plating apparatus, for plating different areas, with different electronegative conditions, with separate independently powered anodes, is provided.

Abstract: A method for manufacturing a pin grid array type semiconductor device package including a substrate having a principle surface and a bottom surface opposing the principal surface, a plurality of patterned metallized conductors formed in the substrate or on the principal surface of the substrate so as to be electrically connected to a semiconductor device chip to be located on the principal surface. A plurality of metallized pads are formed on the bottom surface and electrically connected to the patterned metallized conductors. A metal film is deposited so as to cover the bottom surface including the metallized pads, and a lead pin is soldered on the metal film above each metallized pad by a solder material. The lead pin is electroplated by applying a voltage to the metal film.

Abstract: Selective electrolytic deposition on either conductive or non-conductive bodies is provided by forming a layer of a metal which forms a plating-preventing compound on the surface of the body to be plated, and selectively interdiffusing a plating-enabling metal into the surface of that compound-forming metal in those locations where plating is desired and electroplating the body. The interdiffusion may be done before or after the plating-preventing compound has formed on the surface of the compound-forming layer. During the electroplating, the electroplating metal deposits only in those locations where the plating-enabling metal has interdiffused with the compound-forming metal. At the end of the process, the compound-forming metal may be removed in those locations where it is not covered by the electroplated metal to provide a plurality of separate plated conductors.

Abstract: A method for forming a plurality of solder bumps on an electronic component substrate utilizes a transfer plate to electrodeposit solder deposits and subsequently reflow the deposits onto the substrate. The plate comprises discrete pad electrodes formed of a ceramic material that is suitably electrically conductive to permit electroplating of the solder alloy, but is not wet by the molten solder to permit reflow onto the substrate. A preferred electrode material is an indium oxide compound. The solder deposits are plated onto the electrodes, and the transfer plate is superposed on the substrate such that the bumps rest upon bond pads on the substrate. The assembly is heated and cooled to melt and resolidify the solder alloy, whereupon the solder bonds to the substrate pads to form the bumps.

Abstract: A semiconductor crystal wafer is fixed between two electrolyte-filled cells so that the front surface and rear surface thereof are respectively in contact with an electrolyte. A respective electrode is located in the electrolyte, a DC voltage being applied between these electrodes so that the semiconductor-to-electrolyte contact of the one cell is polarized in the conducting direction and the other is polarized in the non-conducting direction. A current flow through the semiconductor crystal body is enabled in that the inhibiting surface of the semiconductor crystal is illuminated and charge carriers are generated as a result thereof. On the basis of the selection of suitable electrolytes and the intensity of illumination, high current density is possible even given high-impedance semiconductor crystal wafers as well as semiconductor crystal bodies having doping steps or pn junctions. The method is particularly simple in many semiconductor processing and analyses methods.

Abstract: A p-type ZnSe bulk or film crystal of good quality has not been produced so far, although various improved methods based on MOCVD or MBE methods have been tried. Prior art required high pressure, high temperature or high vacuum to grow a p-type ZnSe crystal. This invention grows p-type ZnSe by an electrochemical deposition method. A zinc anode and a low-resistivity n-type ZnSe singlecrystalline substrate are immersed into a solution including zinc ions, selenium ions and acceptor ions. Direct current is sent from the zinc anode to the n-type ZnSe singlecrystalline substrate cathode. Selenium ions and zinc ions are attracted to the n-type ZnSe cathode. They are reduced and are deposited on the n-type ZnSe cathode. Deposited ZnSe film is a p-type semiconductor. A ZnSe semiconductor with a pn-junction is obtained.

Abstract: A masked, conformal electrodeposition process for copper metallization of integrated circuits. The process is considerably less complex than other metallization processes utilizing electrodeposition, and provides excellent step coverage for sub-micron contact openings. Full-step coverage has been obtained with the process for contact openings as small as 0.5 microns in diameter. The process begins with the blanket sputter or LPCVD deposition of a thin conductive barrier layer of a material such as titanium nitride, titanium-tungsten or nitrided titanium-tungsten. A photoresist reverse image of the maskwork that normally would be used to etch the metallization pattern on the circuitry is created on the wafer on top of the barrier layer. As an option, the reverse image of the desired metallization pattern may be created by etching a dielectric material layer such as silicon dioxide or silicon nitride, using a photoresist reverse image as a template.

Abstract: In an integrated circuit, gold interconnect metal lines are electroplated onto plating (Pd) and barrier (TiW) layers, using patterned photoresist. The photoresist is stripped and the plating layer portions thus exposed are etched to expose field areas of the barrier layer. Next, sidewall spacers are formed along each side of the interconnect lines. The field areas of the barrier layer are then etched to isolate the gold interconnect lines. The spacers offset the amount of undercut due to isotropic etching of the TiW barrier metal layer. After etching, the sidewall spacers serve to preserve the as-deposited profile of the gold interconnect lines against breadloafing in a subsequent annealing step.

Abstract: A plating rack for use in electroplating at least one substrate includes a rack body onto which the substrate may be placed; a metal ring connected to the rack body so as to surround a substrate placed on the rack body; and bistable, single-tipped cam assemblies for holding a placed substrate in place and for making electrical contact between the metal ring and the substrate.