Abstract: Solar cells are produced using a method for producing solar cells, wherein silicon containing vitreous substrates is provided, wherein each substrate is provided with an electrically conductive material on at least one side thereof. In the method, at least a portion of each substrate is successively transported through an electrolytic solution that is present in an electrolytic bath, and the electrically conductive material as the cathode is connected during the transport of the substrates through the electrolytic bath for the purpose of electrodepositing material from the electrolytic solution onto the electrically conductive material during said transport, wherein the substrates are suspended from a conveyor element during transport and extend in the transport direction.

Abstract: A mechanism is provided for forming a nanodevice. A reservoir is filled with a conductive fluid, and a membrane is formed to separate the reservoir in the nanodevice. The membrane includes an electrode layer having a tunneling junction formed therein. The membrane is formed to have a nanopore formed through one or more other layers of the membrane such that the nanopore is aligned with the tunneling junction of the electrode layer. The tunneling junction of the electrode layer is narrowed to a narrowed size by electroplating or electroless deposition. When a voltage is applied to the electrode layer, a tunneling current is generated by a base in the tunneling junction to be measured as a current signature for distinguishing the base. When an organic coating is formed on an inside surface of the tunneling junction, transient bonds are formed between the electrode layer and the base.

Abstract: A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same or different chambers. Also, bottom coverage may be thinned or eliminated by ICP resputtering in one chamber and SIP in another. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering. In another chamber an array of auxiliary magnets positioned along sidewalls of a magnetron sputter reactor on a side towards the wafer from the target.

Abstract: Processes and systems for electrolytically processing a microfeature workpiece with a first processing fluid and a counter electrode are described. Microfeature workpieces are electrolytically processed using a first processing fluid, a counter electrode, a second processing fluid, and an anion permeable barrier layer. The anion permeable barrier layer separates the first processing fluid from the second processing fluid while allowing certain anionic species to transfer between the two fluids. Some of the described processes produce deposits over repeated plating cycles that exhibit resistivity values within desired ranges.

Abstract: Approaches for formation of a circuit via which electrically connects a first thin film metallization layer a second thin film metallization layer are described. Via formation involves the use of an anodization barrier and/or supplemental pad disposed in a via connection region prior to anodization of the first metallization layer. The material used to form the barrier is substantially impermeable to the anodization solution during anodization, and disrupts the formation of oxide between the electrically conducting layer and the barrier. The supplemental pad is non-anodizable, and is covered by the barrier to substantially prevent current flow through the pad during anodization. Following anodization, the barrier is removed. If the supplemental pad is sufficiently conductive, it can be left on the first metallization layer after removal of the barrier.

Abstract: Microelectronic packages may be formed using the co-deposition of carbon nanotubes. The carbon nanotubes may be functionalized to have an appropriate charge so they can be combined with other materials to give suitable properties. The other materials that are co-deposited may include metals, ceramics, and polymers. The electronic package components may be formed including thermal interface materials, vias, trenches, capacitors, memories, substrates, and substrate cores, as a few examples.

Abstract: An electronic fuse structure including an Mx level comprising an Mx metal, and an Mx+1 level above the Mx level, the Mx+1 level including an Mx+1 metal and a via electrically connecting the Mx metal to the Mx+1 metal in a vertical orientation, where the Mx+1 metal comprises a thick portion and a thin portion, and where the Mx metal, the Mx+1 metal, and the via are substantially filled with a conductive material.

Abstract: A copper electroplating method including dipping a substrate in a copper electroplating solution, the substrate including a seed layer; and forming a copper electroplating layer on the seed layer, wherein the copper electroplating solution includes water, a copper supply source, an electrolytic material, and a first additive, the first additive includes a compound represented by Formula 1, below:

Abstract: A method of forming patterned metallization by electrodeposition under illumination without external voltage supply on a photovoltaic structure or on n-type region of a transistor/junction.

Abstract: Certain embodiments herein relate to a method of electroplating copper into damascene features using a low copper concentration electrolyte having less than about 10 g/L copper ions and about 2-15 g/L acid. Using the low copper electrolyte produces a relatively high overpotential on the plating substrate surface, allowing for a slow plating process with few fill defects. The low copper electrolyte may have a relatively high cloud point.

Abstract: There is provided a method of manufacturing a wiring substrate. The method includes: (a) forming a first resist layer having first openings therein on a first surface of a support plate, forming first plated films in the first openings by an electrolytic plating method, and removing the first resist layer; (b) forming a second resist layer having second openings therein on the first surface of the support plate, forming second plated films in the second openings by an electrolytic plating method, and removing the second resist layer; (c) forming a wiring layer and an insulating layer such that the wiring layer is electrically connected to the first and second plated films; and (d) removing the support plate to expose the first and second plated films.

Abstract: A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material.

Abstract: A method and composition for metallizing a via feature in a semiconductor integrated circuit device substrate, using a leveler compound which is a dipyridyl compound.

Abstract: A method and apparatus for selectively controlling deposition rate of conductive material during an electroplating process. Dopants are predominantly incorporated into a conductive seed layer on field regions of a substrate prior to filling openings in the field regions by electroplating. A substrate is positioned in one or more processing chambers, and barrier and conductive seed layers formed. A dopant precursor is provided to the chamber and ionized, with or without voltage bias. The dopant predominantly incorporates into the conductive seed layer on the field regions. Electrical conductivity of the conductive seed layer on the field regions is reduced relative to that of the conductive seed layer in the openings, resulting in low initial deposition rate of metal on the field regions during electroplating, and little or no void formation in the metal deposited in the openings.

Abstract: A single-crystal substrate is placed on a supporting table while maintaining crystalline orientation of the single-crystal substrate. The single-crystal substrate has contacting regions on a periphery of an upper surface of the single-crystal substrate. Linear contacting surfaces of contacting pins are placed in contact with the contacting regions of the single-crystal substrate placed on the supporting table. Longitudinal directions on the contacting surfaces of all the contacting pins are not parallel to intersecting lines of the upper surface of the single-crystal substrate and cleaved surfaces of the single-crystal substrate.

Abstract: A metal covered polyimide composite comprising a tie-coat layer and a metal seed layer formed on a surface of a polyimide film by electroless plating or a drying method is provided. A copper layer or a copper alloy layer is formed thereon by electroplating. The copper plated layer or copper alloy plated layer includes three layers to one layer of the copper layer or copper alloy layer. The metal covered polyimide composite effectively prevents peeling in a non-adhesive flexible laminate (especially a two-layer flexible laminate), and more particularly, effectively inhibits peeling from the interface of a copper layer and tin plating. A method of producing the composite and apparatus for producing the composite are also provided.

Abstract: An electrode for forming an electrochemical cell with a substrate and a method of forming said electrode. The electrode comprises a carrier provided with an insulating layer which is patterned at a front side. Conducting material in an electrode layer is applied in the cavities of the patterned insulating layer and in contact with the carrier. A connection layer is applied at the backside of the carrier and in contact with the carrier. The periphery of the electrode is covered by the insulating material.

Abstract: A method for plating metal to a solar cell is disclosed. The method includes plating a metal layer only on the surface of solar cell without plating metal along the solar cell edges by conducting a first current in a first direction in an electroplating bath, ejecting metal from the metal layer by conducting a second current in a second direction and plating additional metal to the metal layer by conducting a third current in the first direction. The first, second and third current can be alternated. Subsequent to an electroplating process, an ultrasonic cleaning process is performed on the solar cell to remove any excess plated metal along the surface and edges of the solar cell.

Abstract: One embodiment is a method for void-free metallic electrofilling inside openings, said method includes: providing a substrate with at least one opening, the substrate includes an electrically conductive surface, including inside the at least one opening; immersing the substrate in an electrolyte contained in an ECD cell, the ECD cell includes at least one anode and a cathode, the cathode includes at least a portion of the conductive surface, the electrolyte includes plating metallic ions and at least one inhibitor additive, said metallic ions and at least one inhibitor additive having concentrations; providing electrolyte agitation across the substrate surface; and applying electroplating current density to the substrate; wherein the agitation, the concentrations, and the electroplating current density are such to produce void-free metallic electrofilling of the at least one opening, and wherein a height of electrodeposited surface bumps, or transition steps or humps, or transition spikes, is less than 140 nm

Abstract: An aqueous, acid bath for the electrolytic deposition of copper contains at least one copper ion source, at least one acid ion source, at least one brightener compound, and at least one leveler compound, and generates a very uniform copper deposit in particular in blind micro vias (BMVs) and trenches. The leveler compound is selected from among synthetically produced non-functionalized peptides, synthetically produced functionalized peptides, and synthetically produced functionalized amino acids.

Abstract: Disclosed herein are a nickel plating solution and a method for forming a nickel layer on an external electrode of a chip component by using the nickel plating solution, the nickel plating solution including: a nickel ion; a chloride ion; and a pH buffer, wherein the pH buffer is used by mixing an inorganic acid, and an organic acid and a salt thereof, so that the damage to a body of the chip component can be reduced by containing organic acid and a salt thereof in the nickel plating solution for forming the nickel plating layer on the external electrode of the chip component having a body formed of a material including ferrite or manganese oxide.

Abstract: A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material.

Abstract: A metal underlayer is selectively plated on semiconductor wafers immediately followed by plating copper on the metal underlayer using a low internal stress copper plating bath. Additional metallization may be done to build up the metal layers using conventional metal plating baths and methods to form current tracks. Formation of metal silicides is avoided. Good adhesion of the metals to the semiconductors is achieved. The metalized semiconductors may be used in the manufacture of photovoltaic devices.

Abstract: A substantially uniform layer of a metal is electroplated onto a work piece having a seed layer thereon. This is accomplished by employing a “high resistance ionic current source,” which solves the terminal problem by placing a highly resistive membrane (e.g., a microporous ceramic or fretted glass element) in close proximity to the wafer, thereby swamping the system's resistance. The membrane thereby approximates a constant current source. By keeping the wafer close to the membrane surface, the ionic resistance from the top of the membrane to the surface is much less than the ionic path resistance to the wafer edge, substantially compensating for the sheet resistance in the thin metal film and directing additional current over the center and middle of the wafer.

Abstract: An apparatus and process are described that allow electroplating to fill sub-micron, high aspect ratio semiconductor substrate features using a non-copper/pre-electroplating layer on at least upper portions of side walls of the features, thereby providing reliable bottom up accumulation of the electroplating fill material in the feature. This apparatus and process eliminates feature filling material voids and enhances reliability of the electroplating in the diminishing size of features associated with future technology nodes of 22, 15, 11, and 8 nm. The presence of non-copper pre-electroplating material on the side walls allows the feature whose side walls, but not bottom surface, are lined with such pre-electroplating material (such as cobalt) to fill the feature using electroplated fill material accumulating from the bottom of the feature up to reliability and predictability and substantially void-free.

Abstract: A method for forming, on a conductive or semiconductor substrate, nanowires based on CuSCN, including the steps of: preparing an aqueous electrolytic solution from a Cu(II) salt having a concentration lower than 120 mM, a Cu(II) complexing agent from the aminocarboxylic acid family, and a thiocyanate salt, the solution having a pH ranging between 0.1 and 3; electrochemically depositing the aqueous electrolytic solution on the substrate.

Abstract: A method of forming interconnects for three dimensional integrated circuits comprises attaching a metal layer on a first carrier, attaching a first side of a packaging component on the metal layer, wherein the packaging component comprises a plurality of through vias. The method further comprises filling the plurality of through vias with a metal material using an electrochemical plating process, wherein the metal layer functions as an electrode for the electrochemical plating process, attaching a second carrier on a second side of the packaging component, detaching the first carrier from the packaging component, forming a photoresist layer on the metal layer, patterning the photoresist layer and detaching exposed portions of the metal layer.

Abstract: The present invention relates to an electrodeposition composition intended particularly for coating a semiconductor substrate in order to fabricate structures of the “through via” type for the production of interconnects in integrated circuits. According to the invention, the said solution comprises copper ions in a concentration of between 14 and 120 mM and ethylenediamine, the molar ratio between ethylenediamine and copper being between 1.80 and 2.03 and the pH of the electrodeposition solution being between 6.6 and 7.5. The present invention also relates to the use of the said electrodeposition solution for the deposition of a copper seed layer, and to the method for depositing a copper a seed layer with the aid of the electrodeposition solution according to the invention.

Abstract: The object of the present invention is a method of coating a surface of a substrate with copper by electroplating. According to the invention, this method comprises: a step during which the surface to be coated is brought into contact with an electroplating bath while the surface is not under electrical bias; a step of forming the coating during which the surface is biased; a step during which the surface is separated from the electroplating bath while it is under electrical bias; the aforementioned electroplating bath comprising, in solution in a solvent: a source of copper ions, with a concentration of between 0.4 and 40mM; and at least one copper complexing agent.

Abstract: Metal electroplating processes are used in pH sensitive applications to plate metal layers on semiconductors. The semiconductors may be used in the manufacture of photovoltaic devices and solar cells.

Abstract: A method for forming a defect marker on a thin film of a photovoltaic device by plating to detect pinholes and/or electrical shunts during device fabrication is disclosed. Also disclosed is a system for implementing such a method.

Abstract: Techniques disclosed herein a method and system for coating the interior surfaces of microscale hole features fabricated into the substantially planar surface of a substrate. Techniques include creating a separation or smoothing layer between a nucleation layer process and a metallization or gapfill process. The addition of such a separation layer avoids dissolving a seed layer and gapfill complications from remnant organic material. Techniques include adding a conformal copper smoothing layer step after applying a direct on-barrier nucleation layer. The smoothing layer adds a sufficient thickness so that the gapfill chemistry does not erode the nucleation layer. The smoothing layer can also provide a high-purity copper film that will not detrimentally interact with the TSV gapfill chemistry. This smoothing layer can also provide a surface with consistent roughness to allow uniform adhesion of the organic additives in the TSV gapfill chemistry to create a filling profile that is void-free.

Abstract: A method of fluid processing a semiconductor workpiece, including disposing a workpiece holder with a housing capable of containing a fluid, the workpiece holder retaining the workpiece, providing an agitation system connected to the housing and comprising a member disposed within the housing adjacent the workpiece holder, and agitating the fluid by moving the member substantially parallel to a surface of the workpiece with a non-uniform oscillatory motion, the non-uniform oscillatory motion being a series of substantially continuous geometrically asymmetric oscillations wherein each consecutive oscillation of the series is geometrically asymmetric having at least two substantially continuous opposing strokes wherein reversal positions of each substantially continuous stroke of the substantially continuous asymmetric oscillation are disposed asymmetrically with respect to a center point of each immediately preceding substantially continuous stroke of the oscillation.

Abstract: A plating protocol is employed to control plating of metal onto a wafer comprising a conductive seed layer. Initially, the protocol employs cathodic protection as the wafer is immersed in the plating solution. In certain embodiments, the current density of the wafer is constant during immersion. In a specific example, potentiostatic control is employed to produce a current density in the range of about 1.5 to 20 mA/cm2. The immersion step is followed by a high current pulse step. During bottom up fill inside the features of the wafer, a constant current or a current with a micropulse may be used. This protocol may protect the seed from corrosion while enhancing nucleation during the initial stages of plating.

Abstract: The subject-matter of the present invention is a composition especially intended for filling, by the electroplating of copper, a cavity in a semiconductor substrate such as a “through-via” structure for the production of interconnects in three-dimensional integrated circuits. According to the invention, this composition comprises in solution in a solvent: copper ions in a concentration lying between 45 and 1500 mM; a complexing agent for the copper consisting of at least one compound chosen from aliphatic polyamines having 2 to 4 amino groups, preferably ethylenediamine, in a concentration lying between 45 and 3000 mM; the molar ratio between the copper and said complexing agent lying between 0.1 and 5; thiodiglycolic acid in a concentration lying between 1 and 500 mg/l; and optionally a buffer system, in particular ammonium sulfate, in a concentration lying between 0.1 and 3M.

Abstract: An apparatus for electroplating a layer of metal onto the surface of a wafer includes an ionically resistive ionically permeable element located in close proximity of the wafer and an auxiliary cathode located between the anode and the ionically resistive ionically permeable element. The ionically resistive ionically permeable element serves to modulate ionic current at the wafer surface. The auxiliary cathode is configured to shape the current distribution from the anode. The provided configuration effectively redistributes ionic current in the plating system allowing plating of uniform metal layers and mitigating the terminal effect.

Abstract: An electrodeposited nano-twins copper layer, a method of fabricating the same, and a substrate comprising the same are disclosed. According to the present invention, at least 50% in volume of the electrodeposited nano-twins copper layer comprises plural grains adjacent to each other, wherein the said grains are made of stacked twins, the angle of the stacking directions of the nano-twins between one grain and the neighboring grain is between 0 to 20 degrees. The electrodeposited nano-twins copper layer of the present invention is highly reliable with excellent electro-migration resistance, hardness, and Young's modulus. Its manufacturing method is also fully compatible to semiconductor process.

Abstract: Effective fillability and the uniformity electrodeposition of a copper electroplating solution is judged by determining the time-dependent potential change thereof at a cathode current density of 0.1-20 A/dm2. The potential change is determined at a working electrode rotation of 100-7500 rpm, and the fillability with the solution is judged from the curve profile. In an embodiment of the present invention, the fillability is judged by obtaining the potential change speed in the initial stage of electrolysis and the potential convergent point from the time-dependent potential change curve for a predetermined period of time after the start of the electrolysis.

Abstract: A piezoelectric actuator is formed by forming first and second electrodes on a substrate, and depositing a material on the substrate and between side surfaces of adjacent first and second electrodes to form a thin film sheet within which the first and the second electrodes extend from a first surface of the thin film sheet towards a second surface of the thin film sheet opposite the first surface. The second electrode is interdigitated in relation to the first electrode. The side surfaces of the first and the second electrodes are at least substantially perpendicular to the substrate. The thin film sheet is to physically deform in response to an electric field induced within the thin film sheet via application of a voltage across the first and the second electrodes.

Abstract: A method for manufacturing a semiconductor device includes providing a template having openings on upper surface, channels for receiving plating solution and connecting from the openings to lower surface of the template, and electrodes in positions corresponding to the channels on the lower surface and extending to the openings through the channels, positioning a substrate having circuits on upper surface of the substrate and through holes penetrating through the substrate and connected to circuit electrodes of the circuits such that the upper surface of the substrate faces downward, coupling the template and substrate such that the holes are positioned to correspond with the openings, supplying plating solution from the channels to the holes, and applying voltage between the circuit electrodes as cathodes and electrodes as anodes such that through-hole electrodes are formed in the holes and that the circuit electrodes are connected to the electrodes.

Abstract: A method for manufacturing semiconductor devices comprises: applying a dual pulse power to the semiconductor device during metal electroplating a part of the semiconductor device and applying ultrasonic energy to said semiconductor device during the metal electroplating.

Abstract: A method for metallizing a via feature in a semiconductor integrated circuit device substrate, wherein the semiconductor integrated circuit device substrate comprises a front surface, a back surface, and the via feature and wherein the via feature comprises an opening in the front surface of the substrate, a sidewall extending from the front surface of the substrate inward, and a bottom. The method comprises contacting the semiconductor integrated circuit device substrate with an electrolytic copper deposition chemistry comprising (a) a source of copper ions and (b) a leveler compound, wherein the leveler compound is a reaction product of a dipyridyl compound and an alkylating agent; and supplying electrical current to the electrolytic deposition chemistry to deposit copper metal onto the bottom and sidewall of the via feature, thereby yielding a copper filled via feature.

Abstract: Arrangements for plating a single surface of a thin foil are described. In one aspect, a metal foil is wrapped tightly at least partially around a plating solution drum. The drum is partially immersed in a plating solution such that the waterline of the metal plating solution is below a break point where the metallic foil strip begins to unwind from the plating solution drum. With this arrangement, one side of the metallic foil strip is exposed to the metal plating solution, while the opposing back side of the metallic foil strip does not come in substantial contact with the metal plating solution. In this manner, the exposed side of the foil is plated while the back surface of the foil is not plated. The drum may be rotated to convey the foil through the plating solution.

Abstract: The invention relates generally to electrodeposition apparatus and methods. When depositing films via electrodeposition, where the substrate has an inherent resistivity, for example, sheet resistance in a thin film, methods and apparatus of the invention are used to electrodeposit materials onto the substrate by forming a plurality of ohmic contacts to the substrate surface and thereby overcome the inherent resistance and electrodeposit uniform films. Methods and apparatus of the invention find particular use in solar cell fabrication.

Abstract: A method of automatic deposition profile targeting for electrochemically depositing copper with a position-dependent controllable plating tool including the steps of depositing copper on a patterned product wafer, measuring an actual thickness profile of the deposited copper and generating respective measurement data, feeding the measurement data to an advanced process control (APC) model and calculating individual corrections for plating parameters in the position-dependent controllable plating tool.

Abstract: A semiconductor substrate is anodized to be shaped into an optical lens. Prior to being anodized, the substrate is finished with an anode pattern on its bottom surface so as to be consolidated into a unitary structure in which the anode pattern is precisely reproduced on the substrate. The anodization utilizes an electrolytic solution which etches out oxidized portion as soon as it is formed as a result of the anodization, to thereby develop a porous layer in a pattern in match with the anode pattern. The anode pattern brings about an in-plane distribution of varying electric field intensity by which the porous layer develops into a shape complementary to a desired lens profile. Upon completion of the anodization, the semiconductor substrate is shaped into the lens by etching out the porous layer and the anode pattern from the substrate.

Abstract: A method of manufacturing a package carrier is provided. An insulation cover is provided. The insulation cover has an inner surface and an outer surface opposite to each other, a plurality of openings, and a containing space. A patterned metal layer is foamed on the outer surface of the insulation cover. A surface treatment layer is formed on the patterned metal layer. A heat dissipation element is formed in the containing space of the insulation cover and structurally connected to the insulation cover. A thermal-conductive layer is formed on a surface of the heat dissipation element, and a portion of the thermal-conductive layer is exposed by the openings of the insulation cover.

Abstract: Methods, electroplating solution, and apparatuses for electroplating copper into a surface of a partially fabricated semiconductor substrate are provided. Electroplating solutions include copper ions, suppressor additives, chloride ions, and alternative halide ions, which include bromide ions and/or iodide ions. The concentration of the alternative halide ions in the solution may be between about 0.25 ppm and 20 ppm. Addition of the alternative halide ions at certain concentrations improves suppression properties of the solution over a range of feature sizes without a need to change suppressors.

Abstract: A copper electroplating bath that includes an aqueous solution that comprises a copper salt and at least one acid and a container that comprises a copper salt in solid form, is disclosed. The container supplies copper ions to the aqueous solution to maintain the copper ion concentration of the aqueous solution at saturation levels while retaining the copper salt in solid form within the container.

Abstract: Apparatus and methods for uniform metal plating onto a semiconductor wafer, such as GaAs wafer, are disclosed. One such apparatus can include an anode and a showerhead body. The anode can include an anode post and a showerhead anode plate. The showerhead anode plate can include holes sized to dispense a particular plating solution, such as plating solution that includes gold, onto a wafer. The showerhead body can be coupled to the anode post and the showerhead anode plate. The showerhead body can be configured to create a seal sufficient to substantially prevent a reduction of pressure in the plating solution flowing from the anode post to holes of the showerhead anode plate.