Abstract: A semiconductor package device includes a first dielectric layer, a first interconnection layer, a second interconnection layer, and a second dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first interconnection layer is within the first dielectric layer. The second interconnection layer is on the second surface of the first dielectric layer and extends from the second surface of the first dielectric layer into the first dielectric layer to electrically connect to the first interconnection layer. The second dielectric layer covers the second surface and the lateral surface of the first dielectric layer and the second interconnection layer.

Abstract: A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, a molding layer and a sacrificial layer. The circuit layer includes conductive traces and conductive pads. The molding layer has an upper surface and a lower surface opposite to the upper surface, wherein the molding layer partially covers the conductive traces and the conductive pads, and first surfaces of the conductive traces and first surfaces of the conductive pads are exposed from the upper surface of the molding layer. The sacrificial layer covers the lower surface of the molding layer, second surfaces of the conductive pads.

Abstract: A multilayer printed circuit board having a stackup including an upper half of the stackup and a lower half of the stackup, the multilayer printed circuit board having a top exposed surface and a bottom exposed surface, a first trace and via structure, having one portion disposed on the top exposed surface and another portion disposed within the upper half of the stackup, a second trace and via structure, having one portion disposed on the top exposed surface and another portion disposed within the upper half of the stackup, and first electrical components and second electrical components disposed on the top exposed surface of the multilayer printed circuit board and associated, respectively, with the first trace and via structure and the second trace and via structure, wherein the first electrical components are mounted orthogonally with respect to the second electrical components.

Abstract: An extremely thin copper foil with a carrier is provided that can keep stable releasability even after being heated for a prolonged time at a high temperature of 350° C. or more. The extremely thin copper foil with a carrier includes a carrier composed of a glass or ceramic material; an intermediate layer provided on the carrier and composed of at least one metal selected from the group consisting of Cu, Ti, Al, Nb, Zr, Cr, W, Ta, Co, Ag, Ni, In, Sn, Zn, Ga, and Mo; a release layer provided on the intermediate layer and including a carbon sublayer and a metal oxide sublayer or containing metal oxide and carbon; and an extremely thin copper layer provided on the release layer.

Abstract: A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, a molding layer and a sacrificial layer. The circuit layer includes conductive traces and conductive pads. The molding layer has an upper surface and a lower surface opposite to the upper surface, wherein the molding layer partially covers the conductive traces and the conductive pads, and first surfaces of the conductive traces and first surfaces of the conductive pads are exposed from the upper surface of the molding layer. The sacrificial layer covers the lower surface of the molding layer, second surfaces of the conductive pads.

Abstract: A multilayer printed wiring board and a method of manufacturing the same are provided. A multilayer printed wiring board of the present embodiment includes: a core base material formed by laminating a first wiring layer and a first insulating layer in this order on an insulating substrate; and a built-up layer formed by laminating a second wiring layer and a second insulating layer in this order on the core base material. A primer layer is formed between the second wiring layer and the first insulating layer, the second wiring layer has a lower surface at least part of which is in contact with the primer layer, and the second wiring layer has an upper surface and a side surface on both of which a tin-plated layer and a silane coupling layer are formed in this order.

Abstract: The present invention concerns a metal or metal alloy deposition composition, particularly a copper or copper alloy deposition composition, for electrolytic deposition of a metal or metal alloy layer, particularly for electrolytic deposition of a copper or copper alloy layer, comprising at least one type of metal ions to be deposited, preferably copper ions, and at least one imidazole based plating compound. The present invention further concerns a method for preparation of the plating compound, the plating compound itself and its use in a metal or metal alloy deposition composition. The inventive metal or metal alloy deposition composition can be preferably used for filling recessed structures, in particular those having higher diameter to depth aspect ratios.

Abstract: A circuit board is manufactured by mounting a first circuit layer, mounting a conductive bump on the first circuit layer, covering the first circuit layer with a first dielectric layer which exposes the conductive bump, mounting a second dielectric layer on the first dielectric layer with a second dielectric layer opening that exposes the conductive bump, and finally, mounting a second circuit layer on the surface of the second dielectric layer and in the second dielectric layer opening. Since the surface roughness of the second dielectric layer and the second dielectric layer opening is low, it is unlikely to form nano voids between the second dielectric layer and the second circuit layer, and the second circuit layer may be attached to the second dielectric layer firmly, which is an advantage for fine line circuit disposal.

Abstract: Interconnect structures are provided. An interconnect structure includes a substrate; a first dielectric layer on the substrate and including an opening for a first interconnect layer extending to the substrate; a first metal layer having a first portion in the opening and a second portion in contact with the first portion and on a portion of the first dielectric layer adjacent to the opening; a second dielectric layer on the first dielectric layer and on the first metal layer, the second dielectric layer including a trench for a second interconnect layer, the trench exposing the second portion of the first metal layer; and a second metal layer in the trench, wherein the second portion of the first metal layer forms a lower portion of the second interconnect layer.

Abstract: A method for producing an electrical component is disclosed using a molybdenum adhesion layer, connecting a polyimide substrate to a copper seed layer and copper plated attachment.

Abstract: An electroplating bath for depositing a silver/tin alloy on a substrate. The electroplating bath comprises (a) a source of tin ions; (b) a source of silver ions; (c) an acid; (d) a first complexing agent; (e) a second complexing agent, wherein the second complexing agent is selected from the group consisting of allyl thioureas, aryl thioureas, and alkyl thioureas, and combinations thereof; and (f) optionally, a wetting agent, and (g) optionally, an antioxidant.

Abstract: An electronic device fabrication system may include, but is not limited to: a conductive material deposition device configured for deposition of a conductive material; at least one electronic device substrate configured to receive deposited conductive material; and at least one mask configured to selectively transmit the conductive material to the electronic device substrate, wherein the at least one mask configured to selectively transmit the conductive material to the electronic device substrate includes: at least a first side disposed at an angle relative to an adjacent second side.

Abstract: A conductor trace structure reducing insertion loss of circuit board, the circuit board laminates an outer layer circuit board, an inner layer circuit board and a glass fiber resin films which arranged between each board; before laminated process, the conductor traces of the inner layers had formed by etching of imaging transfer process and conductor traces had been roughed process for making the glass fiber resin films having good adhesive performance during laminating; before etching of imaging transfer process that forms the conductor traces of the outer layers or solder resist coat process or coating polymer materials, the conductor traces have been roughed process to make insulating resin layer of the solder resist coat or polymer materials to has better associativity; wherein a smooth trench is formed by physical or chemical process constructed on the roughed conductor traces surface to guide electric ions transmitted on these smooth trench surface to enhance electric ions transmission rate, resulting i

Abstract: A printed circuit board includes: a first insulating layer; and a heat radiating circuit pattern disposed on a first surface of the first insulating layer and having a pad and a via. The heat radiating circuit pattern includes: a first metal layer disposed on the first insulating layer; a graphite layer disposed on the first metal layer; and a second metal layer disposed on the graphite layer.

Abstract: The present disclosure is directed a process for the electrolytic polishing of a metallic substrate, including the steps of (i) providing an electrolyte in an electrolytic cell having at least one electrode, (ii) disposing a metallic substrate as an anode in the electrolytic cell, (iii) applying a current at a voltage of 270 to 315 V from a power source between the at least one electrode and the metallic substrate, and (iv) immersing the metallic substrate in the electrolyte, wherein the electrolyte includes at least one acid compound, at least one fluoride compound, and at least one complexing agent.

Abstract: A method for preparing a conductive circuit can begin with the preparation of a non-conductive substrate having a top surface and a bottom surface, and then utilizing a pulse laser to create a top circuit pattern upon the top surface, a bottom circuit pattern upon the bottom surface, and a through hole connecting the top circuit pattern with the bottom circuit pattern. Subsequently, a conductive circuit is formed upon the top circuit pattern and the bottom circuit pattern and inside the through hole, wherein the conductive circuit is restricted from being formed upon the top surface outside of the top isolation region and the bottom surface outside of the bottom isolation region.

Abstract: Provided herein is a method for measuring a concentration of a metal ion in an electrodeposition solution. The method of the present disclosure can substantially reduce the interference of organic additives and different electrode conditions on voltammetric metal ion concentration measurements.

Abstract: According to an embodiment, a flexible circuit board includes: a first substrate; a second substrate disposed on the first substrate and including an opening; a first conductive pattern part disposed on a bottom surface of the first substrate; a second conductive pattern part disposed on a top surface of the second substrate; a third conductive pattern part disposed between the first substrate and the second substrate; and an upper protective layer partially disposed on the second conductive pattern part and including a first open region, wherein the third conductive pattern part includes: a first inner lead pattern part disposed in the opening of the second substrate; and a first extension pattern part connected to the first inner lead pattern part, the second conductive pattern part includes: a second inner lead pattern part disposed in the first open region of the upper protective layer; and a second extension pattern part connected to the second inner lead pattern part, and a number of first inner lead pa

Abstract: This tin or tin alloy plating solution includes a soluble salt including at least a stannous salt (A), an acid selected from an organic acid and an inorganic acid or a salt thereof (B), a surfactant (C), benzalacetone (D), and a solvent (E), wherein the plating solution is used to form a pattern in which bump diameters are different from each other on a base material, an amount of the benzalacetone (D) is 0.05 g/L to 0.2 g/L, a mass ratio (C/D) of the surfactant (C) to the benzalacetone (D) is 10 to 200, and a mass ratio (E/D) of the solvent (E) to the benzalacetone (D) is 10 or more.

Abstract: In a described example, a method for passivating a copper structure includes: passivating a surface of the copper structure with a copper corrosion inhibitor layer; and depositing a protection overcoat layer with a thickness less than 35 ?m on a surface of the copper corrosion inhibitor layer.

Abstract: A method of preparing a non-conductive substrate to allow metal plating thereon. The method includes the steps of a) contacting the non-conductive substrate with a conditioner comprising a conditioning agent; b) applying a carbon-based dispersion to the conditioned substrate, wherein the carbon-based dispersion comprises carbon or graphite particles dispersed in a liquid solution; and c) etching the non-conductive substrate. The etching step is performed before the liquid carbon-based dispersion dries on the non-conductive substrate.

Abstract: A mechanical subtractive method of manufacturing a flexible circuitry layer may include mechanically removing at least a portion of a conductive mesh, wherein, following the mechanical removal, a remaining portion of the conductive mesh forms at least a portion of a circuitry trace comprising an electrode; forming an electrical connection between the electrode and a terminal of an interfacing component, wherein the interfacing component comprises a connector; and encasing at least a portion of the circuit trace with an insulative layer.

Abstract: To provide a semiconductor device 100 including a semiconductor element with a less warped chip. A semiconductor device manufacturing method include: bonding a rear surface of a chip having electrodes on both sides thereof to a front surface of a substrate; providing, to the front surface of the substrate to which the chip is bonded, a plating protective film having an opening at a position which is on the front surface of the chip and corresponds to an electrode at which plating is to be formed, after the bonding; plating the electrode of the chip after the providing; and removing the plating protective film from the substrate, after the plating.

Abstract: According to an embodiment, a substrate treatment apparatus includes a hair member including a noble metal, and a liquid chemical supply member to supply a liquid chemical. While a tip part of the hair member is contact with a predetermined surface of a metal, the liquid chemical is supplied onto the surface of the metal, and the metal is removed with etching.

Abstract: A method includes forming a metal-containing material layer over a substrate, patterning the metal-containing material layer, where the patterned material layer has an average roughness, and electrochemically treating the patterned metal-containing material layer to reduce the average roughness. The treatment may be implemented by exposing the patterned metal-containing material layer to an electrically conducting solution and applying a potential between the patterned material layer and a counter electrode exposed to the solution, such that the treating reduces the average roughness of the patterned material layer. The electrically conducting solution may include an ionic compound dissolved in water, alcohol, and/or a surfactant.

Abstract: A printed circuit board includes: an insulating layer having a via hole formed therein; a single layer metal pad disposed in the insulating layer and having a center portion that is exposed by the via hole, the center portion of the pad having a higher roughness than peripheral portions of the pad; and a via formed in the via hole and connected to the center portion of the pad.

Abstract: Provided is a ceramic substrate. The ceramic substrate includes a core layer, made of zirconia toughened alumina; and surface layers, symmetrically located on an upper and a lower surfaces of the core layer, made of Al2O3. The core layer has a chemical composition of 0 wt %<ZrO2?40 wt % and 60 wt %?Al2O3<100 wt %. A method for manufacturing the ceramic substrate and a power module including the ceramic substrate are also provided.

Abstract: A multilayer substrate includes a first metal plate forming a first coil; a second metal plate facing the first metal plate in a coil-winding axis direction and forming a second coil; a first insulating layer having therein the first metal plate; and a second insulating layer having therein the second metal plate. A metal foil is connected to the first metal plate through a plurality of via holes. An electronic component embedded in the first insulating layer is connected to a pattern formed on the metal foil.

Abstract: A circuit apparatus includes a first circuit feature upon a first insulator and a second circuit feature upon the first insulator. The first circuit feature includes a planarized surface and the second circuit feature includes an irregular surface. The first circuit feature and the second circuit feature may be formed from patterning a conductive sheet that is upon the first insulator. The conductive sheet includes an irregular surface and a planarized surface. Conductive sheet roughness is minimized in first regions thereof and is maintained in second regions thereof. Selectively planarizing portions of the conductive sheet allows for the utilization of lower cost rougher conductive sheets. The planarized surface allows for increased signal integrity and reduced insertion loss and the irregular surface allows for increased adhesion and enhancing reliability of the circuit apparatus.

Abstract: A substrate includes a substrate body, a flux coating portion which is coated with flux promoting solder fluidity on a surface of the substrate body, a conduction portion which is disposed on the surface of the substrate body to be separated from the flux coating portion and is conductive, and a silk portion which is disposed between the flux coating portion and the conduction portion on the surface of the substrate body and is provided by silk printing.

Abstract: A method includes etching a mandrel layer to form mandrel strips, and selectively depositing metal lines on sidewalls of the mandrel strips. During the selective deposition, top surfaces of the mandrel strips are masked by dielectric masks. The method further includes removing the mandrel layer and the dielectric masks, filling spaces between the metal lines with a dielectric material, forming via openings in the dielectric material, with top surfaces of the metal lines exposed to the via openings, and filling the via openings with a conductive material to form vias.

Abstract: The present invention relates to methods for fabricating a laterally-limited two-dimensional structure through template synthesis. The methods of the invention are useful in forming homogenous and heterogeneous layered materials. The invention also provides structures and devices formed by the method of the present invention and uses thereof.

Abstract: A method of forming a semiconductor package comprises forming one or more first vias in a first side of a substrate and attaching a first side of a first microelectronic element to the first side of the substrate. The first microelectronic element is electrically coupled to at least one of the one or more first vias. The method further comprise obtaining a second microelectronic element including one or more second vias in a first side of the second microelectronic element, and attaching a second side of the substrate to the first side of the second microelectronic element. The second microelectronic element is electrically coupled to at least one of the one or more first vias. Each of one or more connecting elements has a first end attached to a first side of the second microelectronic element and a second end extends beyond a second side of the first microelectronic element.

Abstract: In a semiconductor device, a thinly-molded portion covering a whole of a heat dissipating surface portion of a lead frame and a die pad space filled portion are integrally molded from a second mold resin, because of which adhesion between the thinly-molded portion and lead frame improves owing to the die pad space filled portion adhering to a side surface of the lead frame. Also, as the thinly-molded portion is partially thicker owing to the die pad space filled portion, strength of the thinly-molded portion increases, and a deficiency or cracking is unlikely to occur.

Abstract: A method of depositing coating onto both sides of a substrate is provided, which includes steps of upwardly sputtering one or more lower targets to deposit a sacrificial coating onto a second surface and downwardly sputtering one or more upper targets to deposit a first functional coating onto a first surface, washing the substrate with one or more washers to remove the sacrificial coating from the second surface while leaving intact the first functional coating on the first surface, and downwardly sputtering the one or more upper targets to deposit a second functional coating onto the second surface.

Abstract: A wiring board assembly (1) includes: a flexible printed wiring board (2) which includes at least an insulating substrate (5) including a through-hole (53), and wiring patterns (61) and (62) provided on the insulating substrate (5) and extending to peripheral edge portions (531n) and (532n) of the through-hole (53); a metal reinforcing plate (3) attached to the flexible printed wiring board (2) and facing the through-hole (53); and a solder connection portion (4) covering an inner wall surface (534) of the through-hole (53) and electrically connecting the wiring patterns (61) and (62) to the metal reinforcing plate (3).

Abstract: An ultra dense and ultra low power microhotplates using silica aerogel and method of making the same, comprising creating a sol-gel by impregnation of ethanol with functional colloidal alcogel particles is described. The technique further comprises forming tiny aerogel particles on the wafer and networking the particles together just by exposure to air during spin coating. The novelty of this technique is not limited to the processing of thin film and thick film silica aerogel.

Abstract: A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1.

Abstract: A microelectronic device is formed by providing a substrate having a recess at a top surface, and a liner layer formed over the top surface of the substrate, extending into the recess. A protective layer is formed over the liner layer, extending into the recess. A CMP process removes the protective layer and the liner layer from over the top surface of the substrate, leaving the protective layer and the liner layer in the recess. The protective layer is subsequently removed from the recess, leaving the liner layer in the recess. The substrate may include an interconnect region with a bond pad and a PO layer having an opening which forms the recess; the bond pad is exposed in the recess. The liner layer in the recess may be a metal liner suitable for a subsequently-formed wire bond or bump bond.

Abstract: The present invention relates to a method of manufacturing an optical device for a back light unit, and an optical device and an optical device array manufactured by the method, in which optical device chips constituting the optical device array are each laid the sides thereof on a printed circuit board in such a manner that light can be emitted from the optical device chips in a lateral direction, thus reducing the overall thickness of the back light unit.

Abstract: There is provided a method of manufacturing a semiconductor device, including forming a seed layer on a substrate by performing a cycle a predetermined number of times, the cycle including supplying a halogen-based first processing gas to the substrate; supplying a non-halogen-based second processing gas to the substrate; and supplying a hydrogen-containing gas to the substrate. Further, the method further includes forming a film on the seed layer by supplying a third processing gas to the substrate.

Abstract: A pattern-forming method for forming a conductive circuit pattern, the pattern-forming method including the steps of: preparing a pattern-forming composition composed of: Cu powder; solder particles for electrically coupling the Cu powder; a polymer resin; a deforming agent that is selected from among acrylate oligomer, polyglycols, glycerides, polypropylene glycol, dimethyl silicon, simethinecone, tributyl phosphare, and polymethylsiloxane, and that increases bonding force between the Cu powder and the solder particles; a curing agent; and a reductant; forming a circuit pattern by printing the pattern-forming composition on a substrate; heating the circuit pattern at a temperature effective to cure the pattern-forming composition and provide the conductive circuit pattern; and electrolytically plating a metal layer onto the conductive circuit pattern. A circuit pattern having superior conductivity is formed at low cost.

Abstract: The present invention relates to a composition for forming a conductive pattern, which is able to form a fine conductive pattern onto a variety of polymer resin products or resin layers by a very simple process, a method for forming the conductive pattern using the same, and a resin structure having the conductive pattern.

Abstract: Disclosed is an integrated circuit arrangement including a two sided circuit board, having a first surface and a second surface. A plurality of electrical conductors is incorporated as part of the two sided circuit board. An array of through holes extend through the first surface and the second surface, arranged in a pattern and are configured to provide a common electrical connection area, wherein the common electrical connection area is associated with a portion of a particular one of the plurality of electrical conductors.

Abstract: A method of forming a resist pattern including forming a first resist pattern on a substrate; applying a cross-linking composition so as to cover the first resist pattern; heating the covered first resist pattern and crosslinking an isocyanate group in the cross-linking composition with the first resist pattern; and developing the covered first resist pattern, wherein the cross-linking composition includes a blocked isocyanate compound having a protected isocyanate group.

Abstract: A first coil portion is formed in a first coil region of an upper surface of an insulating layer, and a second coil portion is formed on a lower surface of the insulating layer. A second terminal is formed at a position outside the first coil region. One or more intersection regions, in which a path, extending from an inner end of the first coil portion to the second terminal, intersects the first coil portion, are provided on the upper surface. The first coil portion is parted in each intersection region. A second lead portion passes between one portion and another portion of the first coil portion parted in said each intersection region and extends from the inner end of the first coil portion to the second terminal. The first coil portion and the second coil portion are connected together in parallel via through holes formed in the insulating layer.

Abstract: A carrier is disclosed, including: a main body having a first surface and a second surface opposing the first surface; a conductive part formed on the first surface of the main body; and a plurality of heat conductors that are not in contact with the conductive part and penetrate the main body to connect the first surface with the second surface. Therefore, heat generated by electronic elements can be effectively dissipated outside to improve the functionality and lifetime of electronic elements.

Abstract: A first resin layer (11) is provided with a first through hole (12), a conductive pattern (31, 41, 51) extends from a first surface of the first resin layer (11) to a second surface of the first resin layer (11) through the first through hole (12), and a second resin layer (21) is provided with a first protrusion (22) which fills at least a portion of the first through hole (12).

Abstract: An electrochemical biosensor includes a substrate, a plurality of layered active metal parts, a plurality of layered electrodes, a reaction confinement layer, an electrochemical reactive layer and a cover piece. The substrate is formed with through holes each of which is defined by an interior wall surface and penetrates top and bottom surfaces. Each of the layered active metal parts is formed at least upon a respective one of the interior wall surfaces. The layered electrodes are formed on the layered active metal parts. The reaction confinement layer confines a reactor space over a region where the through holes are formed. The electrochemical reactive layer is disposed in the reactor space and is electrically coupled to the layered electrodes.

Abstract: An ultra dense and ultra low power microhotplates using silica aerogel and method of making the same, comprising spin coating an aerogel layer followed by SiO2 as capping interlayer, and Nichrome (Ni80/Cr20) for heating element to increase the efficiency of metal oxide gas sensors. There may be multiple thin layers of aerogel separated by interlayers such as of SiO2.