Abstract: A method of manufacturing a space transformer includes providing a carrier substrate made for a chip package, forming an insulated layer disposed on the carrier substrate, and forming a conductive block. The carrier substrate is formed with elongated first and second wires. The first wire has an elongated contact which is longer than the width of the first wire. The insulated layer is formed with a hole corresponding in position to the elongated contact. The conductive block is formed with an elongated connecting column located in the hole and connected with the elongated contact, and a cylindrical contact pad exposed at the outside of the insulated layer, larger-sized than the elongated connecting column is connected with the elongated connecting column. As a result, the cylindrical contact pad has sufficient area and structural strength for contact with a probe needle.

Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same. The printed circuit board according to a preferred embodiment of the present invention includes a base substrate; a through via formed to penetrate through the base substrate; and circuit patterns formed on one side and the other side of the base substrate and formed to be thinner than an inner wall of the through via.

Abstract: Electroplating systems that include a plurality of electrodes, a power supply operably coupled to the plurality of electrodes, a platen for bearing a substrate on which metal features are to be formed, and an electrode support are disclosed. The electrode support may be configured for suspending the electrode assembly over an upper surface of the substrate disposed on the platen in spaced relation to and in alignment with the substrate or for supporting the electrode assembly in a stationary position over the substrate when the voltage is applied across the plurality of electrodes. The electrodes may be adjacent, mutually spaced and electrically isolated and connected in series so as to be oppositely polarized when the voltage is applied thereacross or may be connected so as to have alternating polarities when the voltage is applied thereacross.

Abstract: Method for continuously producing flexible copper clad laminates includes performing continuous ion implantation and/or plasma deposition on the surface of an organic macromolecular polymer film, and performing continuous copper plating. The bonding force between the copper film and the substrate in a two-layer flexible copper clad laminate produced by the method is much larger than that in a flexible copper clad laminate produced by a sputtering/plating method and equivalent to that in a flexible copper clad laminate produced by a coating method and a lamination method. Meanwhile the thickness of the copper film can be easily controlled to be less than 18 microns.

Abstract: Within a method for the determination of film-forming amines in liquids by adding a reacting agent with the amine to form a colored complex to be measured by photometric method for the reaction the pH of the liquid mixture is lowered by using hydrochloric acid.

Abstract: A method for electroless coating of substrates by applying an activating coat of polyelectrolyte or salt with a first aqueous composition; rinsing the activating coat such that the activating coat not being entirely removed; contacting and coating of the activated surfaces that have remained after rinsing with an aqueous composition in the form of a solution, emulsion or suspension, to form an organic secondary coat; and drying. The activating coat is a solution, emulsion or suspension containing a anionic polyelectrolyte or at least one anionic salt in solution in water. The aqueous composition forming the secondary coat has constituents which can be precipitated, deposited or salted out and which are anionically, zwitterionically, sterically or cationically stabilized. The dry film formed in the process, comprising the activating coat and the secondary coat, has a thickness of at least 1 ?m.

Abstract: The present invention relates to a method for preparing a supported metal catalyst for the selective hydrogenation of unsaturated hydrocarbons, characterized in that it comprises the following steps: a) electroplating a layer of nickel on a metallic support, and then b) electroplating a top layer of platinum and/or palladium. The present invention also relates to the supported metal catalyst obtained by this process, and the use thereof in hydrogenation reactions of unsaturated hydrocarbons, in particular for the selective hydrogenation of light olefins.

Abstract: Housings for electronic devices including adaptive plugs, and the use of adaptive plugs in methods of manufacturing housings. The housing may include an opening, and an adaptive plug releasably positioned within the opening. A method of forming a housing may include forming an opening within the housing, disposing a curable material within the opening of the housing, and curing the material to form an adaptive plug. The adaptive plug may be positioned within the opening of the housing. The method may also include performing at least one surface treatment on the housing. A method of protecting an edge of an opening in a housing may include providing the housing including the opening, forming an adaptive plug within the opening of the housing, and forming a barrier on the edge of the opening using the adaptive plug.

Abstract: The present invention relates to a galvanic process for filling through-holes with metals. The process is particularly suitable for filling through-holes of printed circuit boards with copper. The process comprises the following steps: (i) formation of a narrow part in the center of a through-hole by electroplating; and (ii) filling the through-hole obtained in step (i) with metal by electroplating.

Abstract: An embodiment device package includes a discrete device, a first connector on a bottom surface of the discrete device, and a second connector on a top surface of the discrete device. The first connector bonds the discrete device to a first package component, and the second connector bonds the discrete device to a second package component.

Abstract: A method for preparing graphene nanoplate (GNP) is provided and includes preparing expanded graphite (EG) and exfoliating, grinding, or cracking the expanded graphite to crack the EG induced by gas-phase-collision. A graphene nanoplate paste and a conductive coating layer formed of the graphene nanoplate paste are provided and are prepared by the method for preparing graphene nanoplate.

Abstract: A component built-in board, wherein at least two layers of a plurality of printed wiring bases are disposed on a rear surface side of an electronic component; the at least two layers of the printed wiring bases include a heat radiation-dedicated wiring pattern that is disposed above the rear surface of the electronic component; the heat radiation-dedicated wiring pattern is formed such that a heat radiation-dedicated wiring line and a signal-dedicated wiring line are continuous; a via includes a plurality of heat radiation-dedicated vias which connects the rear surface of the electronic component and the heat radiation-dedicated wiring pattern; and the heat radiation-dedicated wiring pattern is continuous from a place where connected to the heat radiation-dedicated via to be connected also to another via disposed at an outer peripheral side of the electronic component.

Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of manufacturing a PCB. Embodiments include depositing upon layers of laminate printed circuit traces and joining the layers of laminate. Embodiments also include drilling at least one via hole through the layers of laminate and placing in the via hole a via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a second metal having a conductivity lower than the conductivity of copper.

Abstract: A method for manufacturing a build-up substrate, the build-up substrate comprising an insulating layer and a wiring pattern layer stacked over a circuit substrate, said method comprising the steps of: (i) applying a photoactive metal oxide precursor material to one or both sides of the circuit substrate with a wiring pattern, and drying the applied photoactive metal oxide precursor material to form an insulating film; (ii) forming an opening for a via hole in the insulating film by exposure and development of the insulating film; (iii) applying a heat treatment to the insulating film to convert the insulating film into a metal oxide film, thereby forming a build-up insulating layer of the metal oxide film; and (iv) plating the build-up insulating layer to form via holes in the openings, forming a metal layer on the build-up insulating layer, and etching the metal layer to form a build-up wiring pattern; and (v) repeating the steps from (i) to (iv) at least one time.

Abstract: An electrolytic copper plating solution is provided which has an excellent via filling ability without using formaldehyde, which is harmful to the environment. An electrolytic copper plating solution which contains compounds which have an —X—S—Y— structure wherein X and Y are individually atoms selected from a group comprising hydrogen, carbon, sulfur, nitrogen, and oxygen atoms and X and Y can be the same only when they are carbon atoms and specific nitrogen-containing compounds. Good filled vias can be made without causing a worsening of the exterior appearance of the plating by using this electrolytic copper plating solution.

Abstract: Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.

Abstract: A method for manufacturing an embedded wiring board is provided. An activating insulation layer is formed. The activating insulation layer includes a plurality of catalyst particles, and covers a first wiring layer. An intaglio pattern and at least one blind via partially exposing the first wiring layer are formed on the activating insulation layer, in which some of the catalyst particles are activated and exposed in the intaglio pattern and the blind via. The activating insulation layer is dipped in a first chemical plating solution, and a solid conductive pillar is formed in the blind via through electroless plating. The activating insulation layer is dipped in a second chemical plating solution after the solid conductive pillar is formed, and a second wiring layer is formed in the intaglio pattern through the electroless plating. Components of the first chemical plating solution and the second chemical plating solution are different.

Abstract: A method of making an array of integral terminals on a circuit assembly. The method includes the steps of depositing at least a first liquid dielectric layer on the first surface of a first circuit member, imaged to include a plurality of first recesses corresponding to the array of integral terminals. The selected surfaces of the first recesses are processed to accept electro-less conductive plating deposition. Electro-lessly plating is applied to the selected surfaces of the first recesses to create a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. Electro-plating is applied to the electro-less plating to substantially first recesses with a conductive material. The steps of depositing, processing, electro-less plating, and electro-plating are repeated to form the integral terminals of a desired shape. The dielectric layers are removed to expose the terminals.

Abstract: A circuit substrate includes: a substrate; an insulating coating layered structure formed on the substrate, having top and bottom surfaces, and formed with a patterned recess that is indented inwardly from the top surface, that is disposed above the bottom surface, and that is defined by a recess-defining wall, the recess-defining wall having a bottom wall portion and a surrounding wall portion that extends upwardly from a periphery of the bottom wall portion; and a patterned metallic layered structure including an electroless plating metal layer formed on the bottom wall portion of the recess-defining wall.

Abstract: Provided is a method for manufacturing a surface acoustic wave apparatus that can reduce degradation of electric characteristics and also reduce the number of manufacturing processes. The method for manufacturing a surface acoustic wave apparatus includes the steps of: forming an IDT electrode on an upper surface of a piezoelectric substrate, forming a frame member surrounding a formation area in which the IDT electrode is formed on the piezoelectric substrate, and mounting a film-shaped lid member on the upper surface of the frame member so as to be joined to the frame member so that a protective cover, used for covering the formation area and for providing a tightly-closed space between it and the formation area, is formed.

Abstract: A thermal management circuit material comprises a thermally conductive metallic core substrate, metal oxide dielectric layers on both sides of the metallic core substrate, electrically conductive metal layers on the metal oxide metal oxide dielectric layers, and at least one through-hole via filled with an electrically conductive metal-containing core element connecting at least a portion of each of the electrically conductive metal layers, wherein the containing walls of the through-hole via are covered by a metal oxide dielectric layer connecting at least a portion of the metal oxide dielectric layers on opposite sides of the metallic core substrate. Also disclosed are methods of making such circuit materials, comprising forming metal oxide dielectric layers by oxidative conversion of a surface portion of the metallic core substrate. Articles having a heat-generating electronic device such as an HBLED mounted in the circuit material are also disclosed.

Abstract: Systems and methods for reducing overhang on electroplated surfaces of printed circuit boards are described. One such method includes applying a first resist layer on a substrate having a first copper layer, applying a first image to the first resist layer, developing the first resist layer in accordance with the first image, applying a second copper layer on the first copper layer, electroplating a first metallic layer on the second copper layer, removing the first resist layer, etching a portion of the first copper layer, removing the first metallic layer, depositing a third copper layer on a surface of the assembly, applying a second resist layer on the third copper layer, applying a second image to the second resist layer, developing the second resist layer in accordance with the second image, electroplating a preselected metal layer on the third copper layer, removing the second resist layer, and etching a portion of the third copper layer.

Abstract: A method for producing ceramic circuit boards from ceramic substrates having metal-filled vias. In order to be able to fill the vias by means of a single filling process, either a planar copper metallization is applied on one side to the ceramic substrate having vias by means of scren printing, or a copper film of 100-300 ?m is bonded on one side to the ceramic substrate having vias in a DCB/DBC process and the vias are filled from the ceramic side by means of an electrogalvanic process in a copper bath by the deposition of copper.

Abstract: A composition comprising a source of metal ions and at least one leveling agent obtainable by condensing at least one trialkanolamine of the general formula N(R1—OH)3 (Ia) and/or at least one dialkanolamine of the general formula R2—N(R1—OH)2 (Ib) to give a polyalkanolamine(II), wherein the R1 radicals are each independently selected from a divalent, linear or branched aliphatic hydrocarbon radical having from 2 to 6 carbon atoms, and the R2 radicals are each selected from hydrogen and linear or branched aliphatic, cycloaliphatic and aromatic hydrocarbon radicals having from 1 to 30 carbon atoms, or derivatives obtainable by alkoxylation, substitution or alkoxylation and substitution of said polyalkanolamine(II).

Abstract: A manufacturing method of a package carrier includes the following steps. Two base metal layers are bonded together. Two supporting layers are laminated onto the base metal layers respectively. Two release metal films are disposed on the supporting layers respectively. Each release metal film includes a first metal film and a second metal film separable from each other. Two first patterned metal layers are formed on the release metal films respectively. Each first patterned metal layer includes a pad pattern. Two dielectric layers are formed on the release metal films respectively and cover the corresponding first patterned metal layers. Each dielectric layer has a conductive via connecting to the corresponding pad pattern. Two second patterned metal layers are formed on the dielectric layers respectively. Each second patterned metal layer at least covers the conductive via. The base metal layers are separated from each other to form two independent package carriers.

Abstract: A circuit board upon which to mount an integrated circuit chip may include a first interconnect zone on the surface of the circuit board having first contacts with a first pitch, and a second interconnect zone, surrounding the first zone, having second contacts or traces with a second pitch that is smaller than the first pitch. The first contacts may have a design rule (DR) for direct chip attachment (DCA) to an integrated circuit chip. The first contacts may be formed by bonding a sacrificial substrate having the first contacts to a surface of the board; or by laser scribing trenches where the conductor will be plated to create the first contacts. Such a board allows DCA of smaller footprint processor chips for devices, such as tablet computers, cell phones, smart phones, and value phone devices.

Abstract: A manufacturing method of a package carrier includes the following steps. Firstly, two base metal layers are bonded together. Then, two supporting layers are laminated onto the base metal layers respectively. Next, two release metal films are disposed on the supporting layers respectively, wherein each of the release metal films includes a first metal film and a second metal film separable from each other. Next, two patterned metal layers are formed on the release metal films respectively, wherein each of the patterned metal layers is suitable for carrying and electrically connected to a chip. Then, the base metal layers are separated from each other to form two package carriers independent from each other. A package carrier formed by the manufacturing method described above is also provided.

Abstract: A surface of an object to be plated is subjected to a treatment for palladium catalyst impartation to impart a palladium catalyst to the surface of an insulating part thereof. A palladium conductor layer is formed on the insulating part from a solution for palladium conductor layer formation which contains a palladium compound, an amine compound, and a reducing agent. On the palladium conductor layer is then directly formed a copper deposit by electroplating. Thus, the work is converted to a conductor with the solution for palladium conductor layer formation, which is neutral, without using an electroless copper plating solution which is highly alkaline. Consequently, the polyimide is prevented from being attacked and no adverse influence is exerted on adhesion. By adding an azole compound to the solution for palladium conductor layer formation, a palladium conductor layer is prevented from depositing on copper.

Abstract: Disclosed herein is an interposer substrate, including: a core layer and a through core via (TCV) penetrating through the core layer; circuit wirings formed on both surfaces of the core layer and a TCV upper pad and a TCV lower pad which are each bonded to upper and lower surfaces of the TCV formed on both surfaces of the core layer; upper insulating layers covering the TCV upper pad and the circuit wiring formed on one surface of the core layer and having the circuit wirings formed on upper surfaces thereof; a stack via penetrating through the upper insulating layers of each layer and having one end connected to the TCV upper pad; and a lower insulating layer covering the TCV lower pad and the circuit wiring formed on the other surface of the core layer and provided with an opening which exposes the TCV lower pad.

Abstract: Disclosed are pre-wetting apparatus designs and methods. These apparatus designs and methods are used to pre-wet a wafer prior to plating a metal on the surface of the wafer. Disclosed compositions of the pre-wetting fluid prevent corrosion of a seed layer on the wafer and also improve the filling rates of features on the wafer.

Abstract: A printed wiring board includes an insulative resin substrate having a penetrating hole, a first conductive layer formed on first surface of the substrate, a second conductive layer formed on second surface of the substrate on the opposite side, and a through-hole conductor formed in the penetrating hole and connecting the first and second conductive layers. The through-hole conductor includes a seed layer on inner wall of the penetrating hole, a first electrolytic plated layer on the seed layer such that the first plated layer is filling the space formed by the seed layer in the penetrating hole and forming recesses at the ends of the penetrating hole, respectively, and second electrolytic plated layers filling the recesses, respectively, and the second plated layers includes electrolytic plating having an average crystalline particle diameter greater than an average crystalline particle diameter of electrolytic plating forming the first plated layer.

Abstract: Provided is a resin composition which enables the formation of a roughened surface having a low roughness degree on the surface of an insulation layer in a printed wiring board material when used on the insulation layer regardless of the roughening conditions employed and also enables the formation of a conductive layer having excellent adhesion properties, heat resistance, heat resistance under absorption of moisture, thermal expansion properties and chemical resistance on the roughened surface. A resin composition comprising (A) an inorganic filler that is soluble in an acid, (B) a cyanic acid ester compound and (C) an epoxy resin.

Abstract: A printed circuit board includes a first seed layer, a second seed layer, and a metal layer. The first and second seed layers are disposed on a base substrate and spaced apart from each other. The metal layer covers the first and second seed layers except a first side of the first seed layer and a second side of the second seed layer. The first side of the first seed layer faces the second side of the second seed layer.

Abstract: The presently claimed invention is to provide a package for compact RF signal system, and a method to form the package thereof in order to miniaturize the size of package, improve signal integrity, and reduce manufacturing cost. The package comprises a hybrid substrate with a sandwiched structure, in which the hybrid substrate comprises an upper layer and a lower layer with different dielectric properties being separated by an interposer for improving electrical isolation and mechanical stiffness. Metal layers are formed on the sidewalls of the opening to surround an active component, such that the metal sidewalls together with two ground plates in the upper and lower layers constitute a self-shielding enclosure inside the package to protect the active component.

Abstract: An integrated circuit package includes a packaging substrate with an electrical connection pad formed thereon and an integrated circuit die coupled to the electrical connection pad. The electrical connection pad includes an electroplated surface finish layer, but does not include an electrical trace configured as a plating tail. Because the electrical connection pad is free of a plating tail, signal degradation caused by the presence of plating tails in the integrated circuit package is avoided.

Abstract: The present invention discloses a printed circuit board including a lower wiring layer, an insulating layer which buries the lower wiring layer, and an upper wiring layer formed on the insulating layer to improve reliability of interlayer electrical connection between the wiring layers, wherein the interlayer connection between the upper wiring layer and the lower wiring layer is performed by a via electrode which is provided between the upper wiring layer and the lower wiring layer and has an upper surface bonded to the upper wiring layer and a lower surface bonded to the lower wiring layer, wherein the lower surface of the via electrode is larger than the upper surface thereof.

Abstract: The present invention provides a circuit creation technology that improves conductive line manufacture by adding active and elemental palladium onto the surface of a substrate. The palladium is disposed in minute amounts on the surface and does not form a conductive layer by itself, but facilitates subsequent deposition of a metal onto the surface, according to the pattern of the palladium, to form the conductive lines.

Abstract: A printed wiring board includes an insulative resin substrate having a penetrating hole, a first conductive layer formed on first surface of the substrate, a second conductive layer formed on second surface of the substrate, and a through-hole conductor formed in the hole such that the conductor is connecting the first and second conductive layers. The conductor has a seed layer on inner wall of the hole, a laminated plated layer on the seed layer and a filled plated layer on the laminated layer, the laminated layer is formed such that the laminated layer is closing center portion of the hole and forming recess at end of the hole, the filled layer is formed such that the filled layer is filling the recess, and the laminated layer includes multiple electrolytic plated films laminated along the seed layer and each having thickness which is less at edge than at center.

Abstract: A base insulating layer is formed on a suspension body. A lead wire for plating and a wiring trace are integrally formed on the base insulating layer. A cover insulating layer is formed on the base insulating layer to cover the lead wire for plating and the wiring trace. A thickness of a portion of the cover insulating layer above a region of the base insulating layer in which the lead wire for plating is formed is set smaller than the thickness of a portion of the cover insulating layer above other regions of the base insulating layer.

Abstract: PROBLEMS TO BE SOLVED: To provide a process for roughening both sides of a copper plate by forming a protrusion with a fine bump shape on the both sides of the copper plate, and then to provide a process for a deterioration of an electroplating solution for plating copper to become hard to progress therein. MEANS FOR SOLVING THE PROBLEMS: First of all, there is designed to be arranged electrodes (3, 3) as a similar pole for therebetween to be opposed to each other in an electroplating copper solution 2, and then to be arranged a copper plate 4 at therebetween. And then at first there becomes to be performed an anodic treatment for generating a copper fine particles on both surfaces of the copper plate 4, by performing an electrolytic process with the copper plate 4 as a positive electrode and the electrodes 3 as negative electrodes.

Abstract: An exemplary printed circuit board includes a base, solder pads, and signal traces. The base includes outer surfaces. The signal traces having a first height relative to the base are formed on the outer surface of the base. The solder pads having a second height relative to the base are formed on the same surface having the signal traces. The first height of the signal trace is greater than the second height of the solder pad. Exemplary methods for manufacturing the printed circuit board are also provided.

Abstract: A method of forming a metal pattern includes forming a precursor layer including a metal precursor on a substrate, irradiating a light on the precursor layer to form a metal seed layer having a predetermined pattern, and electroless-plating the metal seed layer to form a metal pattern layer.

Abstract: A voltage is applied between a stainless steel plate and an electrode such that the stainless steel plate is an anode, whereby a passive film formed at a portion to be plated of the stainless steel plate melts due to the reduction reaction and is removed. Thereafter, a voltage is applied between the stainless steel plate and the electrode such that the stainless steel plate is a cathode, whereby a plating underlayer is formed at the portion to be plated of the stainless steel plate from which the passive film is removed.

Abstract: Methods of electroplating metal on a substrate while controlling azimuthal uniformity, include, in one aspect, providing the substrate to the electroplating apparatus configured for rotating the substrate during electroplating, and electroplating the metal on the substrate while rotating the substrate relative to a shield such that a selected portion of the substrate at a selected azimuthal position dwells in a shielded area for a different amount of time than a second portion of the substrate having the same average arc length and the same average radial position and residing at a different angular (azimuthal) position. For example, a semiconductor wafer substrate can be rotated during electroplating slower or faster, when the selected portion of the substrate passes through the shielded area.

Abstract: The present invention is directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a method including capacitively coupling a plating stub to ground so that the resonant frequency caused by the plating stub in a semiconductor package is shifted away from an operational frequency.

Abstract: Electrodeposition methods for use with printed circuit boards and other articles are provided.

Abstract: A fabricating method of a flexible circuit board includes the following steps. The metal carrier foil with metal oxide layer on its surfaces is provided first. The metal oxide layer is formed from the spontaneous oxidization of the metal carrier foil in ambient air and provides passive protection in a sulfuric acid solution or an acidic copper sulphate solution. A conductive seed layer is electroplated onto the metal oxide layer. A flexible insulating layer is formed onto the conductive seed layer by performing a polyimide casting process. The metal carrier foil is then peeled off from the conductive seed layer, which is supported by the insulating layer. A patterned circuit is formed on the insulating layer by performing photoresist coating, developing and etching.

Abstract: A method for making a printed wiring member including wire-bondable contact pads and wear-resistant connector pads, the method includes a) providing a blank printed wiring member comprising a copper foil laminated to a dielectric substrate; b) masking the blank printed wiring member to protect regions of the copper foil; c) removing copper in unprotected regions of the blank printed wiring member to form a patterned printed wiring member including contact pads and connector pads; d) depositing a nickel coating on the patterned printed wiring member; e) electrolytically depositing a hard gold layer on the nickel coating; and f) depositing palladium on a surface of the hard gold layer to improve bondability of the contact pads while preserving wear resistance of the connector pads.

Abstract: There is provided a method of manufacturing a wiring substrate. The method includes: (a) forming a first resist layer having first openings therein on a first surface of a support plate, forming first plated films in the first openings by an electrolytic plating method, and removing the first resist layer; (b) forming a second resist layer having second openings therein on the first surface of the support plate, forming second plated films in the second openings by an electrolytic plating method, and removing the second resist layer; (c) forming a wiring layer and an insulating layer such that the wiring layer is electrically connected to the first and second plated films; and (d) removing the support plate to expose the first and second plated films.

Abstract: A method of treating a copper containing structure on a substrate is disclosed. The method includes electrodepositing the copper containing structure on a substrate, annealing the copper containing structure, and forming an interface between a pad of the copper containing structure and a solder structure after anneal. The interface can have improved resistance to interfacial voiding. The copper containing structure is configured to deliver current between one or more ports and one or more solder structures in the integrated circuit package. Annealing the copper containing structure can move impurities and vacancies to the surface of the copper containing structure for subsequent removal.