Etching Of Coating Patents (Class 205/223)
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Publication number: 20110162972Abstract: A method for producing a thin-film battery includes a film-formation step of forming a film of a positive-electrode material to form a positive-electrode active material film and an annealing step of annealing the positive-electrode active material film. After the annealing step, a lithium-ion introduction step of introducing lithium ions into the positive-electrode active material film. After the introduction of the lithium ions, a reverse-sputtering step of edging the positive-electrode active material film by reverse sputtering.Type: ApplicationFiled: June 26, 2009Publication date: July 7, 2011Applicant: SONY CORPORATIONInventors: Tatsuya Furuya, Katsunori Takahara, Hiroyuki Morioka, Yuichi Sabi
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Publication number: 20110089042Abstract: Methods for manufacturing a gas electron multiplier. One method comprises a step of preparing a blank sheet comprised of an insulating sheet with first and second metal layers on its surface, a first metal layer hole forming step in which the first metal layer is patterned by means of photolithography, such as to form holes through the first metal layer, an insulating sheet hole forming step, in which the holes formed in the first metal layer are extended through the insulating layer by etching from the first surface side only, and a second metal layer hole forming step, in which the holes are extended through the second metal layer. Alternatively, the second metal layer hole forming step is performed by electrochemical etching, such that the first metal layer remains unaffected during etching of the second metal layer.Type: ApplicationFiled: April 14, 2008Publication date: April 21, 2011Applicant: CERN - EUROPEAN ORGANIZATION FOR NUCLEAR RESEARCHInventors: Rui De Oliveira, Serge Duarte Pinto
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Publication number: 20110022207Abstract: Multi-layer structures are electrochemically fabricated by depositing a first material, selectively etching the first material (e.g. via a mask), depositing a second material to fill in the voids created by the etching, and then planarizing the depositions so as to bound the layer being created and thereafter adding additional layers to previously formed layers. The first and second depositions may be of the blanket or selective type. The repetition of the formation process for forming successive layers may be repeated with or without variations (e.g. variations in: patterns; numbers or existence of or parameters associated with depositions, etchings, and or planarization operations; the order of operations, or the materials deposited). Other embodiments form multi-layer structures using operations that interlace material deposited in association with some layers with material deposited in association with other layers.Type: ApplicationFiled: August 6, 2010Publication date: January 27, 2011Inventor: Dennis R. Smalley
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Patent number: 7857959Abstract: A cost-effective and highly reproducible method of fabricating nanowires, and small gaps or spacings in nanowires is disclosed. The nanogaps bridge an important size regime between 1 nm and 100 nm. The nanogaps can be selectively predetermined to be as small as 1.0 nm, or larger than 1000 nm. These electrode gaps can be useful in preparing molecular electronic devices that involve making electrical contact to individual molecules, such as biomolecules, or small clusters of molecules. Microelectrodes having nanogaps for electrical and magnetic applications formed by the method, and as well as biosensors and their use in detecting a biological species, such as DNA, are also disclosed.Type: GrantFiled: May 18, 2007Date of Patent: December 28, 2010Assignee: The Trustees of Boston CollegeInventors: John T. Fourkas, Michael J. Naughton, Richard A. Farrer
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Patent number: 7854831Abstract: In order to provide sanitary fittings, in particular, water supply fittings and sanitary shut-off devices, in general, which visually and haptically are very similar to or scarcely distinguishable (stainless steel finish) from the stainless steel surface of stainless steel sinks, using starting materials which can be processed more cost-effectively, it is proposed that a fitting or fitting parts be manufactured from brass; the fittings or fitting parts be ground and polished; the visible surface of the fittings or fitting parts be nickel-plated; the nickel-plated surface of the fittings or fitting parts be ground and/or brushed; and the ground and/or brushed nickel-plated surface of the fittings or fitting parts be chromium-plated.Type: GrantFiled: September 12, 2005Date of Patent: December 21, 2010Assignee: BLANCO Gmbh + Co KGInventor: Kurt Müllmaier
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Publication number: 20100318142Abstract: An aluminum slug anode usable in capacitors is produced from multiple-stacked layers of aluminum foils. The foils are stacked (possibly after cutting them to have an area similar to the area desired for the anode), hot-pressed, sintered, and anodized to generate the anode. A contact in electrical communication with the foils is formed, as by welding a contact across at least some of the foils. A capacitor casing be formed by situating the anode within a casing which serves as a cathode, with the anode being wrapped in a dielectric such as separator paper.Type: ApplicationFiled: May 4, 2010Publication date: December 16, 2010Inventor: Singjang Chen
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Patent number: 7833403Abstract: This invention involves the technological field of electroplating, chemical plating, specially involves a method for partially plating aluminum and aluminum copper radiators. A radiator is conducted partial chemical oxidation and enclosure before undergoing galvanization. Firstly oxidize the non-plate surface of the radiator by chemical oxidation, then utilize a sealing compound to fill up tiny holes of the porous layer to make a film thereon against the erosion of acid and alkali, and then process common chemical plating or electroplating. Only plate a weldable nickel-phosphorus alloy on the touching parts at where the aluminum radiator or the aluminums and copper radiator connect with the main frame.Type: GrantFiled: October 16, 2007Date of Patent: November 16, 2010Assignee: TWD Metal Production Co., Ltd.Inventors: Wenzhen Xie, Donglin Li
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Patent number: 7828952Abstract: Multi-layer structures are electrochemically fabricated by depositing a first material, selectively etching the first material (e.g. via a mask), depositing a second material to fill in the voids created by the etching, and then planarizing the depositions so as to bound the layer being created and thereafter adding additional layers to previously formed layers. The first and second depositions may be of the blanket or selective type. The repetition of the formation process for forming successive layers may be repeated with or without variations (e.g. variations in: patterns; numbers or existence of or parameters associated with depositions, etchings, and or planarization operations; the order of operations, or the materials deposited). Other embodiments form multi-layer structures using operations that interlace material deposited in association with some layers with material deposited in association with other layers.Type: GrantFiled: October 6, 2006Date of Patent: November 9, 2010Assignee: Microfabrica Inc.Inventor: Dennis R. Smalley
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Patent number: 7811427Abstract: Permanent or temporary alignment and/or retention structures for receiving multiple components are provided. The structures are preferably formed monolithically via a plurality of deposition operations (e.g. electrodeposition operations). The structures typically include two or more positioning fixtures that control or aid in the positioning of components relative to one another, such features may include (1) positioning guides or stops that fix or at least partially limit the positioning of components in one or more orientations or directions, (2) retention elements that hold positioned components in desired orientations or locations, and/or (3) positioning and/or retention elements that receive and hold adjustment modules into which components can be fixed and which in turn can be used for fine adjustments of position and/or orientation of the components.Type: GrantFiled: March 12, 2007Date of Patent: October 12, 2010Assignee: Microfabrica Inc.Inventors: Adam L. Cohen, Daniel I. Feinberg, Christopher A. Bang
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Publication number: 20100230290Abstract: The invention relates to a method (3) of fabricating a mould (39, 39?) including the following steps: a) depositing (9) an electrically conductive layer on the top (20) and bottom (22) of a wafer (21) made of silicon-based material; b) securing (13) said wafer to a substrate (23) using an adhesive layer; c) removing (15) one part (26) of said conductive layer from the top of the wafer (21); d) etching (17) said wafer as far as the bottom conductive layer (22) thereof in the shape (26) of said part removed from the top conductive layer (22) to form at least one cavity (25) in said mould. The invention concerns the field of micromechanical parts, particularly for timepiece movements.Type: ApplicationFiled: March 12, 2010Publication date: September 16, 2010Applicant: NIVAROX-FAR S.A.Inventors: Pierre Cusin, Clare Golfier, Jean-Philippe Thiebaud
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Publication number: 20100224501Abstract: The present invention relates to methods and apparatus for plating a conductive material on a workpiece surface in a highly desirable manner. Using a workpiece-surface-influencing device, such as a mask or sweeper, that preferentially contacts the top surface of the workpiece, relative movement between the workpiece and the workpiece-surface-influencing device is established so that an additive in the electrolyte solution disposed on the workpiece and which is adsorbed onto the top surface is removed or otherwise its amount or concentration changed with respect to the additive on the cavity surface of the workpiece. Plating of the conductive material can place prior to, during and after usage of the workpiece-surface-influencing device, particularly after the workpiece surface influencing device no longer contacts any portion of the top surface of the workpiece, to achieve desirable semiconductor structures.Type: ApplicationFiled: May 24, 2010Publication date: September 9, 2010Applicant: NOVELLUS SYSTEMS, INC.Inventor: Bulent M. Basol
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Patent number: 7790269Abstract: To produce an ultra-thin copper foil with a carrier foil that microscopic crystal grains can be deposited without being affected by the surface roughness of a carrier foil, etching can be performed until an ultra-fine width such that line/space is 15 mum or less, and the microscopic line and a wiring board have large peel strength even after line of 15 mum is etched. An ultra-thin copper foil wherein a carrier foil, a peeling layer, an ultra-thin copper foil are laminated in this order, the ultra-thin copper foil (before roughening treatment is performed) is an electrolytic copper foil that surface roughness of 2.5 mum as ten point height of roughness profile, and the minimum distance between peaks of salients of a based material is 5 mum or more. Moreover, the surface of the ultra-thin copper foil is performed roughening treatment.Type: GrantFiled: September 5, 2008Date of Patent: September 7, 2010Assignee: The Furukawa Electric Co., Ltd.Inventors: Akitoshi Suzuki, Shin Fukuda
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Patent number: 7776199Abstract: The present invention provides a printed wiring board free from undercuts, which can be formed by an additive method without a dry treatment and a dry treatment apparatus, and a production method thereof. A printed wiring board of the present invention has a conductor circuit free from undercuts which is produced by carrying out additional plating to fill undercuts.Type: GrantFiled: August 11, 2004Date of Patent: August 17, 2010Assignee: Fujikura Ltd.Inventors: Hideyuki Fujinami, Reiji Higuchi, Kazuharu Kobayashi
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Publication number: 20100193366Abstract: An electroplating method that includes: a) contacting a first substrate with a first article, which includes a substrate and a conformable mask disposed in a pattern on the substrate; b) electroplating a first metal from a source of metal ions onto the first substrate in a first pattern, the first pattern corresponding to the complement of the conformable mask pattern; and c) removing the first article from the first substrate, is disclosed. Electroplating articles and electroplating apparatus are also disclosed.Type: ApplicationFiled: February 1, 2010Publication date: August 5, 2010Inventor: Adam L. Cohen
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Patent number: 7763158Abstract: Mass distribution within programmable surface control devices is controlled by the presence or absence of an electrodeposition of metal and/or metal ions from a solid solution upon application of a suitable electric field. One such programmable surface control device includes a tunable cantilever assembly whose resonant frequency is changed by depositing and dissolving an electrodeposit on a surface of the assembly using an electric field.Type: GrantFiled: February 14, 2006Date of Patent: July 27, 2010Assignee: Axon Technologies CorporationInventor: Michael N Kozicki
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Patent number: 7759138Abstract: A method of fabricating a microchannel plate includes forming a plurality of pores in a silicon substrate. The plurality of pores is oxidized, thereby consuming silicon at surfaces of the plurality of pores and forming a silicon dioxide layer over the plurality of pores. At least a portion of the silicon dioxide layer is stripped, which reduces a surface roughness of the plurality of pores. A semiconducting layer can be deposited onto the surface of the silicon dioxide layer. The semiconducting layer is then oxidized, thereby consuming at least some of the polysilicon or amorphous silicon layer and forming an insulating layer. Resistive and secondary electron emissive layers are then deposited on the insulating layer by atomic layer deposition.Type: GrantFiled: September 20, 2008Date of Patent: July 20, 2010Assignee: Arradiance, Inc.Inventors: David Beaulieu, Neal T. Sullivan
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Patent number: 7731830Abstract: An electroformed tool has an integrated base with channels contacting the tool with heat exchange fluids flowing through the channels during molding or embossing. A blank base is machined with a network of interconnected open channels on a top surface and end flow through passageways communicating with the channels. The tool is used as an electrode to erode the top surface of the blank base using plunge electro discharge machining by lowering the uneven deposit on the bottom of the electroformed tool down onto the top surface of the blank base in the electro discharge machining environment to form a top contoured surface to mate with the uneven deposit on the non-molding side of the substrate. Thermal management fluid channels are thereby conformal to the mold cavity. The tool and base are sealed together.Type: GrantFiled: May 1, 2007Date of Patent: June 8, 2010Inventor: Robert E. Szokolay
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Publication number: 20100108531Abstract: The object of the invention is to provide an adhesive layer forming liquid capable of maintaining the performance of forming an adhesive layer easily and keeping adhesive property to a resin certainly, and an adhesive layer forming process using the liquid. The adhesive layer forming liquid of the invention is an adhesive layer forming liquid for forming an adhesive layer for bonding a copper and a resin to each other, which is an aqueous solution comprising an acid, a stannous salt, a stannic salt, a complexing agent, and a stabilizer, and which is prepared to set the value of B/A to 0.010 or more and 1.000 or less at the time of the preparation, wherein A represents the concentration (unit: % by mass) of the stannous salt as the concentration of bivalent tin ions, and B represents the concentration (unit: % by mass) of the stannic salt as the concentration of tetravalent tin ions.Type: ApplicationFiled: November 2, 2009Publication date: May 6, 2010Applicant: MEC COMPANY LTD.Inventors: Mutsuyuki KAWAGUCHI, Tsuyoshi AMATANI, Yuko FUJII, Masami TSUTAE
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Patent number: 7702434Abstract: A motor vehicle and an indicating apparatus for a motor vehicle, includes a display for optical depiction of information concerning the motor vehicle by the emission of light, and having a decorative layer positioned on the display.Type: GrantFiled: September 3, 2004Date of Patent: April 20, 2010Assignee: Volkswagen AGInventors: Cedric Dupont, Arne Stoschek, Sven Strohband
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Patent number: 7674361Abstract: Multi-layer fabrication methods (e.g. electrochemical fabrication methods) for forming microscale and mesoscale devices or structures (e.g. turbines) provide bushings or roller bearing that allow rotational or linear motion which is constrained by multiple structural elements spaced from one another by gaps that are effectively less than minimum features sizes associated with the individual layers used to form the structures. In some embodiments, features or protrusions formed on different layers on opposing surfaces are offset along the axis of layer stacking so as to bring the features into positions that are closer than allowed by the minimum features sizes associated with individual layers. In other embodiments, interference is used to create effective spacings that are less than the minimum features sizes.Type: GrantFiled: May 26, 2006Date of Patent: March 9, 2010Assignee: Microfabrica Inc.Inventor: Adam L. Cohen
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Publication number: 20100044080Abstract: Systems and methods include depositing one or more materials on a voltage switchable dielectric material. In certain aspects, a voltage switchable dielectric material is disposed on a conductive backplane. In some embodiments, a voltage switchable dielectric material includes regions having different characteristic voltages associated with deposition thereon. Some embodiments include masking, and may include the use of a removable contact mask. Certain embodiments include electrografting. Some embodiments include an intermediate layer disposed between two layers.Type: ApplicationFiled: October 29, 2009Publication date: February 25, 2010Inventor: Lex Kosowsky
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Patent number: 7655127Abstract: Method of fabricating electronic devices is disclosed. The method includes the steps of forming an anodized layer that has a thickness greater than a desired thickness, and forming an electrically conductive layer on the anodized layer. The method further includes the steps of removing the conductive layer in a selected area to expose the anodized layer, and removing the exposed anodized layer until the anodized layer in the exposed area has the desired thickness.Type: GrantFiled: November 27, 2006Date of Patent: February 2, 2010Assignee: 3M Innovative Properties CompanyInventors: Michael W. Bench, Steven D. Theiss, Grace L. Ho
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Patent number: 7618525Abstract: An electroplating method that includes: a) contacting a first substrate with a first article, which includes a substrate and a conformable mask disposed in a pattern on the substrate; b) electroplating a first metal from a source of metal ions onto the first substrate in a first pattern, the first pattern corresponding to the complement of the conformable mask pattern; and c) removing the first article from the first substrate, is disclosed. Electroplating articles and electroplating apparatus are also disclosed.Type: GrantFiled: October 29, 2007Date of Patent: November 17, 2009Assignee: University of Southern CaliforniaInventor: Adam L. Cohen
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Patent number: 7611616Abstract: Various embodiments of the invention are directed to formation of mesoscale or microscale devices using electrochemical fabrication techniques where structures are formed from a plurality of layers as opened structures which can be folded over or other otherwise combined to form structures of desired configuration. Each layer is formed from at least one structural material and at least one sacrificial material. The initial formation of open structures may facilitate release of the sacrificial material, ability to form fewer layers to complete a structure, ability to locate additional materials into the structure, ability to perform additional processing operations on regions exposed while the structure is open, and/or the ability to form completely encapsulated and possibly hollow structures.Type: GrantFiled: August 18, 2006Date of Patent: November 3, 2009Assignee: Microfabrica Inc.Inventors: Adam L. Cohen, Michael S. Lockard, Dennis R. Smalley
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Patent number: 7611617Abstract: A method of forming a dielectric component, such as a capacitor is disclosed. In such a method, a conductive surface is applied to a dielectric to form a coated dielectric. Then a portion of the conductive surface is removed from the coated dielectric to form at least two electrically isolated conductive areas.Type: GrantFiled: March 12, 2007Date of Patent: November 3, 2009Assignee: Spectrum Control, Inc.Inventors: Jeffrey D. Chereson, Rob Ehrensberger, Michael Boudreaux
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Publication number: 20090226760Abstract: A method for forming a tapered, electroplated structure. The method involves forming a first mask structure having an opening. A shrink material is deposited into the opening, such that the thickness of the shrink material is less than the thickness of the first mask structure. The first mask structure and the shrink material are then heated causing the sides of the opening in the mask structure to bulge inward. The shrink material is then removed, and a first electrically conductive material can then be electroplated into the opening to a thickness that is much less than the thickness of the mask. The bulbous shaped of the deformed photoresist mask forms a taper on the first electrically conductive material. The first mask can then be removed and a second electrically conductive material can be electroplated over the first electrically conductive material.Type: ApplicationFiled: March 6, 2008Publication date: September 10, 2009Inventors: Christian Rene Bonhote, Jeffrey S. Lille, Scott Arthur MacDonald
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Publication number: 20090218233Abstract: Method of forming a multilayer structure by electroetching or electroplating on a substrate. A seed layer is arranged on the substrate and a master electrode is applied thereto. The master electrode has a pattern layer forming multiple electrochemical cells with the substrate. A voltage is applied for etching the seed layer or applying a plating material to the seed layer. A dielectric material (9) is arranged between the structures (8) thus formed. The dielectric layer is planarized for uncovering the structure below and another structure layer is formed on top of the first. Alternatively, the dielectric layer is applied with a thickness two layers and the structure below is accessed by selective etching of the dielectric layer for selectively uncovering the top surface of the structure below. Multiple structure layer may also be formed in one step.Type: ApplicationFiled: November 20, 2006Publication date: September 3, 2009Inventors: Mikael Fredenberg, Patrik Moller, Peter Wiwen-Nilsson
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Publication number: 20090207576Abstract: An embodiment is an inductor that may include a slotted magnetic material to decrease eddy currents therein that may limit the operation of the inductor at high frequency. An embodiment may employ electro- or electroless plating techniques to form a layer or layers of magnetic material within the slotted magnetic material structure, and in particular those magnetic material layers adjacent to insulator layers.Type: ApplicationFiled: March 18, 2009Publication date: August 20, 2009Applicant: INTEL CORPORATIONInventors: Donald S. Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
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Publication number: 20090202845Abstract: An anodized aluminum product in continuous web or sheet form, which is heat sealed and coated with an antimicrobial composition. The antimicrobial coating can be bound to surface of the anodic layer and can comprise a network of cross-linked organo-silane molecules that are also covalently bound to the surface of the anodic layer. A process also is provided including: forming an anodic layer on the surface of an aluminum substrate; heat sealing the anodic layer; preheating the web or sheet to a range from about 140° F. to about 200° F.; applying an antimicrobial composition at an application rate sufficient for the composition to at least begin binding to the surface of and form an antimicrobial coating over the anodic layer; and post heating the coated anodized antimicrobial web or sheet to a range from about 140° F. to about 200° F. to further bind the composition to the cure the antimicrobial coating.Type: ApplicationFiled: February 10, 2009Publication date: August 13, 2009Applicant: Lorin Industries, Inc.Inventors: Lance W. Hodges, Thomas R. Achterhoff, Kevin H. Darcy, James A. Nalewick
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Patent number: 7524427Abstract: Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material. Some embodiments use different seed layer materials and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while other embodiments apply the materials in blanket fashion. Some embodiments remove extraneous depositions (e.g. depositions to regions unintended to form part of a layer) via planarization operations while other embodiments remove the extraneous material via etching operations.Type: GrantFiled: January 3, 2005Date of Patent: April 28, 2009Assignee: Microfabrica Inc.Inventors: Adam L. Cohen, Michael S. Lockard, Kieun Kim, Qui T. Le, Gang Zhang, Uri Frodis, Dale S. McPherson, Dennis R. Smalley
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Publication number: 20090101513Abstract: A method of manufacturing a film printed circuit board is provided. A film substrate consisting of a polyimide substrate, an alloy layer and a first copper layer is provided. A first lithographic and etching process is performed to pattern the copper layer and the alloy layer and a plurality of conductive line structures is formed on the polyimide substrate. A second copper layer is formed over the polyimide substrate and the conductive line structures. A second lithographic and etching process is performed to pattern the second copper layer.Type: ApplicationFiled: December 2, 2008Publication date: April 23, 2009Inventors: CHIA-HUI WU, Pai-Sheng Cheng, Hung-Yi Wang
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Publication number: 20090095634Abstract: A plating method can form a plated film having a uniform thickness over the entire surface, including the peripheral surface, of a substrate. The plating method includes: disposing an anode so as to face a conductive film, formed on a substrate, which serves as a cathode, and disposing an auxiliary cathode on an ring-shaped seal member for sealing a peripheral portion of the substrate; bringing the conductive film, the anode and the auxiliary cathode into contact with a plating solution; and supplying electric currents between the anode and the conductive film, and between the anode and the auxiliary cathode to carry out plating.Type: ApplicationFiled: October 15, 2007Publication date: April 16, 2009Inventors: Natsuki Makino, Keisuke Namiki, Kunihito Ide, Junji Kunisawa, Katsuyuki Musaka, Philippe Vereecken, Brett C. Baker-O'Neal, Hariklia Deligianni, Keith Kwietniak
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Patent number: 7517444Abstract: The present invention relates to methods and apparatus for plating a conductive material on a workpiece surface in a highly desirable manner. Using a workpiece-surface-influencing device, such as a mask or sweeper, that preferentially contacts the top surface of the workpiece, relative movement between the workpiece and the workpiece-surface-influencing device is established so that an additive in the electrolyte solution disposed on the workpiece and which is adsorbed onto the top surface is removed or otherwise its amount or concentration changed with respect to the additive on the cavity surface of the workpiece. Plating of the conductive material can place prior to, during and after usage of the workpiece-surface-influencing device, particularly after the workpiece surface influencing device no longer contacts any portion of the top surface of the workpiece, to achieve desirable semiconductor structures.Type: GrantFiled: July 26, 2005Date of Patent: April 14, 2009Assignee: Novellus Systems, Inc.Inventor: Bulent M. Basol
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Patent number: 7517462Abstract: Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material. Some embodiments use different seed layer materials and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while other embodiments apply the materials in blanket fashion. Some embodiments remove extraneous depositions (e.g. depositions to regions unintended to form part of a layer) via planarization operations while other embodiments remove the extraneous material via etching operations.Type: GrantFiled: January 3, 2005Date of Patent: April 14, 2009Assignee: Microfabrica Inc.Inventors: Adam L. Cohen, Michael S. Lockard, Kieun Kim, Qui T. Le, Gang Zhang, Uri Frodis, Dale S. McPherson, Dennis R. Smalley
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Patent number: 7488408Abstract: The present invention has an object to provide a tin-plated film and a method for producing the same, capable of preventing whiskers from being generated and simultaneously preventing the surface of a substrate to be plated, which is not covered with a tin-plated film, from discoloring due to oxidation, by which prevention of whisker generation, suppression of whisker growth, and prevention of discoloring of a substrate to be plated are compatible with simplified operations ensuring excellent productivity. The method is provided with the steps of removing a part of a tin-plated film formed on copper or copper alloy; processing to prevent discoloring of the copper or copper alloy from which the tin-plated film is removed; and applying heat energy to the tin-plated film of the copper or copper alloy which is processed to prevent discoloring.Type: GrantFiled: July 19, 2005Date of Patent: February 10, 2009Assignee: Panasonic CorporationInventors: Hisahiro Tanaka, Shigeki Ogata
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Patent number: 7479232Abstract: A method is for producing a semiconductor component, e.g., a multilayer semiconductor element, e.g., a micromechanical component, e.g., a pressure sensor, having a semiconductor substrate, e.g., made of silicon, and a semiconductor component produced according to the method. To reduce the production cost of such a semiconductor component, in a first step a first porous layer is produced in the semiconductor component, and in a second step a hollow or cavity is produced under or from the first porous layer in the semiconductor component, with the hollow or cavity capable of being provided with an external access opening.Type: GrantFiled: September 6, 2005Date of Patent: January 20, 2009Assignee: Robert Bosch GmbHInventors: Hubert Benzel, Heribert Weber, Hans Artmann, Frank Schaefer
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Patent number: 7422696Abstract: Multicomponent nanorods having segments with differing electronic and/or chemical properties are disclosed. The nanorods can be tailored with high precision to create controlled gaps within the nanorods or to produce diodes or resistors, based upon the identities of the components-making up the segments of the nanorods. Macrostructural composites of these nanorods also are disclosed.Type: GrantFiled: June 30, 2005Date of Patent: September 9, 2008Assignee: Northwestern UniversityInventors: Chad A. Mirkin, Lidong Qin, Sungho Park, Ling Huang, Sung-Wook Chung
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Patent number: 7384530Abstract: The invention includes methods of fabrication and apparatuses. In at least some embodiments of the applicants' invention, the methods include processes of: maskless selective deposition of non-layered structures, selective etching and/or deposition without use of a separate mask and/or lithography techniques, retaining selected portions of sacrificial material during removal (e.g. etching) of other portions of sacrificial material, depositing materials other than the structural and sacrificial materials, including more than one type of structural and/or sacrificial material, and fabrication of interlacing elements. Embodiments of the methods of the invention provide increased capabilities, properties, flexibility and in the fabrication of three-dimensional structures by electro-deposition or other techniques.Type: GrantFiled: May 7, 2004Date of Patent: June 10, 2008Assignee: Microfabrica Inc.Inventors: Adam L. Cohen, Dennis R. Smalley
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Patent number: 7323094Abstract: An electroplating system (30) and process makes electrical current density across a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that plates on electrical current density modifier portions (364) of structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.Type: GrantFiled: August 14, 2002Date of Patent: January 29, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Cindy Reidsema Simpson, Matthew T. Herrick, Gregory S. Etherington, James Derek Legg
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Patent number: 7316783Abstract: A method of wiring formation includes forming a feeder film partially on a substrate, forming on the substrate a plating base film via a physical film making method so that the plate base film partially overlaps the feeder film, forming a plated wiring on the plating base film using an electrolytic plating, and selectively removing at least an area of the feeder film which is exposed from the plated wiring, using a wet etching process.Type: GrantFiled: July 7, 2004Date of Patent: January 8, 2008Assignee: Murata Manufacturing Co., Ltd.Inventors: Yoshiyuki Tonami, Yoshihiro Koshido
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Patent number: 7303663Abstract: Multilayer structures are electrochemically fabricated from at least one structural material (e.g. nickel), that is configured to define a desired structure and which may be attached to a substrate, and from at least one sacrificial material (e.g. copper) that surrounds the desired structure. After structure formation, the sacrificial material is removed by a multi-stage etching Operation. In some embodiments sacrificial material to be removed may be located within passages or the like on a substrate or within an add-on component. The multi-stage etching Operations may be separated by intermediate post processing activities, they may be separated by cleaning Operations, or barrier material removal Operations, or the like. Barriers may be fixed in position by contact with structural material or with a substrate or they may be solely fixed in position by sacrificial material and are thus free to be removed after all retaining sacrificial material is etched.Type: GrantFiled: May 7, 2003Date of Patent: December 4, 2007Assignee: Microfabrica, Inc.Inventors: Adam L. Cohen, Michael S. Lockard, Dale S. McPherson
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Patent number: 7252750Abstract: A dual contact ring for contacting a patterned surface of a wafer and electrochemical plating of a metal on the patterned central region of the wafer and removing the metal from the outer, edge region of the wafer. The dual contact ring has an outer voltage ring in contact with the outer, edge region of the wafer and an inner voltage ring in contact with the inner, central region of the wafer. The outer voltage ring is connected to a positive voltage source and the inner voltage ring is connected to a negative voltage source. The inner voltage ring applies a negative voltage to the wafer to facilitate the plating of metal onto the patterned region of the wafer. A positive voltage is applied to the wafer through the outer voltage ring to remove the plated metal from the outer, edge region of the substrate.Type: GrantFiled: September 16, 2003Date of Patent: August 7, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Wen Liu, Jung-Chih Tsao, Ke-Wei Chen, Ying-Lang Wang
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Patent number: 7252861Abstract: Multi-layer structures are electrochemically fabricated by depositing a first material, selectively etching the first material (e.g. via a mask), depositing a second material to fill in the voids created by the etching, and then planarizing the depositions so as to bound the layer being created and thereafter adding additional layers to previously formed layers. The first and second depositions may be of the blanket or selective type. The repetition of the formation process for forming successive layers may be repeated with or without variations (e.g. variations in: patterns; numbers or existence of or parameters associated with depositions, etchings, and or planarization operations; the order of operations, or the materials deposited). Other embodiments form multi-layer structures using operations that interlace material deposited in association with some layers with material deposited in association with other layers.Type: GrantFiled: May 7, 2003Date of Patent: August 7, 2007Assignee: Microfabrica Inc.Inventor: Dennis R. Smalley
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Patent number: 7250101Abstract: Multilayer structures are electrochemically fabricated on a temporary (e.g. conductive) substrate and are thereafter bonded to a permanent (e.g. dielectric, patterned, multi-material, or otherwise functional) substrate and removed from the temporary substrate. In some embodiments, the structures are formed from top layer to bottom layer, such that the bottom layer of the structure becomes adhered to the permanent substrate, while in other embodiments the structures are form from bottom layer to top layer and then a double substrate swap occurs. The permanent substrate may be a solid that is bonded (e.g. by an adhesive) to the layered structure or it may start out as a flowable material that is solidified adjacent to or partially surrounding a portion of the structure with bonding occurs during solidification. The multilayer structure may be released from a sacrificial material prior to attaching the permanent substrate or it may be released after attachment.Type: GrantFiled: May 7, 2003Date of Patent: July 31, 2007Assignee: Microfabrica Inc.Inventors: Jeffrey A. Thompson, Adam L. Cohen, Michael S. Lockard, Dennis R. Smalley
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Patent number: 7247227Abstract: In devices such as flat panel displays, an aluminum oxide layer is provided between an aluminum layer and an ITO layer when such materials would otherwise be in contact to protect the ITO from optical and electrical defects sustained, for instance, during anodic bonding and other fabrication steps. This aluminum oxide barrier layer is preferably formed either by: (1) partially or completely anodizing an aluminum layer formed over the ITO layer, or (2) an in situ process forming aluminum oxide either over the ITO layer or over an aluminum layer formed on the ITO layer. After either of these processes, an aluminum layer is then formed over the aluminum oxide layer.Type: GrantFiled: September 21, 2001Date of Patent: July 24, 2007Assignee: Micron Technology, Inc.Inventors: Robert J. Hanson, Won-Joo Kim, Mike E. Pugh
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Patent number: 7219414Abstract: A main pole layer of a magnetic head includes a first portion disposed at a distance from a medium facing surface, and a second portion that is smaller in thickness than the first portion and disposed between the first portion and the medium facing surface. The step of forming the main pole layer includes the steps of forming a plating layer such that one of ends of the plating layer closer to the medium facing surface is located at a position that coincides with the position of one of ends of the first portion closer to the medium facing surface; forming a first nonmagnetic layer to cover the plating layer; polishing the first nonmagnetic layer and the plating layer; forming a space by removing the plating layer; forming a magnetic layer, which will be the main pole layer, in the space and on the top surface of the first nonmagnetic layer; forming a second nonmagnetic layer to cover the magnetic layer; and polishing the second nonmagnetic layer and the magnetic layer.Type: GrantFiled: January 25, 2005Date of Patent: May 22, 2007Assignee: TDK CorporationInventors: Yuichi Watabe, Susumu Aoki, Yasuyuki Notsuke, Tetsuya Roppongi
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Patent number: 7214304Abstract: A process for preparing a non-conductive substrate for electroplating is proposed. The proposed process comprises contacting the substrate, after desmear, with a combined neutralization/sacrificial coating solution followed by treatment with a carbon dispersion solution. The combined neutralization/sacrificial coating solution neutralizes permanganate residues from the desmear step and applies a sacrificial coating to metallic surfaces on the substrate. The sacrificial coating allows for easy and reliable removal of unwanted carbon residues from the metallic surfaces prior to electroplating.Type: GrantFiled: October 13, 2004Date of Patent: May 8, 2007Inventors: Hyunjung Lee, Richard C. Retallick
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Patent number: 7192510Abstract: A fluid control device has very fine pores with an average diameter not greater than 10 nm and provides a large flux. The fluid control device comprises an anodized alumina film having fine pores and a silicon based micro-porous film having very fine pores and made from an AlSi mixed film and the fine pores and the very fine pores are at least partly linked with each other. The fluid control device is prepared from a film including at least an aluminum layer and an AlSi mixed film by forming an anodized alumina film having fine pores by way of an anodization process for the aluminum layer part and also forming a silicon based micro-porous film having very fine pores containing silicon as principal ingredient by way of an anodization process or etching process for the AlSi mixed film. The fluid control device can be used as filter or ultrafilter film that allows fluid and gas to pass through it.Type: GrantFiled: December 11, 2003Date of Patent: March 20, 2007Assignee: Canon Kabushiki KaishaInventors: Tohru Den, Kazuhiko Fukutani
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Patent number: 7160429Abstract: In some embodiments, multilayer structures are electrochemically fabricated from at least one structural material (e.g. nickel), at least one sacrificial material (e.g. copper), and at least one sealing material (e.g. solder). In some embodiments, the layered structure is made to have a desired configuration which is at least partially and immediately surrounded by sacrificial material which is in turn surrounded almost entirely by structural material. The surrounding structural material includes openings in the surface through which etchant can attack and remove trapped sacrificial material found within. Sealing material is located near the openings. After removal of the sacrificial material, the box is evacuated or filled with a desired gas or liquid. Thereafter, the sealing material is made to flow, seal the openings, and resolidify. In other embodiments, a post-layer formation lid or other enclosure completing structure is added.Type: GrantFiled: May 7, 2003Date of Patent: January 9, 2007Assignee: Microfabrica Inc.Inventors: Adam L. Cohen, Michael S. Lockard, Dennis R. Smalley, Vacit Arat, Christopher J. Lee
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Patent number: 7087315Abstract: A method for forming a plating film, comprising the steps of: applying a plating film onto an object to be plated at a first current density for a predetermined period in a plating bath having a cathode capable of varying current and an anode and; and maintaining the object to be plated at a second current density lower than the first current density. According to the present invention, it is possible to improve solderability of a plating film for conventional lead-free solder by a simple method, which allows the productivity to further enhanced, resulting in a plating film with reduced production costs.Type: GrantFiled: September 21, 2004Date of Patent: August 8, 2006Assignees: Sharp Kabushiki Kaisha, Kobe Leadmikk Co., Ltd.Inventors: Yoshihiko Matsuo, Ryukichi Ikeda, Kimihiko Yoshida, Fumio Okuda