Filling Or Coating Of Groove Or Through Hole In A Conductor With An Insulator Patents (Class 216/19)
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Patent number: 7931818Abstract: A process of an embedded circuit structure is provided. A complex metal layer, a prepreg, a supporting board, another prepreg and another complex metal layer are laminated together, wherein each of the complex metal layers has an inner metal layer and an outer metal layer stacked on the inner metal layer, the roughness of the outer surfaces of the inner metal layers is less than the roughness of the second outer surfaces of the outer metal layers, and the outer surfaces of the outer metal layers after laminating are exposed outwards. Each of two patterned photoresist layers is respectively formed on the outer surfaces of the outer metal layers. A metal material is created on portions of the outer surfaces of the outer metal layers not covered by the patterned photoresist layers to form two patterned circuit layers. The patterned photoresist layers are then removed to form a laminating structure.Type: GrantFiled: November 2, 2007Date of Patent: April 26, 2011Assignee: Unimicron Technology Corp.Inventors: Tsung-Yuan Chen, Chun-Chien Chen
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Publication number: 20100308010Abstract: The invention relates to a method (1) of fabricating a composite micromechanical component (41, 41?) including the following steps: a) providing (10) a substrate (9, 9?) that includes a horizontal top layer (21) and a horizontal bottom layer (23) made of electrically conductive, micromachinable material, and secured to each other by an electrically insulating, horizontal, intermediate layer (22); b) etching at least one pattern (26) in the top layer (21) through to the intermediate layer (22), so as to form at least one cavity (25) in the substrate (9, 9?); c) coating (16) the top part of said substrate with an electrically insulating coating (30); d) directionally etching (18) said coating and said intermediate layer so as to limit the presence thereof exclusively at each vertical wall (51, 52) formed in said top layer; e) performing (5) an electrodeposition by connecting the electrode to the conductive bottom layer (23) of the substrate (9, 9?) to form at least one metal part (33, 43, 43?) of said componType: ApplicationFiled: June 9, 2010Publication date: December 9, 2010Applicant: NIVAROX-FAR S.A.Inventors: Pierre Cusin, Jean-Philippe Thiebaud
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Patent number: 7743494Abstract: A process for fabricating a circuit board includes: providing a substrate including a first electrically conductive core having a first insulating coating on a first side and a second insulating coating on a second side, forming an opening in the first and second insulating coatings and the first electrically conductive core, exposing an edge of the conductive core within the opening, and electrodepositing a third insulating material on the exposed edge of the first electrically conductive core. A circuit board fabricated using the process is also provided.Type: GrantFiled: January 11, 2008Date of Patent: June 29, 2010Assignee: PPG Industries Ohio, Inc.Inventors: Alan E. Wang, Kevin C. Olson, Michael J. Pawlik
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Patent number: 7718079Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.Type: GrantFiled: November 20, 2001Date of Patent: May 18, 2010Assignee: United Microelectronics CorporationInventors: Chih-Chien Liu, Ta-Shan Tseng, Wen Bin Shieh, Juan-Yuan Wu, Water Lur, Shih-Wei Sun
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Patent number: 7691276Abstract: The method according to the invention is essentially characterised in that a resistance material (5)—for example nickel or a nickel alloy—is attached on a first structured conductor layer (2)—it may be of copper or a copper alloy. Subsequently, the first structured conductor layer (5) is removed again at least at those locations at which a resistor is to arise. This may be effected by way of firstly removing the insulating material (1) on which the first conductor layer adheres, firstly from the rear side at the desired locations for example by way of plasma etching. The conductor layer 2 my be subsequently removed at least in regions.Type: GrantFiled: March 14, 2006Date of Patent: April 6, 2010Assignee: Dyconex AGInventor: Pavlin Sabev
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Publication number: 20100074459Abstract: Provided are a piezoelectric microspeaker and a method of fabricating the same. In the piezoelectric microspeaker, a diaphragm includes a first region and a second region. The first region may be formed of a material capable of maximizing an exciting force, and the second region may be formed of a material having less initial stress and a lower Young's modulus than the first region.Type: ApplicationFiled: April 27, 2009Publication date: March 25, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok-whan CHUNG, Dong-kyun KIM, Byung-gil JEONG
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Patent number: 7615162Abstract: A printed circuit board is by formed by laminating an interlaminar insulating layer on a conductor circuit of a substrate, in which the conductor circuit is comprised of an electroless plated film and an electrolytic plated film and a roughened layer is formed on at least a part of the surface of the conductor circuit.Type: GrantFiled: September 19, 2006Date of Patent: November 10, 2009Assignee: IBIDEN Co., Ltd.Inventors: Motoo Asai, Yasuji Hiramatsu, Yoshinori Wakihara, Kazuhito Yamada
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Publication number: 20090232467Abstract: Disclosed herein is a printed circuit board for an optical waveguide, including a base board, and an optical waveguide formed on the base board. The optical waveguide includes a lower clad layer formed on the base board, an insulation layer formed on the lower clad layer and having a core-forming through-hole, a core part formed on a region of the lower clad layer, which is exposed through the through-hole, and an upper clad layer formed in the through-hole and on the insulation layer.Type: ApplicationFiled: June 9, 2008Publication date: September 17, 2009Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Joon Sung Kim, Sang Hoon Kim, Jae Hyun Jung, Han Seo Cho
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Patent number: 7585419Abstract: A substrate structure and the fabrication method thereof are provided herein. The present invention utilizes a laminate as the support of the package process and then removes the laminate after the following package steps so as to obtain a quite smooth surface for using in the internal-plane structure of the circuit board and a stacking structure that can be applied to many different types of the chip package structures.Type: GrantFiled: June 17, 2005Date of Patent: September 8, 2009Assignee: Boardtek Electronics Corp.Inventor: Joseph Cheng
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Patent number: 7540969Abstract: A manufacturing process of a high thermal conducting circuit substrate is provided. First, a metal core substrate is provided and then the metal core substrate is etched at different etching speeds. Afterwards, two insulating layers are formed respectively on two sides of the etched metal core substrate. In addition, as an option, two conducting layers are formed respectively on two sides of the metal core substrate and are on top of the insulting layers. The conducting layers are patterned according to designs appropriate for the products. Because the high thermal conducting circuit substrate fabricated as the aforementioned manufacturing process mainly comprises the metal core substrate, it helps to elevate the thermal conduction of the circuit substrate itself.Type: GrantFiled: December 1, 2006Date of Patent: June 2, 2009Assignee: Subtron Technology Co., Ltd.Inventors: Chung W. Ho, Leo Shen
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Patent number: 7514014Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.Type: GrantFiled: April 11, 2000Date of Patent: April 7, 2009Assignee: United Microelectronics CorporationInventors: Chih-Chien Liu, Ta-Shan Tseng, W. B. Shieh, J. Y. Wu, Water Lur, Shih-Wei Sun
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Publication number: 20090008361Abstract: A composition that may be used for cleaning a metal containing conductor layer, such as a copper containing conductor layer, within a microelectronic structure includes an aqueous acid, along with an oxidant material and a passivant material contained within the aqueous acid. The composition does not include an abrasive material. The composition is particularly useful for cleaning a residue from a copper containing conductor layer and an adjoining dielectric layer that provides an aperture for accessing the copper containing conductor layer within a microelectronic structure.Type: ApplicationFiled: July 6, 2007Publication date: January 8, 2009Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, INFINEON TECHNOLOGIES NORTH AMERICA CORP.Inventors: John A. Fitzsimmons, David L. Rath, Shom Ponoth, Michael Beck
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Publication number: 20080257859Abstract: In a method for fabricating a molecule characterization device, there is formed an aperture in a support structure, and electrical contact pads are formed on a selected surface of the support structure for connection to molecular analysis circuitry. Then at the aperture is provided at least one carbon nanotube. An electrically insulating layer is deposited on walls of the aperture to reduce an extent of the aperture and form a smaller aperture, while depositing substantially no insulating layer on a region of the nanotube that is at the aperture.Type: ApplicationFiled: June 16, 2008Publication date: October 23, 2008Applicant: President and Fellows of Harvard CollegeInventors: Jene A. Golovchenko, Daniel Branton
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Patent number: 7422696Abstract: Multicomponent nanorods having segments with differing electronic and/or chemical properties are disclosed. The nanorods can be tailored with high precision to create controlled gaps within the nanorods or to produce diodes or resistors, based upon the identities of the components-making up the segments of the nanorods. Macrostructural composites of these nanorods also are disclosed.Type: GrantFiled: June 30, 2005Date of Patent: September 9, 2008Assignee: Northwestern UniversityInventors: Chad A. Mirkin, Lidong Qin, Sungho Park, Ling Huang, Sung-Wook Chung
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Patent number: 7407596Abstract: A fluxgate sensor is integrated in a printed circuit board. The fluxgate sensor has two bar-type (or rectangular-ring shaped) soft magnetic cores to form a closed magnetic path on a printed circuit board and an excitation coil in the form of a metal film is wound around the two bar-type soft magnetic cores either in a united structure that winds the two bar-type soft magnetic cores altogether, or in a separated structure that winds the two bar-type soft magnetic cores respectively, both in a pattern of number ‘8’. A pick-up coil is mounted on the excitation coil, either winding the two bars altogether, or respectively, in a solenoid pattern. The fluxgate sensor integrated in the printed circuit board can be mass-produced at a cheap manufacturing cost. The fluxgate sensor also can be made compact-sized, and at the same time, is capable of forming a closed-magnetic path.Type: GrantFiled: February 28, 2007Date of Patent: August 5, 2008Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Won-youl Choi, Byeong-cheon Koh, Kyung-won Na, Sang-on Choi, Myung-sam Kang, Keon-yang Park
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Patent number: 7396475Abstract: The present invention provides a method for forming a stepped structure on a substrate that features transferring, into the substrate, an inverse shape of the stepped structure disposed on the substrate.Type: GrantFiled: April 25, 2003Date of Patent: July 8, 2008Assignee: Molecular Imprints, Inc.Inventor: Sidlgata V. Sreenivasan
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Patent number: 7371452Abstract: Disclosed is an article comprising a polymer layer containing a plurality of integral polymer conduit channels that contain at least two layers with at least one comprising a conductive material and the other serving a function beyond protection.Type: GrantFiled: April 28, 2003Date of Patent: May 13, 2008Assignee: Eastman Kodak CompanyInventors: Robert P. Bourdelais, Cheryl J. Kaminsky, Debasis Majumdar
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Patent number: 7294902Abstract: The invention relates to a trench isolation with a self-aligning surface sealing and a fabrication method for said surface sealing. In this case, the surface sealing may have an overlap region of the substrate surface or a receded region into which extends an electrically conductive layer formed on the substrate surface.Type: GrantFiled: July 24, 2002Date of Patent: November 13, 2007Assignee: Infineon Technologies AGInventors: Dietmar Temmler, Andreas Wich-Glasen
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Patent number: 7279110Abstract: A method and apparatus for patterning an array of SLM mirrors with a phase step is disclosed. Additional embodiments of the present invention describe a method for processing a substrate, wherein the processed substrate is used in the apparatus for patterning an array of SLM mirrors with a phase step. The processed substrate is then placed in close proximity to the mirrors and the etching/deposition process is then done through openings in the substrate. In embodiments in which the processed substrate does not have a high enough density of openings, a stepping and repeating process is used in order to achieve complete process coverage of every mirror in an array of SLM mirrors.Type: GrantFiled: December 27, 2004Date of Patent: October 9, 2007Assignee: ASML Holding N.V.Inventor: Stephen Roux
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Patent number: 7204933Abstract: Pillars are formed in a fully integrated thermal inkjet printhead to prevent particles from entering into a nozzle chamber along an ink refill channel. The pillars are formed after a step of applying a thin film structure to a substrate. At one step, pits are etched through the thin film structure. At another step, material for an orifice layer is deposited into the pits. At another step, a firing chamber is etched into the orifice layer. At another step, a trench is etched into the backside of the wafer in the vicinity of the filled pits. The material filling each pit is not removed and remains in place to define the respective pillars. Two or more pillars are formed within the trench for each inkjet nozzle chamber. Alternatively pillars are formed by depositing material into the underside trench and performing photoimaging processes.Type: GrantFiled: February 8, 2006Date of Patent: April 17, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: Naoto Kawamura, David R Thomas, David J Waller, Timothy L Weber
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Patent number: 7141176Abstract: Methods and apparatuses for assembling elements onto a substrate. The surfaces of the elements and/or the substrate are treated and the elements are dispensed over the substrate in a slurry. In one example of the invention, the substrate is exposed to a surface treatment fluid to create a surface on the substrate which has a selected one of a hydrophilic or a hydrophobic nature, and a slurry is dispensed over the substrate. The slurry includes a fluid and a plurality of elements (each of which includes a functional component). Each of the plurality of elements is designed to be received by a receptor region on the substrate. The dispensing of the slurry with the fluid occurs after the substrate is exposed to the surface treatment fluid, and the fluid is the selected one of a hydrophilic or a hydrophobic nature. In another example of the invention, a plurality of elements is exposed to a surface treatment fluid to create surfaces on the elements having a selected one of a hydrophilic or a hydrophobic nature.Type: GrantFiled: July 25, 2002Date of Patent: November 28, 2006Assignee: Alien Technology CorporationInventors: John Stephen Smith, Mark A. Hadley, Gordon S. W. Craig, Paul F. Nealey
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Patent number: 7138170Abstract: Disclosed is an article comprising a polymer sheet containing a plurality of integral polymer conduit channels containing a transparent conductive material in which two or more such channels terminate.Type: GrantFiled: April 28, 2003Date of Patent: November 21, 2006Assignee: Eastman Kodak CompanyInventors: Robert P. Bourdelais, Cheryl J. Kaminsky
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Patent number: 7128844Abstract: A metal layer 12 of aluminum or an aluminum alloy is formed on at least one side of a ceramic substrate 10, and a resist 14 having a predetermined shape is formed on the metal layer 12. Then, an etchant of a mixed solution prepared by mixing ferric chloride with water without adding any acids is used for etching and removing an undesired portion of the metal layer 12 to form a metal circuit 12 on the at least one side of the ceramic substrate 10.Type: GrantFiled: May 27, 2004Date of Patent: October 31, 2006Assignee: Dowa Mining Co., Ltd.Inventors: Nobuyoshi Tsukaguchi, Michihiro Kosaka
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Patent number: 7112285Abstract: Methods are provided for fabricating plated through hole conductive core substrate which eliminate the secondary step of producing a through hole in the dielectric material plugging the core through hole. In one embodiment of the method in accordance with the invention, a two-step lamination process is provided. One side of the conductive core is provided with a dielectric laminate, a portion of which flows into and coats the core through hole wall. Excess dielectric material flows out of the core through hole preventing plugging. Similarly, the other side of the conductive core is provided with a dielectric laminate, a portion of which flows into the core through hole completing the coating of the core through hole wall forming a dielectric liner. The dielectric liner insulates the conductive core through hole wall from a conductive layer deposited onto the dielectric liner forming a plated through hole.Type: GrantFiled: December 5, 2002Date of Patent: September 26, 2006Assignee: Intel CorporationInventor: Kishore K. Chakravorty
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Patent number: 7076870Abstract: A surface-mount package for an oscillator crystal blank is made from a metal sheet substrate. Half-etched cavities are formed on one side of the sheet. The half-etched cavities are filled in with an insulator. The center of the insulator is drilled until metal is reached, leaving insulator on the sidewalls of the resulting drilled via. The bottom of the drilled via is plated with a contact metal such as nickel-gold, and then the entire drilled via is filled in with metal such as copper to form via-metal. An external metal surface-mount pad is formed on the surface of each via-metal. The metal sheet is flipped over, and a larger inner cavity etched through until the contact metal over the via-metal is reached. Conductive epoxy is placed on the contact metal, and electrodes on the crystal blank are attached to conductive epoxy.Type: GrantFiled: August 16, 2004Date of Patent: July 18, 2006Assignee: Pericom Semiconductor Corp.Inventor: Wen-Lo Hsieh
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Patent number: 7052619Abstract: Manufacturing process for manufacturing printed circuit boards from an extruded polymer, comprising the steps:-preparing an electro-conductive plate (10) and form embossments (11) by means of selective engraving on a first side (10a), corresponding to future tracks and depressions (12) corresponding to future inter-track areas;-applying a dielectric substrate material, in a pasty or semi-pasty state, according to a first sheet (20a) obtained by extrusion of a thermal-plastic material, arranging it on said first side (10a), covering said embossments (11) and filling said depressions (12), and subjecting the first sheet (20a) and plate (10) assembly to a predetermined pressure so that the dielectric substrate material completely fills said depressions and encloses said embossments (11), and-on the hardened dielectric substrate, carrying out a second selective engraving on a side opposite the first side (10a), removing the material corresponding to said future inter-track areas.Type: GrantFiled: December 5, 2003Date of Patent: May 30, 2006Assignee: Lear CorporationInventor: Jose Antonio Cubero Pitel
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Patent number: 7030031Abstract: This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a diffusion barrier material. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed. The resultant dual damascene structure may then be metallized.Type: GrantFiled: June 24, 2003Date of Patent: April 18, 2006Assignee: International Business Machines CorporationInventors: William C. Wille, Daniel C. Edelstein, William J. Cote, Peter E. Biolsi, John Fritche, Allan W. Upham
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Patent number: 7025892Abstract: A method is provided for creating gated filament structures for a field emission display. A multi-layer structure is provided that includes a substrate, an insulating layer and a metal gate layer positioned on at least a portion of a top surface of the insulating layer. A plurality of patterned gates are also provided in order to define a plurality of gate apertures on the top surface of the insulating layer. A plurality of spacers are formed in the gate apertures at edges of the patterned gates on the top surface of the insulating layer. The spacers are used as masks for etching the insulating layer and forming a plurality of pores in the insulating layer. The pores are plated with a filament material that extends from the insulating pores, into the gate apertures, and creates a plurality of filaments. The spacers are then removed. The multi-layer structure can further include a conductivity layer on at least a portion of a top surface of the substrate.Type: GrantFiled: January 31, 1995Date of Patent: April 11, 2006Assignee: Candescent Technologies CorporationInventors: David L. Bergeron, John M. Macaulay, Roger W. Barton, Jeffrey D. Morse
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Patent number: 7022609Abstract: A manufacturing method of a semiconductor substrate provided with a through hole electrode is proposed. In accordance with the methods, it is possible to effectively form a through hole electrode in a semiconductor substrate in which a device and a wiring pattern have been already fabricated. This manufacturing method includes the steps of forming a first silicon oxide film 12 on a principal surface of the semiconductor substrate 11, forming a small hole 13 through the semiconductor substrate 11 from the opposite the step to reach to the first silicon oxide film 12, covering the inside of the small hole 13 with the second silicon oxide film 14, forming a first thin metal film 15 and a second thin metal film 16 on the first silicon oxide film 12, partially removing the first silicon oxide film 12 corresponding to the end of the small hole 13, and filling the small hole 13 with the conductive material to form a through hole electrode 17.Type: GrantFiled: August 25, 2003Date of Patent: April 4, 2006Assignees: Fujikura Ltd., Olympus Optical Co., Ltd.Inventors: Satoshi Yamamoto, Takashi Takizawa, Tatsuo Suemasu, Masahiro Katashiro, Hiroshi Miyajima, Kazuya Matsumoto, Toshihiko Isokawa
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Patent number: 7001658Abstract: Disclosed is an article comprising first areas of electrically conductive material and second areas of electrically conductive material raised relative to the first areas and substantially electrically isolated from the first areas, said conductive materials exhibiting a resistivity that averages less than 800 ohm/square.Type: GrantFiled: April 28, 2003Date of Patent: February 21, 2006Assignee: Eastman Kodak CompanyInventors: Robert P. Bourdelais, Cheryl J. Kaminsky, John M. Pochan, James F. Elman
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Patent number: 6878297Abstract: A method for forming a patterned layer of a light-emissive material on a substrate, comprising the steps of providing a holed layer on the surface of the substrate, the holed layer being permanently attached to the substrate and defining a plurality of holes through which the underlying substrate is exposed, and applying a light-emissive material to the surface of the holed layer opposite the substrate and displacing the light-emissive material in fluid form across the surface of the holed layer so as to selectively deposit the material only in the holes of the holed layer.Type: GrantFiled: June 1, 2000Date of Patent: April 12, 2005Assignee: Cambridge Display Technology, LimitedInventors: Paul R. Berger, Stephen Karl Heeks
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Patent number: 6783689Abstract: Pillars are formed in a fully integrated thermal inkjet printhead to prevent particles from entering into a nozzle chamber along an ink refill channel. The pillars are formed after a step of applying a thin film structure to a substrate. At one step, pits are etched through the thin film structure. At another step, material for an orifice layer is deposited into the pits. At another step, a firing chamber is etched into the orifice layer. At another step, a trench is etched into the backside of the wafer in the vicinity of the filled pits. The material filling each pit is not removed and remains in place to define the respective pillars. Two or more pillars are formed within the trench for each inkjet nozzle chamber. Alternatively pillars are formed by depositing material into the underside trench and performing photoimaging processes.Type: GrantFiled: May 10, 2002Date of Patent: August 31, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Naoto Kawamura, David R Thomas, David J Waller, Timothy L. Weber
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Publication number: 20040144749Abstract: Methods of forming material in a gap in a substrate include forming a pattern to define a gap on a substrate. A bottom oxide layer is formed on a surface of the substrate and substantially filling the gap. The bottom oxide layer is etched back inside an opening in the gap to expose side walls of the gap so that a residual bottom oxide layer remains at a bottom of the gap. A top oxide layer is selectively deposited on the residual bottom oxide layer, wherein the top oxide layer is deposited in a first direction toward the opening at a faster rate than in a second direction away from the side walls.Type: ApplicationFiled: December 11, 2003Publication date: July 29, 2004Inventors: Hong-Gun Kim, Kyu-Tae Na, Eun-Kee Hong, Ju-Seon Goo
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Patent number: 6764747Abstract: A circuit board comprising a resin molded article which includes a metal powder coated by an insulation film and a metal conductor which is formed by metal deposition over a circuit pattern drawn by laser beam irradiation on the surface of the resin molded article through electroless plating, and the method of producing the same.Type: GrantFiled: December 27, 2002Date of Patent: July 20, 2004Assignee: Mitsui Chemicals, Inc.Inventors: Toshiya Urakawa, Youhei Suzuki, Kunihiro Inada, Yasuyuki Kawano
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Patent number: 6759082Abstract: The present invention provides a method of manufacturing a metal foil laminated plate comprising the step of forming and attaching a resin porous layer onto a metal foil by a wet coagulating method, wherein a metal foil including a conductive bump having an almost equal height on a film forming side surface is used. The present invention provides a metal foil laminated plate comprising a metal foil including a conductive bump having an almost equal height and a resin porous layer laminated integrally, the conductive bump being exposed. The present invention provides another metal foil laminated plate comprising a metal foil including a conductive bump having an almost equal height, a resin porous layer laminated integrally, and a thermosetting resin impregnated in a hole of the resin porous layer, in which the conductive bump is exposed from the resin porous layer.Type: GrantFiled: May 17, 2002Date of Patent: July 6, 2004Assignee: Nitto Denk CorporationInventors: Kenichi Ikeda, Toshiyuki Kawashima, Nobuharu Tahara
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Patent number: 6759112Abstract: The present invention describes a structure for and a method of forming a first set and a second set of features in a substrate; covering the first and second set of features with a material; forming a third set of features in the material and removing the material to expose the first set of features, leaving the second set of features embedded below the material; measuring post-etch overlay between the first set and the third set of features; and measuring post-develop overlay between the second set and the third set of features.Type: GrantFiled: December 30, 2000Date of Patent: July 6, 2004Assignee: Intel CorporationInventor: Alan Wong
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Patent number: 6660175Abstract: Pillars are formed in a fully integrated thermal inkjet printhead to prevent particles from entering into a nozzle chamber along an ink refill channel. The pillars are formed after a step of applying a thin film structure to a substrate. At one step, pits are etched through the thin film structure. At another step, material for an orifice layer is deposited into the pits. At another step, a firing chamber is etched into the orifice layer. At another step, a trench is etched into the backside of the wafer in the vicinity of the filled pits. The material filling each pit is not removed and remains in place to define the respective pillars. Two or more pillars are formed within the trench for each inkjet nozzle chamber. Alternatively pillars are formed by depositing material into the underside trench and performing photoimaging processes.Type: GrantFiled: September 4, 2002Date of Patent: December 9, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventors: Naoto Kawamura, David R Thomas, David J Waller, Timothy L Weber
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Patent number: 6641744Abstract: Pillars are formed in a fully integrated thermal inkjet printhead to prevent particles from entering into a nozzle chamber along an ink refill channel. The pillars are formed after a step of applying a thin film structure to a substrate. At one step, pits are etched through the thin film structure. At another step, material for an orifice layer is deposited into the pits. At another step, a firing chamber is etched into the orifice layer. At another step, a trench is etched into the backside of the wafer in the vicinity of the filled pits. The material filling each pit is not removed and remains in place to define the respective pillars. Two or more pillars are formed within the trench for each inkjet nozzle chamber. Alternatively pillars are formed by depositing material into the underside trench and performing photoimaging processes.Type: GrantFiled: September 22, 2000Date of Patent: November 4, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventors: Naoto Kawamura, David R Thomas, David J Waller, Timothy L Weber
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Patent number: 6618940Abstract: A high density printed wiring board is prepared by applying an essentially solid material into plated through holes such that the metallized layers within the through hole are unaffected by chemical metal etchants. In this manner, lateral surface metallized layers can exclusively be reduced in thickness by use of said chemical agents. These thinned lateral surface metallized layers are ultimately converted into fine pitch, 25 to 40 microns, circuitry, thereby providing high density boards. Since the through hole wall metallization is unaffected by the etching process, excellent electrical connection between the fine line circuitry is obtained. Various printed wiring board embodiments are also presented.Type: GrantFiled: July 19, 2001Date of Patent: September 16, 2003Assignee: International Business Machines CorporationInventors: Kenneth J. Lubert, Curtis L. Miller, Thomas R. Miller, Robert D. Sebesta, James W. Wilson, Michael Wozniak
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Patent number: 6555015Abstract: Method of manufacturing a multi-layer printed circuit board adapted for reduce interfacial sheer stresses includes a laminate substrate having a top layer forming a first major surface, a middle layer having a predetermined thickness and a bottom layer forming a second major surface opposed to the first major surface. Etch resists are disposed on the first and second surfaces corresponding to reverse images of desired conductor patterns. The first and second surfaces are thereafter etched and the photoresist removed. The laminate substrate is secured via a low modules adhesive layer to a major surface of a base. The middle layer of the laminate substrate is thereafter selectively etched so as to isolate selected portions of the first and second surfaces and to define inner connect regions therebetween having a height equal to the predetermined thickness.Type: GrantFiled: November 9, 2000Date of Patent: April 29, 2003Assignee: Visteon Global Technologies, Inc.Inventors: Daniel Phillip Dailey, Robert Edward Belke, Jr., Jay DeAvis Baker, Achyuta Achari, Myron Lemecha, Michael George Todd
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Patent number: 6555016Abstract: A method of making a multilayer substrate comprising: (a) providing an interlayer circuit board having conductor circuits thereon; (b) forming a dielectric layer on the interlayer circuit board; (c) mechanical drilling (or laser drilling) through the dielectric layer to the conductor circuits at predetermined positions thereof so as to form blind-vias; (d) electrolessly plating a conductive layer on the surface of the dielectric layer and the blind-vias; (e) forming an etch resist on the conductive layer, followed by formation of outer conductor circuits on the conductive layer by selectively etching; and (f) removing the etching resist. Since the blind-vias of the present invention are formed by drilling instead of photosensitive polymer technology, the processing steps are minimized thereby significantly improving the production efficiency. Furthermore, since the mechanical drilling (or laser drilling) has better accuracy, the blind-vias can be formed with better accuracy.Type: GrantFiled: December 28, 2000Date of Patent: April 29, 2003Assignees: Advanced Semiconductor Engineering, Inc., Ase Material Inc.Inventor: Kuei-Yu Lai
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Patent number: 6527964Abstract: Methods and apparatuses for assembling elements onto a substrate. The surfaces of the elements and/or the substrate are treated and the elements are dispensed over the substrate in a slurry. In one example of the invention, the substrate is exposed to a surface treatment fluid to create a surface on the substrate which has a selected one of a hydrophilic or a hydrophobic nature, and a slurry is dispensed over the substrate. The slurry includes a fluid and a plurality of elements (each of which includes a functional component). Each of the plurality of elements is designed to be received by a receptor region on the substrate. The dispensing of the slurry with the fluid occurs after the substrate is exposed to the surface treatment fluid, and the fluid is the selected one of a hydrophilic or a hydrophobic nature. In another example of the invention, a plurality of elements is exposed to a surface treatment fluid to create surfaces on the elements having a selected one of a hydrophilic or a hydrophobic nature.Type: GrantFiled: November 2, 1999Date of Patent: March 4, 2003Assignee: Alien Technology CorporationInventors: John Stephen Smith, Mark A. Hadley, Gordon S. W. Craig, Paul F. Nealey
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Patent number: 6495053Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26, and which includes grooves or troughs 20, 22 which are effective to selectively entrap liquefied adhesive material, thereby substantially preventing the adhesive material from entering the apertures 26.Type: GrantFiled: August 30, 2000Date of Patent: December 17, 2002Assignee: Visteon Global Tech, Inc.Inventors: Lawrence Leroy Kneisel, Mohan R. Paruchuri, Vivek Amir Jalrazbhoy, Vladimir Stoica
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Patent number: 6461527Abstract: A method for fabricating a flexible printed circuit board with access on both sides includes the steps of applying a metallic conductor track sheet to a base sheet and patterning the metallic conductor track sheet in order to produce conductor tracks. A conductor track covering with first contact-making cutouts is applied over the conductor tracks. Second contact-making cutouts are produced in the base sheet material by locally removing the base sheet through the use of laser irradiation. As an alternative, the first contact-making cutouts as well as the second contact-making cutouts can be produced by removing material with a laser.Type: GrantFiled: June 26, 2000Date of Patent: October 8, 2002Assignee: Siemens AktiengesellschaftInventors: Detlef Haupt, Frank Franzen
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Patent number: 6436610Abstract: A maskless exposure system for selectively exposing a photosensitive work surface, such as a photoresist layer, includes a semiconductor substrate having an elongated aperture. A series of shutters and associated guides are formed upon the substrate using conventional wafer processing methods. The shutters move between a first position covering the aperture and a second position exposing the aperture. A corresponding series of computer-controlled actuators, in the form of electromagnetic coils, cooperate with the shutters for selectively sliding each shutter between its first and second positions. A light beam is directed toward the aperture, and the shutters create a patterned light beam exiting the aperture. A computer-controlled stepper is synchronized with the shutter actuators and adjusts the relationship between the patterned light beam and the photosensitive work surface to direct the patterned light beam at different portions of the work material.Type: GrantFiled: May 25, 2001Date of Patent: August 20, 2002Inventor: James E. Sanford
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Patent number: 6429755Abstract: Integrated circuit fabrication technique for constructing novel MEMS devices, specifically band-pass filter resonators, in a manner compatible with current integrated circuit processing, and completely encapsulated to optimize performance and eliminate environmental corrosion. The final devices may be constructed of single-crystal silicon, eliminating the mechanical problems associated with using polycrystalline or amorphous materials. However, other materials may be used for the resonator. The final MEMS device lies below the substrate surface, enabling further processing of the integrated circuit, without protruding structures. The MEMS device is about the size of a SRAM cell, and may be easily incorporated into existing integrated circuit chips. The natural frequency of the device may be altered with post-processing or electronically controlled using voltages and currents compatible with integrated circuits.Type: GrantFiled: January 30, 2001Date of Patent: August 6, 2002Assignee: International Business Machines CorporationInventors: James L. Speidell, James F. Ziegler
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Patent number: 6426011Abstract: A method of making a printed circuit board whereby a fine wiring pattern can be formed. A through hole is formed in a substrate, both surfaces of the substrate being covered with copper foil. The substrate is treated with a catalyst and plated with copper. The through hole is filled with an insulating material, and the copper layer on the substrate is etched so that the catalyst layer is not exposed, leaving a thinned copper layer. Then, the substrate surfaces are ground and leveled by removing any projecting insulating material. Thereafter, another copper layer is deposited on the surface of the substrate, including surface regions on the fill material and is circuitized to form a wiring pattern. Since the catalyst layer is not exposed when the copper layer on the substrate is thinned, a fine wiring pattern can be obtained without the problem of subsequent peeling of the wiring conductors, or the entrapment of air.Type: GrantFiled: March 31, 2000Date of Patent: July 30, 2002Assignee: International Business Machines CorporationInventor: Takashi Katoh
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Publication number: 20020094493Abstract: A method of forming a partial reverse active mask. A mask pattern comprising a large active region pattern with an original dimension and a small active region pattern is provided. The large active region pattern and the small active region pattern are shrunk until the small active region pattern disappears. The large active region pattern enlarged to a dimension slightly smaller than the original dimension.Type: ApplicationFiled: November 21, 2001Publication date: July 18, 2002Inventors: Coming Chen, Juan-Yuan Wu, Water Lur
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Patent number: 6402970Abstract: A method of manufacturing a support circuit includes providing a conductive layer with top and bottom surfaces, providing a top etch mask on the top surface that includes an opening that exposes a portion of the top surface, providing a bottom etch mask on the bottom surface that includes an opening that exposes a portion of the bottom surface, applying an etch to the exposed portion of the top surface through the opening in the top etch mask, thereby etching partially but not completely through the conductive layer and forming a recessed portion in the conductive layer below the top surface, forming an insulative base on the recessed portion without forming the insulative base on the top surface, and applying an etch to the exposed portion of the bottom surface through the opening in the bottom etch mask, thereby forming a through-hole in the recessed portion that extends to and is covered by the insulative base.Type: GrantFiled: August 22, 2000Date of Patent: June 11, 2002Inventor: Charles W. C. Lin
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Patent number: 6396001Abstract: A printed circuit board includes a rectangular, insulating substrate and a conductive land formed on the substrate. The land is arranged near a selected one of the longitudinal edges of the substrate. An L-shaped terminal is mounted on the substrate, so that its longer horizontal portion overlaps the land, while its shorter bent portion is engaged with a positioning groove formed in the selected longitudinal edge of the substrate. The land is caused to protrude from the overlapping horizontal portion of the terminal toward the opposite longitudinal edge of the substrate.Type: GrantFiled: November 13, 2000Date of Patent: May 28, 2002Assignee: Rohm Co. Ltd.Inventor: Satoshi Nakamura