Removing At Least One Of The Self-sustaining Preforms Or A Portion Thereof Patents (Class 216/36)
  • Patent number: 6872319
    Abstract: A MEMS fabrication process eliminates through-wafer etching, minimizes the thickness of silicon device layers and the required etch times, provides exceptionally precise layer to layer alignment, does not require a wet etch to release the moveable device structure, employs a supporting substrate having no device features on one side, and utilizes low-temperature metal-metal bonding which is relatively insensitive to environmental particulates. This process provided almost 100% yield of scanning micromirror devices exhibiting scanning over a 12° optical range and a mechanical angle of ±3° at a high resonant frequency of 2.5 kHz with an operating voltage of only 20 VDC.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: March 29, 2005
    Assignee: Rockwell Scientific Licensing, LLC
    Inventor: Chialun Tsai
  • Publication number: 20040265531
    Abstract: A slider assembly is provided comprising a plurality of sliders bonded by a debondable solid encapsulant. The solid encapsulant is comprised of a silicon-based polymer. Each slider has a surface that is free from the encapsulant. The encapsulant-free surfaces are coplanar to each other. Also provided are methods for forming the assembly and methods for patterning a slider surface using the encapsulant.
    Type: Application
    Filed: June 30, 2003
    Publication date: December 30, 2004
    Inventors: Dennis R. McKean, Robert D. Miller, Willi Volksen, James L. Hedrick, Craig J. Hawker, Phillip J. Brock, Dan J. Dawson, Teddie P. Magbitang, Michael W. Chaw, Richard I. Palmisano
  • Patent number: 6793830
    Abstract: A method for forming a microstructure from a substrate is provided. The method includes providing a monocrystalline substrate having a (100) orientation and subjecting a first portion of the substrate to ion bombardment to effect ion implantation to a desired penetration depth. A second portion of the substrate is etched to a depth at least as great as the desired penetration depth. The substrate then is thermally treated to form a microstructure at a surface of the substrate and to effect at least partial separation between the microstructure and the substrate.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: September 21, 2004
    Assignee: Medtronic, Inc.
    Inventors: Michael F. Mattes, Ralph B. Danzl
  • Patent number: 6793831
    Abstract: A method for fabricating devices in a pre-assembled state comprising forming plural laminae, registering the laminae, and bonding the laminae one to another is described. The plural laminae contain the substructures and structures of the device. The substructures are coupled to structures and other substructures by fixture bridges in the pre-assembled state. The substructures of the device are dissociated by eliminating the fixture bridges. The plural laminae are registered and bonded to form the device either before or after the fixture bridges are eliminated. The fixture bridges can be eliminated in a variety of ways, including vaporization by electrical current, chemical dissolution, or thermochemical dissociation. One method to selectively bond the laminae together is by microprojection welding. Microprojection welding comprises forming laminae with projections that extend from at least one planar surface of the lamina.
    Type: Grant
    Filed: August 5, 1999
    Date of Patent: September 21, 2004
    Assignee: State of Oregon acting by and through the State Board of Higher Education on behalf of Oregon State University
    Inventors: Brian Kevin Paul, Richard Budd Peterson, Tyson Jedd Terhaar
  • Patent number: 6758983
    Abstract: A staggered torsional electrostatic combdrive includes a stationary combteeth assembly and a moving combteeth assembly with a mirror and a torsional hinge. The moving combteeth assembly is positioned entirely above the stationary combteeth assembly by a predetermined vertical displacement during a combdrive resting state. A method of fabricating the staggered torsional electrostatic combdrive includes the step of deep trench etching a stationary combteeth assembly in a first wafer. A second wafer is bonded to the first wafer to form a sandwich including the first wafer, an oxide layer, and the second wafer. A moving combteeth assembly is formed in the second wafer. The moving combteeth assembly includes a mirror and a torsional hinge. The moving combteeth assembly is separated from the first wafer by the oxide layer. The oxide layer is subsequently removed to release the staggered torsional electrostatic combdrive.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: July 6, 2004
    Assignee: The Regents of the University of California
    Inventors: Robert A. Conant, Jocelyn T. Nee, Kam-Yin Lau, Richard S. Muller
  • Patent number: 6742832
    Abstract: A vehicle bed assembly 10 has a floor pan 18, a front wall 20, and substantially identical side walls 14, 16. The front wall 20 and the side walls 14, 16 are coupled to the floor pan 18. The vehicle bed assembly 10 further includes a rear wall 22 which is deployed upon a tailgate 21 which is selectively coupled to the floor pan 18, and a pair of substantially identical top rail members 100 which overlay and receive a unique one of the side walls 14, 16 and a bracket 210 which overlays and receives the front wall 20 and which is coupled to the top rail member 100 by a pair of end cap members 122. Particularly, the end cap members 122 and the top rail members 100 cooperatively provide a direct load path from any location on each of the side walls 14, 16 to the bracket 210 which may be coupled to a portion of the vehicle 12, thereby reducing the likelihood of damage to the sidewalls 14, 16 and the front wall 20.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: June 1, 2004
    Assignee: Ford Global Technologies, LLC
    Inventors: Peter Miskech, David Gary Dahlstrom, Keith Alan Kuzmich, Earl Ray Dover, Karen Diane Wallag, James Matthew Posa, Joseph Paul Tekelly
  • Patent number: 6719914
    Abstract: The present invention relates to a method of manufacturing a piezoelectric device of high sensitivity using direct bonded quartz plate. To achieve this object, the invented method comprises the steps of covalently bonding a plurality of quartz plates, dry etching the bonded quartz plates with plasma from one side of its surfaces down to a bonded plane, and dry etching with plasma thereafter from the other side of the surfaces.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: April 13, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaya Nakatani, Michihiko Hayashi, Hirofumi Tajika
  • Patent number: 6616854
    Abstract: A donor substrate (12) which is patterned to include a donor mesa (18) is bonded to a receiving substrate (20). In a one embodiment, a bulk portion of the donor substrate is removed while leaving a transferred layer (26) bonded to the receiving substrate. The transferred layer is a layer of material transferred from the donor mesa. A portion of receiving substrate can be processed to form a recess (27, 28, or 32) to receive the donor mesa. Alternatively, the transferred layer can be formed over a dummy feature (46) formed on the receiving substrate, either with or without the use of mesas on the donor substrate. In a preferred embodiment, the transferred layer is used to form an optical device such as a photodetector in a semiconductor device. With the invention, bonding can be achieve despite having a non-planar surface on the receiving substrate.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: September 9, 2003
    Assignee: Motorola, Inc.
    Inventors: Robert E. Jones, Sebastian Csutak
  • Patent number: 6582615
    Abstract: This invention relates to a relatively thin cladded graphic arts impression graphic arts impression die plate (20) having a steel layer (22) which is integral throughout the extent thereof with a layer of copper (24) or bronze. A relieved design-defining surface may be formed in the copper or bronze layer by a chemical etching process or by chemical milling. The graphic arts impression die plate may be mounted on a magnetic support member (28) to present an assembly which increases the thickness of the die assembly sufficiently to permit use thereof on standard stamping and embossing equipment without modification of the die-supporting chase. The magnetic support member (28) has a plurality of pairs of permanent magnets (33, 35) each pair of which is embedded within a respective cavity (32) and that are magnetically bridged by a steel plate 36.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: June 24, 2003
    Assignee: Universal Engraving. Inc.
    Inventors: Glenn E. Hutchison, Todd E. Scholtz
  • Patent number: 6582614
    Abstract: This invention relates to a relatively thin cladded graphic arts impression graphic arts impression die plate (20) having a steel layer (22) which is integral throughout the extent thereof with a layer of copper (24) or bronze. A relieved design-defining surface may be formed in the copper or bronze layer by a chemical etching process or by chemical milling. In the case of chemical etching of the graphic arts impression die plate (20), a design-defining layer of photo-resist is applied to the outer surface of the copper layer (24) or the bronze layer and the relieved design is formed in the copper or bronze layer using a conventional ferric chloride etching solution. The etched graphic arts impression die plate may be mounted on an etchant-resistant backing or magnetic support member (28) to present an assembly which increases the thickness of the die assembly sufficiently to permit use thereof on standard stamping and embossing equipment without modification of the die-supporting chase.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: June 24, 2003
    Assignee: Universal Engraving, Inc.
    Inventors: Glenn E. Hutchison, Todd E. Scholtz
  • Patent number: 6572781
    Abstract: A sheet including lead regions with conductors and a main region surrounding the lead regions is formed on the front surface of a microelectronic element such as a wafer, or assembled thereto, so that the conductors are connected to contacts on the microelectronic element. After the sheet is in place, the sheet is eroded to form gaps partially bounding the lead regions, leaving tip ends of the lead regions moveable with respect to the main region. The tip ends of the lead regions, or the main region, is lifted away from the microelectronic element, thus bending the tip ends away from the main region. Because the gaps are not formed until after the conductors are connected to the contacts, the connecting step is simplified.
    Type: Grant
    Filed: May 16, 2001
    Date of Patent: June 3, 2003
    Assignee: Tessera, Inc.
    Inventor: Belgacem Haba
  • Publication number: 20030071015
    Abstract: A two-step method of releasing microelectromechanical devices from a substrate is disclosed. The first step comprises isotropically etching a silicon oxide layer sandwiched between two silicon-containing layers with a gaseous hydrogen fluoride-water mixture, the overlying silicon layer to be separated from the underlying silicon layer or substrate for a time sufficient to form an opening but not to release the overlying layer, and the second step comprises adding a drying agent to substitute for moisture remaining in the opening and to dissolve away any residues in the opening that can cause stiction.
    Type: Application
    Filed: October 8, 2002
    Publication date: April 17, 2003
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Jeffrey D. Chinn, Sofiane Soukane
  • Patent number: 6495053
    Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26, and which includes grooves or troughs 20, 22 which are effective to selectively entrap liquefied adhesive material, thereby substantially preventing the adhesive material from entering the apertures 26.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: December 17, 2002
    Assignee: Visteon Global Tech, Inc.
    Inventors: Lawrence Leroy Kneisel, Mohan R. Paruchuri, Vivek Amir Jalrazbhoy, Vladimir Stoica
  • Patent number: 6406636
    Abstract: Wafer-to-wafer bonding using, e.g., solder metal bonding, glass bonding or polymer (adhesive) bonding is improved by profiling one or both of the wafer surfaces being bonded to define microstructures therein. Profiling means providing other than the conventional planar bonding surface to define cavities therein. The bonding material fills the cavities in the microstructures. For instance, a system of ridges and trenches (e.g. in cross-section vertical, slanted, key-holed shaped, or diamond-shaped) are microstructures that increase the surface area of the wafers to which the bonding material can adhere. Use of the key-hole shaped or diamond-shaped profile having a negative slope at the trench interior substantially increases the bonding force.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: June 18, 2002
    Assignee: MegaSense, Inc.
    Inventor: Vladimir I. Vaganov
  • Patent number: 6393685
    Abstract: A wafer level interconnecting mechanism for assembling and packaging multiple MEMS devices (modules), using microfabricated, interlocking, mechanical joints to interconnect different modules and to create miniature devices. Various devices can be fabricated using these joints, including fiber-optic switches, xyz translational stages, push-n-lock locking mechanisms, slide-n-lock locking mechanisms, t-locking joints, fluidic interconnects, on/off valves, optical fiber couplers with xy adjustments, specimen holders, and membrane stops.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: May 28, 2002
    Assignee: The Regents of the University of California
    Inventor: Scott D. Collins
  • Patent number: 6387822
    Abstract: A method and apparatus for resist strip. Wafers (108) with a patterned resist formed thereon are placed in a carrier (104) in a process chamber (102). An ozonated deionized water mist (120) is sprayed on the surface of wafer (108). The ozonated deionized water mist (120) strips the resist and removes the resist residue without the use of hazardous chemicals. The ozonated deionized water mist (120) may be formed in an atomizer that mixes deionized water (116) with ozone (118). The ozonated deionized water mist (120) is then sprayed onto the wafers (108) while the wafers are being rotated.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: May 14, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Neal T. Murphy, Claire Ching-Shan Jung, Danny F. Mathews
  • Patent number: 6350387
    Abstract: A multilayer rigid flex printed circuit board wherein the board laminate comprises a basestock composite containing a flexible core, formed by laminating a first conductive layer to a flexible insulator layer, a second insulator layer affixed to the basestock, said second insulator layer having a cutout region proximate to the flexible core of the basestock composite to expose a portion of said first conducting layer on said flexible core, a second conductive layer attached to said second insulator layer said second conductive layer having a cutout region proximate to the flexible core of the basestock composite, and a photo-imageable soldermask applied to the exposed portion said first conducting layer, and to the second conductive layer, wherein said photoimageable soldermask allows for photo definition of openings on the conductive layers to which it is applied.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: February 26, 2002
    Assignee: Teledyne Industries, Inc.
    Inventors: A. Roland Caron, Sandra L. Jean, James E. Keating, Robert S. Larmouth, Lee J. Millette
  • Publication number: 20020020053
    Abstract: This invention uses large surface to volume ratio materials for separation, release layer, and sacrificial material applications. The invention outlines the material concept, application designs, and fabrication methodologies. The invention is demonstrated using deposited column/void network materials as examples of large surface to volume ratio materials. In a number of the specific applications discussed, it is shown that it is advantageous to create structures on a laminate on a mother substrate and then, using the separation layer material approach, to separate this laminate from the mother substrate using the present separation scheme. It is also shown that the present materials have excellent release layer utility. In a number of applications it is also shown how the approach can be used to uniquely form cavities, channels, air-gaps, and related structures in or on various substrates.
    Type: Application
    Filed: April 17, 2001
    Publication date: February 21, 2002
    Inventors: Stephen J. Fonash, Wook Jun Nam, Youngchul Lee, Kyuhwan Chang, Daniel J. Hayes, A. Kaan Kalkan, Sanghoon Bae
  • Patent number: 6341557
    Abstract: This invention relates to a relatively thin cladded graphic arts impression graphic arts impression die plate (20) having a steel layer (22) which is integral throughout the extent thereof with a layer of copper (24) or bronze. A relieved design-defining surface may be formed in the copper or bronze layer by a chemical etching process or by chemical milling. In the case of chemical etching of the graphic arts impression die plate (20), a design-defining layer of photo-resist is applied to the outer surface of the copper layer (24) or the bronze layer and the relieved design is formed in the copper or bronze layer using a conventional ferric chloride etching solution. The etched graphic arts impression die plate may be mounted on an etchant-resistant backing or magnetic support member (28) to present an assembly which increases the thickness of the die assembly sufficiently to permit use thereof on standard stamping and embossing equipment without modification of the die-supporting chase.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: January 29, 2002
    Assignee: Universal Engraving, Inc.
    Inventors: Glenn E. Hutchison, Todd E. Scholtz
  • Patent number: 6337028
    Abstract: A process for forming an inorganic material layer pattern on a substrate. The process includes the steps of transferring an inorganic powder dispersed paste layer supported on a support film to the surface of the substrate to form the inorganic powder dispersed paste layer on the substrate; forming a resist film on the inorganic powder dispersed paste layer transferred to the surface of the substrate; exposing the resist film to light through a mask to form a latent image of a resist pattern; developing the exposed resist film to form the resist pattern; etching exposed portions of the inorganic powder dispersed paste layer to form an inorganic powder dispersed paste layer pattern corresponding to the resist pattern; and baking the pattern to form an inorganic material layer pattern.
    Type: Grant
    Filed: November 10, 1998
    Date of Patent: January 8, 2002
    Assignee: JSR Corporation
    Inventors: Hideaki Masuko, Tadahiko Udagawa, Hiroaki Nemoto, Nobuo Bessho
  • Patent number: 6299785
    Abstract: A process for the preparation of an electrode, which comprises: (1) transferring a conductive paste layer supported on a base film to a substrate to form the conductive paste layer on the substrate; (2) forming a resist film on the conductive paste layer transferred to the substrate; (3) exposing the resist film through a mask to form a resist pattern latent image; (4) developing the exposed resist film to form a resist pattern; (5) etching exposed portions of the conductive paste layer to form a conductive paste layer pattern corresponding to the resist pattern; and (6) thermosetting the pattern to form a conductive layer pattern.
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: October 9, 2001
    Assignee: JSR Corporation
    Inventors: Tsutomu Shimokawa, Hideaki Masuko, Hiroaki Nemoto, Nobuo Bessho
  • Publication number: 20010023010
    Abstract: A substrate on which a plurality of thin films having a plurality of cross-sections corresponding to the cross-section of a micro-structure are formed is placed on a substrate holder. The substrate holder is elevated to bond a thin film formed on the substrate to the surface of a stage, and by lowering the substrate holder, the thin film is separated from the substrate and transferred to the stage side. The transfer process is repeated to laminate a plurality of thin films on the stage and to form the micro-structure. Accordingly, there are provided a micro-structure having high dimensional precision, especially high resolution in the lamination direction, which can be manufactured from a metal or an insulator such as ceramics and can be manufactured in the combined form of structural elements together, and a manufacturing method and an apparatus thereof.
    Type: Application
    Filed: February 26, 2001
    Publication date: September 20, 2001
    Applicant: Fuji Xerox Co. Ltd.
    Inventors: Takayuki Yamada, Mutsuya Takahashi, Masaki Nagata
  • Publication number: 20010017287
    Abstract: A micromachined fluid handling device having improved properties. The valve is made of reinforced parylene. A heater heats a fluid to expand the fluid. The heater is formed on unsupported silicon nitride to reduce the power. The device can be used to form a valve or a pump. Another embodiment forms a composite silicone/parylene membrane. Another feature uses a valve seat that has concentric grooves for better sealing operation.
    Type: Application
    Filed: December 22, 2000
    Publication date: August 30, 2001
    Applicant: California Institute of Technology, a California corportion
    Inventors: Xu-Chong Tai, Xing Yang, Charles Grosjean, Xuan-Qi Wang
  • Publication number: 20010010303
    Abstract: A multilayer rigid flex printed circuit board wherein the board laminate comprises a basestock composite containing a flexible core, formed by laminating a first conductive layer to a flexible insulator layer, a second insulator layer affixed to the basestock, said second insulator layer having a cutout region proximate to the flexible core of the basestock composite to expose a portion of said first conducting layer on said flexible core, a second conductive layer attached to said second insulator layer said second conductive layer having a cutout region proximate to the flexible core of the basestock composite, and a photo-imageable soldermask applied to the exposed portion said first conducting layer, and to the second conductive layer, wherein said photoimageable soldermask allows for photo definition of openings on the conductive layers to which it is applied.
    Type: Application
    Filed: March 1, 1999
    Publication date: August 2, 2001
    Inventors: A. ROLAND CARON, SANDRA L. JEAN, JAMES E. KEATING, ROBERT S. LARMOUTH, LEE J. MILLETTE
  • Patent number: 6254794
    Abstract: A method for preparing a semiconductor member comprises: forming a substrate having a non-porous silicon monocrystalline layer and a porous silicon layer; bonding another substrate having a surface made of an insulating material to the surface of the monocrystalline layer; and etching to remove the porous silicon layer by immersing in an etching solution.
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: July 3, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kiyofumi Sakaguchi, Takao Yonehara, Nobuhiko Sato
  • Patent number: 6245249
    Abstract: A substrate on which a plurality of thin films having a plurality of cross-sections corresponding to the cross-section of a micro-structure are formed is placed on a substrate holder. The substrate holder is elevated to bond a thin film formed on the substrate to the surface of a stage, and by lowering the substrate holder, the thin film is separated from the substrate and transferred to the stage side. The transfer process is repeated to laminate a plurality of thin films on the stage and to form the micro-structure. Accordingly, there are provided a micro-structure having high dimensional precision, especially high resolution in the lamination direction, which can be manufactured from a metal or an insulator such as ceramics and can be manufactured in the combined form of structural elements together, and a manufacturing method and an apparatus thereof.
    Type: Grant
    Filed: April 22, 1998
    Date of Patent: June 12, 2001
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Takayuki Yamada, Mutsuya Takahashi, Masaki Nagata
  • Patent number: 6238586
    Abstract: A method for preparing a semiconductor member comprises: forming a substrate having a non-porous silicon monocrystalline layer and a porous silicon layer; bonding another substrate having a surface made of an insulating material to the surface of the monocrystalline layer; and etching to remove the porous silicon layer by immersing in an etching solution.
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: May 29, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kiyofumi Sakaguchi, Takao Yonehara, Nobuhiko Sato
  • Patent number: 6197208
    Abstract: A method for contacting at least one printed circuit board or at least one punched grid and at least one hybrid includes the steps of: forming contact elements in a contacting foil, positioning the contacting foil over the hybrid in such a way that the contact elements are arranged at preselected positions between the printed circuit traces of the hybrid and the printed circuit traces of the printed circuit board, and etching away at least a portion of the contacting foil, such that the contact elements are at least partially freely accessible.
    Type: Grant
    Filed: January 7, 1999
    Date of Patent: March 6, 2001
    Assignee: Robert Bosch GmbH
    Inventor: Thomas Wiesa
  • Patent number: 6159385
    Abstract: The present invention relates to a fabrication process relating to a fabrication process for manufacture of micro-electromechanical (MEM) devices such as cantilever supported beams. This fabrication process requires only two lithographic masking steps and offers moveable electromechanical devices with high electrical isolation. A preferred embodiment of the process uses electrically insulating glass substrate as the carrier substrate and single crystal silicon as the MEM component material. The process further includes deposition of an optional layer of insulating material such as silicon dioxide on top of a layer of doped silicon grown on a silicon substrate. The silicon dioxide is epoxy bonded to the glass substrate to create a silicon--silicon dioxide-epoxy-glass structure. The silicon is patterned using anisotropic plasma dry etching techniques.
    Type: Grant
    Filed: May 8, 1998
    Date of Patent: December 12, 2000
    Assignee: Rockwell Technologies, LLC
    Inventors: Jun J. Yao, Robert J. Anderson
  • Patent number: 6110393
    Abstract: A class of epoxy bond and stop etch (EBASE) microelectronic fabrication techniques is disclosed. The essence of such techniques is to grow circuit components on top of a stop etch layer grown on a first substrate. The first substrate and a host substrate are then bonded together so that the circuit components are attached to the host substrate by the bonding agent. The first substrate is then removed, e.g., by a chemical or physical etching process to which the stop etch layer is resistant. EBASE fabrication methods allow access to regions of a device structure which are usually blocked by the presence of a substrate, and are of particular utility in the fabrication of ultrafast electronic and optoelectronic devices and circuits.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: August 29, 2000
    Assignee: Sandia Corporation
    Inventors: Jerry A. Simmons, Mark V. Weckwerth, Wes E. Baca
  • Patent number: 6099745
    Abstract: In a rigid/flex circuit board and fabricating process, patterns of electrical traces are formed by etching conductive layers on outer surfaces of a flexible multi-layer circuit structure. A protective barrier material is deposited on the etched traces using an "electroless" process, such as immersion of the flexible circuit board in an aqueous solution containing ionic tin. The protective barrier material adheres to and encapsulates the copper traces. An outer circuit structure including a bondfilm of epoxy-impregnated fiberglass ("prepreg" bondfilm) and a copper foil layer is laminated onto the flexible circuit structure. The prepreg bondfilm has a window area removed by routing or an equivalent process prior to being laminated to the flexible structure. The window area defines a flex area of the rigid/flex circuit board that will be relatively flexible.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: August 8, 2000
    Assignee: Parlex Corporation
    Inventors: Darryl McKenney, Arthur Demaso, Craig Wilson
  • Patent number: 6090688
    Abstract: A method for fabricating an SOI substrate is provided, which has an active substrate formed as a thin film. The method comprises the steps of: using a both-side polishing apparatus to polish both sides of a supporting substrate 1; bonding an active substrate 2 onto the supporting substrate 1. to form a bonded-wafer; removing an unbonded portion formed at the circumference of the bonded-wafer; flat grinding the active substrate 2 to reduce the thickness thereof; etching the active substrate 2 by spin etching; and processing the active substrate to be a thin film by PACE processing.
    Type: Grant
    Filed: November 15, 1996
    Date of Patent: July 18, 2000
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Tadashi Ogawa, Akihiro Ishii, Yuichi Nakayoshi
  • Patent number: 5993677
    Abstract: A thin film is transferred from an initial substrate onto a final substrate. The process includes the following successive stages: joining of the thin film (112) onto a handle substrate (120) comprising a cleavage zone, elimination of the initial substrate, joining of the thin film (112) with a final substrate (132), and cleavage of the handle substrate (120) following the cleavage zone. The cleavage zone includes a film of micro-bubbles formed by ion implantation. The invention has, in particular, applications in the fabrication of three-dimensional structures of integrated circuits.
    Type: Grant
    Filed: January 10, 1997
    Date of Patent: November 30, 1999
    Assignee: Commissariat a L'Energie Atomique
    Inventors: Beatrice Biasse, Michel Bruel, Marc Zussy
  • Patent number: 5981400
    Abstract: Compliant universal (CU) substrates and techniques for forming the same facilitate growth of epitaxial layers comprised of materials which are highly lattice mismatched with the substrate material. The CU substrates employ very thin (e.g., 1-20 nm or less) substrate layers which are loosely bonded to a thick bulk material base layer. Because of the loose bonding, the bonding energy of the atoms in the thin substrate layer is reduced, thus greatly increasing the flexibility of the thin substrate layer. This enables the substrate layer to absorb strain or stress imparted during the growth of lattice mismatched epitaxial layers, thus avoiding the formation of defects in the epitaxial layers. The "loose" bonding of the thin substrate layer to the base layer can be achieved in any of a number of ways. First, the thin substrate layer can be bonded at an angle relative to the base layer so that screw dislocations form which provide the desired reduction in bonding energy and increase in flexibility.
    Type: Grant
    Filed: September 18, 1997
    Date of Patent: November 9, 1999
    Assignee: Cornell Research Foundation, Inc.
    Inventor: Yu-Hwa Lo
  • Patent number: 5948282
    Abstract: A process for transfer printing papers having a flip-flop effect is disclosed. A substrate consisting of a base paper, a glue, a transparent tape, a transparent resin, a hydrophilic paint and a metal layer is manufactured by a vapor deposition method. A flip-flop ink having a predetermined pattern is printed on the substrate. The metal layer which is not covered by the ink is etched by an alkaline solution. The alkaline solution is neutralized by an acid solution. The substrate is washed and then dried so that the transfer printing papers having a flip-flop effect are obtained.
    Type: Grant
    Filed: September 24, 1997
    Date of Patent: September 7, 1999
    Inventor: Sheng-Chih Hu
  • Patent number: 5932113
    Abstract: A method for preparing the air bearing surface of a slider for etch patterning including the steps of applying a first thin film to a carrier, applying a second thin film to the carrier, the first thin film and the second thin film separated by a recess, each of the first and second thin films having respective first and second air bearing surfaces, applying an adhesive film over the first and second thin films, depositing a fluid in the recess, the fluid held in the recess by the adhesive film, curing the fluid, and removing the adhesive film. The method of the invention may also include coating the first and second air bearing surfaces with an etch mask, developing the etch mask, and patterning the first and second air bearing surfaces.
    Type: Grant
    Filed: September 4, 1997
    Date of Patent: August 3, 1999
    Assignee: International Business Machines Corporation
    Inventors: Bulent Nihat Kurdi, Dennis R. McKean, Eric Keith Wong
  • Patent number: 5863829
    Abstract: The present invention provides a process for fabricating an SOI substrate with no peripheral scratches and with enhanced fabrication efficiency. The present process includes bonding a semiconductor wafer of an active substrate 1 and a semiconductor base wafer 2 to form a bonded wafer 4; surface-grinding the active substrate 1; spin etching the surface-ground active substrate 1; and PACE processing the etched active substrate 1 to form the active substrate into a thin film and simultaneously, to remove the non-bonded peripheral portion of the bonded wafer 4.
    Type: Grant
    Filed: November 13, 1996
    Date of Patent: January 26, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Yuichi Nakayoshi, Hiroaki Yamamoto, Akihiro Ishii
  • Patent number: 5822850
    Abstract: A supporting member or first synthetic resin sheet with conductive bumps disposed at predetermined positions are superposed on a second synthetic resin sheet under the condition that the resin component of the second synthetic resin sheet is plastic deformed or the temperature thereof exceeds a glass transition temperature so that the conductive bumps are pierced into the second synthetic resin sheet. In other words, the conductive bumps are pierced vertically into the second synthetic resin sheet so as to form through-type conducive lead portions exposed to the first (supporting substrate) and second synthetic resin sheets. The through-type conductive lead portions are used to electrically connect electric devices and circuit and to connect wiring pattern layers. The conductive bumps can be precisely and densely formed and disposed by printing method or plating method. The conductive bumps can be pushed and pierced into the second synthetic resin sheet.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: October 20, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Odaira, Eiji Imamura, Yusuke Wada, Yasushi Arai, Kenji Sasaoka, Takahiro Mori, Fumitoshi Ikegaya, Sadao Kowatari
  • Patent number: 5804086
    Abstract: This process for producing a structure incorporating a substrate (2), a thin surface film (16) made from a non-conducting material joined to one face (1) of the substrate (2), said substrate (2) having cavities (10) flush with said face (1), comprises the following successive stages:etching cavities (10) in one face (1) of a substrate, the cavities having in the plane of the substrate face at least one dimension which is a function of the thickness of the surface film, in order to correctly secure the latter,joining a non-conducting material wafer (12) to the face (1) of the substrate (2),thinning the wafer (12) to obtain the thin surface film.
    Type: Grant
    Filed: August 1, 1996
    Date of Patent: September 8, 1998
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Michel Bruel
  • Patent number: 5770522
    Abstract: A method for mounting a semiconductor wafer on a polishing block to hold the semiconductor wafer during polishing. The method comprises the steps of providing a polishing block having a surface for mounting the semiconductor wafer and providing a heater comprising a heater body and a thermally conductive buffer plate which is selectively moveable with respect to the heater body between a pre-heating position in which the plate is spaced from the heater body and a heating position in which the plate contacts the heater body. A bonding agent is applied to the polishing block surface. The polishing block is placed on the buffer plate when the buffer plate is positioned in the pre-heating position and the buffer plate is moved from the pre-heating position to the heating position to heat the buffer plate, the polishing block and the bonding agent.
    Type: Grant
    Filed: November 12, 1996
    Date of Patent: June 23, 1998
    Assignee: MEMC Electronic Materials, Inc.
    Inventor: Francis Richard Bronson
  • Patent number: 5766493
    Abstract: A method of fabricating a substrate includes the steps of providing a first substrate having a first thickness, providing a second substrate having a second thickness, providing an inner layer between the first and second substrates, assembling the first substrate, the second substrate, and the inner layer using an adhesive, and reducing the thickness of at least one of the first and second substrates.
    Type: Grant
    Filed: October 27, 1995
    Date of Patent: June 16, 1998
    Assignee: LG Electronics Inc.
    Inventor: Woo Sup Shin
  • Patent number: 5750000
    Abstract: A semiconductor device having a substrate with an insulating surface and a non-porous semiconductor region bonded to the body of the device. A porous semiconductor region on the surface of the substrate was removed by etching.
    Type: Grant
    Filed: November 25, 1996
    Date of Patent: May 12, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takao Yonehara, Nobuhiko Sato, Kiyofumi Sakaguchi, Shigeki Kondo
  • Patent number: 5714079
    Abstract: A metallic sheet (10) is laminated between a pair of photoresist layers (26, 30) having different properties which permit one photoresist (26) to be stripped from the metallic sheet, substantially without effecting the other photoresist (30). A thin gauge blank or article (56) is photo-chemically machined from the lamination and the photoresist (26) is stripped from one side, leaving the other photoresist (30) to provide electrical insulation on just one side of the article.
    Type: Grant
    Filed: December 8, 1995
    Date of Patent: February 3, 1998
    Assignee: Eastman Kodak Company
    Inventors: Edwin Anthony Mycek, Larry Lee Lapa
  • Patent number: 5690839
    Abstract: A method for forming an array of thin film actuated mirrors for use in an optical projection system comprises the steps of: (a) providing a base; (b) depositing a separation layer on top of the base; (c) forming a first an electrodisplacive, a second, an elastic and a sacrificial layers successively on top of the separation layer; (d) forming an array of M.times.N supporting members, each thereof having a conduit; (e) patterning to form an array of multilayered actuated mirror structures; (f) attaching an active matrix included therein an array of transistors to the array of multilayered actuated mirror structures; (g) separating the base to form said array of thin film actuated mirrors. In the inventive method, the heat treatment of the electrodisplacive layer is carried out prior to the attaching of the active matrix, thereby preventing the transistors from being degraded by the heat.
    Type: Grant
    Filed: May 4, 1995
    Date of Patent: November 25, 1997
    Assignee: Daewoo Electronics Co., Ltd.
    Inventor: Yong-Ki Min
  • Patent number: 5690837
    Abstract: In a process for producing a multilayer printed circuit board comprising drilling holes for via holes in a composite film material containing at least a copper foil and an insulating half-cured adhesive layer, laminating the resulting film material on an innerlayer circuit substrate, ad electrically connecting an innerlayer circuit with an outer layer copper foil, when an adhesive resin flowed into the holes is roughened, or when a composite film material having a copper foil of less than 12 .mu.m thick formed on a carrier is used, or a special cushion material is further laminated on the laminate of the innerlayer circuit substrate and the film material, electrical connection reliability is enhanced and circuit density can be increased with easy steps.
    Type: Grant
    Filed: December 21, 1995
    Date of Patent: November 25, 1997
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Akishi Nakaso, Koichi Tsuyama, Kazuhisa Otsuka, Haruo Ogino, Yoshihiro Tamura, Teiichi Inada, Kazunori Yamamoto, Akinari Kida, Atsushi Takahashi, Yoshiyuki Tsuru, Shigeharu Arike
  • Patent number: 5672240
    Abstract: A diamond-based structure includes a substrate, an adhesive material on a face of the substrate, and an array of spaced apart diamond mesas bonded to the substrate by the adhesive material. In particular, each of the diamond mesas can have a growth surface adjacent the substrate and an interfacial surface opposite the substrate, and the interfacial surface can be smooth relative to the growth surface. This structure can be fabricated by providing a sacrificial substrate, forming a plurality of diamond mesas on a face of the sacrificial substrate, bonding the diamond mesas to a transfer substrate, and removing the sacrificial substrate. Accordingly, the interfacial surfaces of the diamond, which are formed adjacent the sacrificial substrate and then exposed by removing the substrate are smooth.
    Type: Grant
    Filed: June 5, 1996
    Date of Patent: September 30, 1997
    Assignee: Kobe Steel USA Inc.
    Inventors: Brian R. Stoner, Joseph S. Holmes, Jr., David L. Dreifus, Scott R. Sahaida, Roy E. Fauber, Michelle L. Hartsell, Dean Malta
  • Patent number: 5601732
    Abstract: Upon grinding a back of a substrate, a protecting tape made of a material soluble to IPA (isopropanol), for example, a vinyl acetate thermoplastic adhesive is appended on the surface of a pattern-formed layer of a wafer, grinding the back, dipping the wafer in a cleaning vessel containing IPA, and dissolving and removing the protecting tape from the wafer, thereby giving no damages to the wafer, and reducing the number of operation steps.
    Type: Grant
    Filed: November 9, 1995
    Date of Patent: February 11, 1997
    Assignee: Sony Corporation
    Inventor: Masahiro Yoshida
  • Patent number: 5554304
    Abstract: In a micromotion mechanical structure, such as a vibration-type sensor or a step motor, comprising at least one fixed electrode and at least one movable electrode which is moved by electrostatic power applied to the fixed electrode, at least one of the electrodes is formed essentially by a single crystal semiconductor material. The single crystal semiconductor material has various merits of uniform mechanical properties, small internal stress, etc. for use in such electrodes. Such structure has been realized by attaching patterned electrode made of the material to another substrate and then removing or thinning the original substrate carrying the patterned electrodes.
    Type: Grant
    Filed: March 24, 1995
    Date of Patent: September 10, 1996
    Assignee: Nec Corporation
    Inventor: Kenichiro Suzuki
  • Patent number: 5538151
    Abstract: A structure and method for removing and recovering an anodically bonded glass device from a substrate using a metal interlayer interposed between the glass and the substrate is provided. As used in semiconductor mask fabrication, the structure comprises a silicon wafer substrate coated with a membrane on which a metal interlayer is disposed. The metal interlayer and a glass device are anodically bonded together. Recovery of the glass device is accomplished by chemically and mechanically removing the wafer and its membrane from the metal interlayer. The membrane is preferably removed using reactive ion etching to which the metal interlayer is resistant. The metal interlayer is then removed from the glass device using a highly corrosive chemical solution. The recovered glass device may then be reused.
    Type: Grant
    Filed: January 20, 1995
    Date of Patent: July 23, 1996
    Assignee: International Business Machines Corp.
    Inventors: Thomas B. Faure, Kurt R. Kimmel, Wilbur D. Pricer, Charles A. Whiting
  • Patent number: 5517758
    Abstract: A dry sandblasting treatment for spraying abrasives onto a surface of an insulating resin layer, a chemical etching for chemically etching the surface, and a plating process for plating a conductive layer on the resulting insulating resin layer are successively performed. Since the surface of the insulating resin layer is roughened by the dry sandblasting treatment and the resulting surface is subjected to the chemical etching, a minute anchor structure is formed on the surface. Accordingly, the adhesion between the insulating resin layer and a plating layer (i.e., a circuit conductive layer) is improved. Due to the dry sandblasting treatment, the shape of a via hole formed in the insulating resin layer is improved, and an exposed surface of the circuit conductor layer and an inner wall of a through-hole are cleaned.
    Type: Grant
    Filed: September 28, 1993
    Date of Patent: May 21, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Tsuneshi Nakamura