Abstract: Methods and systems for reducing stiction through roughening the surface and reducing the contact area in MEMS devices are disclosed. A method includes fabricating bumpstops on a surface of a MEMS device substrate to reduce stiction. Another method is directed to applying roughening etchant to a surface of a silicon substrate to enhance roughness after cavity etch and before removal of hardmask. Another embodiment described herein is directed to a method to reduce contact area between proof mass and UCAV (“upper cavity”) substrate surface with minimal impact on the cavity volume by introducing a shallow etch process step and maintaining high pressure in accelerometer cavity. Another method is described as to increasing the surface roughness of a UCAV substrate surface by depositing a rough layer (e.g. polysilicon) on the surface of the substrate and etching back the rough layer to transfer the roughness.

Abstract: A glass substrate includes a pair of main surfaces including a first main surface and a second main surface opposed to the first main surface; an edge surface arranged along a direction orthogonal to the pair of main surfaces; and a connecting surface arranged between the first main surface and the edge surface. The connecting surface has a plurality of pores. A difference between a 50% particle diameter of the pores in a portion 20 ?m distant from the first main surface and a 50% particle diameter in a portion 20 ?m distant from the edge surface is 10 ?m or less.

Abstract: A method includes applying a composition for forming a resist underlayer film to a substrate having a recess in a surface, and baking the composition for forming a resist underlayer film to form a resist underlayer film for filling at least the recess. The composition for forming a resist underlayer film has a copolymer having a structural unit of following formula (1), a cross-linkable compound, a cross-linking catalyst, and a solvent: wherein R1 and R2 are each independently a C1-3 alkylene group or a single bond, Z is an —O— group, a —S— group, or a —S—S— group, and Ar is an arylene group.

Abstract: Exemplary semiconductor processing chambers may include a substrate support positioned within a processing region of the semiconductor processing chamber. The chamber may include a lid plate. The chamber may include a gasbox positioned between the lid plate and the substrate support. The gasbox may be characterized by a first surface and a second surface opposite the first surface. The gasbox may define a central aperture. The gasbox may define an annular channel in the first surface of the gasbox extending about the central aperture through the gasbox. The gasbox may include an annular cover extending across the annular channel defined in the first surface of the gasbox. The chamber may include a blocker plate positioned between the gasbox and the substrate support. The chamber may include a ferrite block positioned between the lid plate and the blocker plate.

Abstract: The present disclosure relates to systems and methods relating to the fabrication of light guide elements. An example system includes an optical component configured to direct light emitted by a light source to illuminate a photoresist material at one or more desired angles so as to expose an angled structure in the photoresist material. The photoresist material overlays at least a portion of a first surface of a substrate. The optical component includes a container containing a light-coupling material that is selected based in part on the one or more desired angles. The system also includes a reflective surface arranged to reflect at least a first portion of the emitted light to illuminate the photoresist material at the one or more desired angles.

Abstract: Embodiments of the invention provide a method for atomic layer etching (ALE) of a substrate. According to one embodiment, the method includes providing a substrate, and exposing the substrate to hydrogen fluoride (HF) gas and a boron-containing gas to etch the substrate. According to another embodiment, the method includes providing a substrate containing a metal oxide film, exposing the substrate to HF gas to form a fluorinated surface layer on the metal oxide film, and exposing the substrate to a boron-containing gas to remove the fluorinated surface layer from the metal oxide film. The exposures may be repeated at least once to further etch the metal oxide film.

Abstract: A method for producing a material based on silicon nanowires is provided. The method includes the steps of: i) bringing into contact, in an inert atmosphere, a sacrificial support based on a halogenide, a carbonate, a sulfate or a nitrate of an alkali metal, an alkaline earth metal or a transition metal having metal nanoparticles, with the pyrolysis vapours of a silicon source having a silane compound, by which silicon nanowires are deposited on the sacrificial support; and optionally ii) eliminating the sacrificial support and recovering the silicon nanowires produced in step ii).

Abstract: A plasma generating apparatus according to the present disclosure includes: a high frequency power supply that generates a high frequency power; a plasma generation electrode connected to the high frequency power supply and formed by a hollow tube in which cooling water is distributed; a conductivity meter that measures conductivity of the cooling water inside the plasma generation electrode; and a controller that controls output of the high frequency power supply based on the conductivity of the cooling water measured by the conductivity meter.

Abstract: An apparatus can include a logic element configured to generate information corresponding to an adaptive layer to be formed over a current substrate based at least in part on a difference in flatness profiles associated with a first substrate chuck and a second substrate chuck. In another aspect, a method can include obtaining a difference in thickness profiles for the first and second chucks using a prior substrate, and forming an adaptive layer over a previously formed patterned layer of a current substrate and before forming a patterned resist layer aligned to the previously formed patterned layer. In an embodiment, the thickness profile of the adaptive layer is a function of the inverse of the difference in flatness profiles of the substrate chucks. The adaptive layer can help to reduce overlay error associated with different flatness profiles of substrate chucks.

Abstract: A method of forming a semiconductor device fabrication is described that includes forming a material layer over a substrate, forming a first trench in the material layer, forming a first dielectric capping layer along sidewalls of the first trench, forming a second trench in the material layer while the capping layer disposed along sidewalls of the first trench, forming a second dielectric capping layer along sidewalls of the second trench and along the sidewalls of the first trench and forming a conductive feature within the second trench and the first trench.

Abstract: A first electro-optic display comprises first and second substrates, and an adhesive layer and a layer of electro-optic material disposed between the first and second substrates, the adhesive layer comprising a mixture of a polymeric adhesive material and a hydroxyl containing polymer having a number average molecular weight not greater than about 5000. A second electro-optic display is similar to the first but has an adhesive layer comprising a thermally-activated cross-linking agent to reduce void growth when the display is subjected to temperature changes. A third electro-optic display, intended for writing with a stylus or similar instrument, is produced by forming a layer of an electro-optic material on an electrode; depositing a substantially solvent-free polymerizable liquid material over the electro-optic material; and polymerizing the polymerizable liquid material.

Abstract: Methods of planarizing materials, such as where surface topographies are created as part of a thin film device fabrication process are described. These methods find particular application in the creation of nano-sized devices, where surface topographical features can be effectively planarized without adversely creating other surface topographies and/or causing deleterious effects a material junctions. Methods include the step of depositing a sacrificial layer overlying at least a portion of a first material layer and at least a portion of a backfilled second material at a junction between the first and second materials. The sacrificial layer substantially retains the surface topography of the microelectronic device. Chemical-mechanical planarization is performed on a surface of the sacrificial layer but leaving a remainder portion of the thickness of the sacrificial layer.

Abstract: Systems and methods of in-situ calibration of semiconductor material layer deposition and removal processes are disclosed. Sets of test structures including one or more calibration vias or posts are used to precisely monitor processes such as plating and polishing, respectively. Known (e.g., empirically determined) relationships between the test structure features and product feature enable monitoring of wafer processing progress. Optical inspection of the calibration feature(s) during processing cycles permits dynamic operating condition adjustments and precise cessation of processing when desired product feature characteristics have been achieved.

Abstract: Provided is a method for polishing a material having a Vickers hardness of 1500 Hv or higher. The polishing method comprises a step of carrying out preliminary polishing using a preliminary polishing composition that comprises an abrasive APRE and a step of carrying out final polishing using a final polishing composition that comprises an abrasive AFIN lower in hardness than the abrasive APRE.

Abstract: A method of forming a self-aligned pattern of vias in a semiconductor device comprises etching a pattern of lines that contain notches that are narrower than other parts of the line. Thereafter, vias are created where the notches are located. The locations of the vias are such that the effect of blown-out areas is minimized. Thereafter, the lines are etched and the vias and line areas are filled. The layers are planarized such that the metal fill is level with a surrounding ultra-low-k dielectric. Additional metal layers, lines, and vias can be created. Other embodiments are also described herein.

Abstract: In a substrate processing apparatus, a temperature of an anti-static liquid having electrical resistivity which gradually decreases as a liquid temperature increases is adjusted by a temperature adjustment part and the electrical resistivity of the anti-static liquid is higher than the electrical resistivity of a processing liquid (SPM liquid). After that, a plurality of substrates are immersed in the anti-static liquid inside the anti-static liquid storage part and both main surfaces of each substrate entirely conic into contact with the anti-static liquid. This gradually removes static electricity from the substrate. Then, the SPM liquid is supplied onto an upper surface of the substrate to thereby perform an SPM process. In the SPM process, it is thereby possible to prevent a large amount of electric charges from sharply moving from the substrate to the SPM liquid and prevent any damage to the substrate.

Abstract: The substrate treatment apparatus includes a first nozzle, a second nozzle, a detector, and a controller. The first nozzle supplies an organic sublimable material-containing liquid capable of displacing a rinsing liquid, to a surface of a substrate treated with the rinsing liquid. The second nozzle supplies vapor of a solvent in which the organic sublimable material is capable of dissolving, to the surface of the substrate. The detector detects a first physical amount of the vapor on the surface of the substrate. The controller controls a second physical amount of the vapor according to the first physical amount.

Abstract: A method for depositing an amorphous carbon hardmask film includes arranging a substrate in a processing chamber, supplying a carrier gas to the processing chamber, supplying a hydrocarbon precursor to the processing chamber, supplying fluorine precursor from a group consisting of WFa, NFb, SFc, and F2 to the processing chamber, one of supplying plasma to the processing chamber or creating plasma in the processing chamber, and depositing an amorphous carbon hardmask film on the substrate. Fluorine from the fluorine precursor combines with hydrogen from the hydrocarbon precursor in gas phase reactions.

Abstract: In one aspect, a method of polishing includes polishing a substrate, and receiving an identification of a selected spectral feature and a characteristic of the selected spectral feature to monitor during polishing. The method includes measuring a sequence of spectra of light reflected from the substrate while the substrate is being polished, where at least some of the spectra of the sequence differ due to material being removed during the polishing. The method of polishing includes determining a value of a characteristic of the selected spectral feature for each of the spectra in the sequence of spectra to generate a sequence of values for the characteristic, fitting a function to the sequence of values, and determining either a polishing endpoint or an adjustment for a polishing rate based on the function.

Abstract: A method includes forming a first insulating layer over a substrate, the first insulating layer having a non-planar top surface, the first insulating layer having a first etch rate. A second insulating layer is formed over the first insulating layer, the second insulating layer having a non-planar top surface, the second insulating layer having a second etch rate, the second etch rate being greater than the first etch rate. The second insulating layer is polished, the polishing partially removing the second insulating layer. The first insulating layer and the second insulating layer are non-selectively recessed.

Abstract: A method for producing a semiconductor device, which includes forming an underlayer film on a semiconductor substrate with a resist underlayer film forming composition that contains a solvent, and a polymer containing a unit structure of Formula (2): O—Ar2—O—Ar3-T-Ar4??Formula (2) where Ar2, Ar3, and Ar4 are individually a C6-50 arylene group or an organic group containing a heterocyclic group; at least one of Ar3 and Ar4 is a phenylene group; and T is a carbonyl group. The resist underlayer film forming composition has a solid content of 0.1 to 70 mass % of a total mass of the composition.

Abstract: A method of forming a trench isolation (e.g., an STI) for an integrated circuit includes forming a pad oxide layer and then a nitride layer over a semiconductor substrate, performing a trench etch through the structure to form a trench, depositing a trench oxide layer over the structure to form a filled trench, depositing a sacrificial planarizing layer, which is etch-selective to the trench oxide layer, over the deposited oxide, performing a planarizing etch process that removes the sacrificial planarizing layer and decreases surface variations in an upper surface of the trench oxide layer, performing an oxide etch process that is selective to the trench oxide layer to remove remaining portions of the trench oxide layer outside the filled trench, and removing the remaining nitride layer such that the remaining oxide-filled trench defines a trench isolation structure that projects above an exposed upper surface of the semiconductor substrate.

Abstract: A method for making patterns on a substrate, includes forming an assembly guide on first and second areas of the substrate, the assembly guide having, compared to a reference surface, openings with an opening ratio in the first area greater than that of the second area; depositing a block copolymer layer on the substrate to entirely fill the assembly guide and form an over-thickness on the reference surface; assembling the block copolymer, resulting in an organised portion of the block copolymer layer inside the openings; thinning uniformly the block copolymer layer, until a thickness corresponding to the organised portion of the block copolymer layer is reached; eliminating one of the phases of the assembled block copolymer, resulting in a plurality of initial patterns extending into the layer of block copolymer; and transferring the initial patterns of the block copolymer layer into the substrate to form the final patterns.

Abstract: A method of forming a fine pattern includes providing a first metal layer on a base substrate, providing a first passivation layer on the first metal layer, providing a mask pattern on the first passivation layer, providing a partitioning wall pattern having a reverse taper shape by etching the first passivation layer, coating a composition having a block copolymer between the partitioning wall patterns adjacent each other, providing a self-aligned pattern by heating the composition, and providing a metal pattern by etching the first metal layer using the self-aligned pattern as a mask.

Abstract: A method of forming a plurality of regularly spaced lithography features, the method including providing a self-assemblable block copolymer having first and second blocks in a plurality of trenches on a substrate, each trench including opposing side-walls and a base, with the side-walls having a width therebetween, wherein a first trench has a greater width than a second trench; causing the self-assemblable block copolymer to self-assemble into an ordered layer in each trench, the layer having a first domain of the first block alternating with a second domain of the second block, wherein the first and second trenches have the same number of each respective domain; and selectively removing the first domain to form regularly spaced rows of lithography features having the second domain along each trench, wherein the pitch of the features in the first trench is greater than the pitch of the features in the second trench.

Abstract: Solid-state lighting devices (SSLDs) including a carrier substrate with conductors and methods of manufacturing SSLDs. The conductors can provide (a) improved thermal conductivity between a solid-state light emitter (SSLE) and a package substrate and (b) improved electrical conductivity for the SSLE. In one embodiment, the conductors have higher thermal and electrical conductivities than the carrier substrate supporting the SSLE.

Abstract: In a metallization system of a complex semiconductor device, metal pillars, such as copper pillars, may be formed in a nail-like configuration in order to reduce the maximum mechanical stress acting on the metallization system while providing a required contact surface for connecting to the package substrate. The nail-like configuration may be obtained on the basis of appropriately configured resist masks.

Abstract: A method for manufacturing an aluminosilicate glass substrate for a hard disk of the present invention includes polishing an aluminosilicate glass substrate to be polished with a polishing composition that includes silica particles, a polymer having a sulfonic acid group, and water, wherein an adsorption constant of the polymer having the sulfonic acid group on aluminosilicate glass is 1.5 to 5.0 L/g. The polymer having the sulfonic acid group is preferably a polymer having an aromatic ring. The weight average molecular weight of the polymer having the sulfonic acid group is 3000 to 100000.

Abstract: Provided are a method for etching a metal or metal oxide without using a reagent, etc., that affects the environment, a method for smoothing a surface of a metal or metal oxide on an atomic level, and a method for patterning on an atomic level. Etching of a metal or metal oxide, or smoothing of a surface of a metal or metal oxide is possible using ozone water in which only ozone is dissolved. Patterning can also be performed by providing a metal that does not dissolve in the ozone water as a resist on a metal or metal oxide that can be etched by ozone water in which only ozone is dissolved, and etching using the ozone water.

Abstract: The present disclosure pertains to a method of forming a spacer patterning mask. The method entails: providing a substrate; depositing, on the substrate, an interface layer, a core film and a first hard mask; patterning the core film and the first hard mask to form strips; depositing a spacer patterning layer to cover the core film and the first hard mask in the intermediate pattern; planarizing the spacer patterning layer by using the first hard mask in the intermediate pattern as a stop layer; etching the planarized spacer patterning layer; dry etching the second hard mask to expose the partially-etched spacer patterning layer; dry etching the exposed spacer patterning layer to form a spacer pattern; and removing the remaining first hard mask and second hard mask and the core film to obtain the final spacer patterning mask.

Abstract: Damascene processes using physical vapor deposition (PVD) sputter carbon film as a chemical mechanical planarization (CMP) stop layer for forming a magnetic recording head are provided. In one embodiment, one such process includes providing an insulator, removing a portion of the insulator to form a trench within the insulator, depositing a carbon material on first portions of the insulator using a physical vapor deposition process, disposing at least one ferromagnetic material on second portions of the insulator to form a pole including a portion of the ferromagnetic material within the trench, and performing a chemical mechanical planarization on the at least one ferromagnetic material using at least a portion of the carbon material as a stop for the chemical mechanical planarization.

Abstract: The invention provides a chemical-mechanical polishing composition and a method of chemically-mechanically polishing a substrate with the chemical-mechanical polishing composition. The polishing composition comprises (a) abrasive particles that comprise ceria, zirconia, silica, alumina, or a combination thereof, (b) a metal ion that is a Lewis Acid, (c) a ligand that is an aromatic carboxylic acid, an aromatic sulfonic acid, an aromatic acid amide, an amino acid, or a hydroxy-substituted N-heterocycle, and (d) an aqueous carrier, wherein the pH of the chemical-mechanical polishing composition is in the range of about 1 to about 4.

Abstract: A liquid ejection head includes a substrate having an ejection energy generating element formed at a first surface side thereof, a common liquid chamber formed at a second surface of the substrate, and a liquid supply port extending from the bottom of the common liquid chamber to the first surface. The liquid ejection head is manufactured by preparing a substrate having the common liquid chamber formed at the second surface side, then arranging a material to be filled in the common liquid chamber, subsequently forming an aperture in the filled material as corresponding to the liquid supply port to be formed, and thereafter forming the liquid supply port by reactive ion etching, using at least the filled material as a mask.

Abstract: A pattern forming method includes forming a coating film containing a hydrophilic first homopolymer having a first bonding group and a hydrophobic second homopolymer having a second bonding group capable of bonding with the first bonding group, forming a bond between the first and second bonding group to produce a block copolymer of the first and second homopolymers, and heating the coating film to microphase-separating the copolymer into a hydrophilic domain and a hydrophobic domain. The hydrophilic and hydrophobic domains are arranged alternately. The bond is broken, then selectively dissolving-removing either domain by a solvent to provide a polymer pattern of a remainder domain.

Abstract: A method of edge coating a batch of glass articles includes printing masks on surfaces of a glass sheet, where at least one of the masks is a patterned mask defining a network of separation paths. The glass sheet with the printed masks is divided into multiple glass articles along the separation paths. For at least a batch of the glass articles, the edges of the glass articles in the batch are finished to reduce roughness at the edges. Each finished edge is then etched with an etching medium to reduce and/or blunt flaws in the finished edge. A curable coating is simultaneously applied to the etched edges. The curable coatings are pre-cured. Then, the printed masks are removed from the glass articles with the curable coatings. After removing the printed masks, the pre-cured curable coatings are post-cured.

Abstract: The present invention provides a polishing composition that can suppress generation of bumps due to etching on a surface of an object to be polished having a germanium material-containing part during the polishing of the object. The polishing composition of the present invention contains abrasive grains, an oxidant and a water-soluble polymer. The water-soluble polymer may be a water-soluble polymer such that 5,000 or more molecules are adsorbed per 1 ?m2 of the surface area of the abrasive grains. Alternatively, the water-soluble polymer may be a compound that reduces the water contact angle of the germanium material-containing part of the object to be polished after the object has been polished by using the polishing composition.

Abstract: A method for cleaning a dielectric and metal structure within a microelectronic structure uses an oxygen containing plasma treatment, followed by an alcohol treatment, in turn followed by an aqueous organic acid treatment. Another method for cleaning a dielectric and metal structure within a microelectronic structure uses an aqueous surfactant treatment followed by an alcohol treatment and finally followed by an aqueous organic acid treatment. The former method may be used to clean a plasma etch residue from a dual damascene aperture. The second method may be used to clean a chemical mechanical polish planarizing residue from a dual damascene structure. The two methods may be used sequentially, absent any intervening or subsequent sputtering method, to provide a dual damascene structure within a microelectronic structure.

Abstract: A method of polishing a sapphire substrate is provided, comprising: providing a substrate having an exposed sapphire surface; providing a chemical mechanical polishing slurry, wherein the chemical mechanical polishing slurry comprises, as initial components: colloidal silica abrasive, wherein the colloidal silica abrasive has a negative surface charge; and, wherein the colloidal silica abrasive exhibits a multimodal particle size distribution with a first particle size maximum between 2 and 25 nm; and, a second particle size maximum between 75 and 200 nm; optionally, a biocide; optionally, a nonionic defoaming agent; and, optionally, a pH adjuster. A chemical mechanical polishing composition for polishing an exposed sapphire surface is also provided.

Abstract: A method of removing material from a sapphire article is described. In particular, the method comprises the step of providing an initial sapphire layer and reducing the thickness of the layer while not significantly increasing the surface roughness of the layer, Cover plates for electronic device and methods of preparing them are also disclosed, along with a method of analyzing a sapphire article produced by the present method.

Abstract: A method of removing material from a sapphire article is described. In particular, the method comprises the step of providing an initial sapphire layer and reducing the thickness of the layer while not significantly increasing the surface roughness of the layer. Cover plates for electronic device and methods of preparing them are also disclosed, along with a method of analyzing a sapphire article produced by the present method.

Abstract: A method of chemical mechanical polishing (CMP) a diamond containing surface includes providing a slurry including a plurality of particles, at least one oxidizer, and at least one acid, wherein the slurry has a pH?3 or pH greater than 11. At least an outer surface of the plurality of particles is softer than the diamond surface or the particles are diamond particles averaging less than (<) 2 ?m in size. The diamond surface is pressed with respect to a polishing pad providing a Shore D Hardness less than 99 having the slurry in between while rotating the polishing pad relative to the diamond surface to form a smooth diamond surface having a root mean square (rms) surface roughness less than 15 nm.

Abstract: Disclosed is a polishing agent for synthetic quartz glass substrates, which is characterized by containing a colloidal solution of a colloidal silica or the like having a colloid concentration of 20-50% by mass, and a polycarboxylic acid polymer, an acidic amino acid, a phenol or a glycosaminoglycan.

Abstract: According to one embodiment, a planarizing method is proposed. In the planarizing method, a surface to be processed of an object to be processed including a silicon oxide film is planarized in a processing solution by bringing the surface to be processed into contact with or close proximity with the surface of a solid-state plate on which fluorine is adsorbed. The bonding energy between fluorine and the solid-state plate is lower than that between fluorine and silicon.

Abstract: A post chemical-mechanical-polishing (post-CMP) cleaning composition comprising: (A) at least one compound comprising at least one thiol (—SH), thioether (—SR1) or thiocarbonyl (>C?S) group, wherein R1 is alkyl, aryl, alkylaryl or arylalkyl, (B) at least one sugar alcohol which contains at least three hydroxyl (—OH) groups and does not comprise any carboxylic acid (—COOH) or carboxylate (—COO—) groups, and (C) an aqueous medium.

Abstract: A method of manufacturing nanostructures on a surface of a metal substrate is provided. The method includes forming the nanostructures by a forming step, which includes subsequently performing at least once the steps of anodizing the surface at a second voltage for forming at the surface a second oxidized metal layer comprising second pores, and performing an etching step on the surface for modifying the dimensions of the second pores. Prior to the forming step, the method comprises a substrate preparation step for enabling the forming a mix of different sized nanostructures during the forming step, the preparation step including the steps of anodizing the surface at a first voltage for forming at the surface an first oxidized metal layer comprising first pores, selectively etching the surface for extending the first pores into the metal underneath the first oxidized metal layer, and removing the first oxidized metal layer.

Abstract: An etchant composition includes about 25 percent by weight to about 35 percent by weight of phosphoric acid, about 3 percent by weight to about 9 percent by weight of nitric acid, about 10 percent by weight to about 20 percent by weight of acetic acid, about 5 percent by weight to about 10 percent by weight of a nitrate, about 6 percent by weight to about 15 percent by weight of a sulfonic acid, about 1 percent by weight to about 5 percent by weight of an amine compound including a carboxyl group, about 0.1 percent by weight to about 1 percent by weight of a water-soluble amino acid, about 0.01 percent by weight to about 1 percent by weight of an azole compound, and water.

Abstract: Methods for removing, reducing or treating the trace metal contaminants and the smaller fine sized cerium oxide particles from cerium oxide particles, cerium oxide slurry or chemical mechanical polishing (CMP) compositions for Shallow Trench Isolation (STI) process are applied. The treated chemical mechanical polishing (CMP) compositions, or the CMP polishing compositions prepared by using the treated cerium oxide particles or the treated cerium oxide slurry are used to polish substrate that contains at lease a surface comprising silicon dioxide film for STI (Shallow trench isolation) processing and applications. The reduced nano-sized particle related defects have been observed due to the reduced trace metal ion contaminants and reduced very smaller fine cerium oxide particles in the Shallow Trench Isolation (STI) CMP polishing.

Abstract: This invention relates to a novel application of liquid-infused surface materials (LISM) to at least a portion of one or more surfaces of razor components (e.g., frame, housing, clips, blade supports, blade body, blade edge, lubricating bodies, guard, handle, grip, button). If applied to a skin contacting surface of a component, the one or more LISM layers may generally be abrasion-resistant, long-lasting or non-erodible, desirably elevating shaving performance, such as glide, comfort, rinsing, and cleanliness, while also simplifying the manufacturing process.

Abstract: The invention provides a chemical-mechanical polishing composition containing a ceria abrasive, an ionic polymer of formula I: wherein X1 and X2, Z1 and Z2, R2, R3, and R4, and n are as defined herein, and water, wherein the polishing composition has a pH of about 1 to about 4.5. The invention further provides a method of chemically-mechanically polishing a substrate with the inventive chemical-mechanical polishing composition. Typically, the substrate contains silicon oxide, silicon nitride, and/or polysilicon.

Abstract: Greater planarity is achieved between surfaces of a conductive structure and a layer within which the conductive structure resides. A portion of the conductive structure protruding above the surface of the layer is selectively oxidized, at least in part, to form an oxidized portion. The oxidized portion is then removed, at least partially, to facilitate achieving greater planarity. The protruding portions may optionally be formed by selectively disposing conductive material over the conductive structure, when that the conductive structure is initially recessed below the surface of the layer. A further embodiment includes selectively oxidizing a portion of the conductive structure below the surface of the layer, removing at least some of the oxidized portion so that an upper surface of the conductive structure is below the upper surface of the layer, and planarizing the upper surface of the layer to the upper surface of the conductive structure.