Planarizing A Nonplanar Surface Patents (Class 216/38)
-
Patent number: 8329053Abstract: In accordance with an illustrative embodiment, a method of fabricating a transducer is described. The method comprises providing a transducer over a first surface of a substrate, wherein the substrate comprises a thickness. The method further comprises patterning a mask over a second surface. The mask comprises an opening for forming a scribe etch. The method comprises etching through the opening in the mask and into but not through the thickness of the substrate to provide the scribe etch.Type: GrantFiled: November 23, 2009Date of Patent: December 11, 2012Assignee: Avago Technologies Wireless IP (Singapore) Pte. Ltd.Inventors: David Martin, Joel Philliber
-
Patent number: 8318477Abstract: A cellular electrophysiological measurement device includes a thin plate and a frame. The thin plate has a first surface with a depression and a second surface with a through-hole. The frame is in contact with an outer periphery on the second surface of thin plate. The thin plate has a laminated structure of at least two layers including a first material layer on the first surface and a second material layer on the second surface. The frame is formed of a third material layer. The structure allows the cellular electrophysiological measurement device to be not so vulnerable to breakage of thin plate and other damages, thereby having high production yield.Type: GrantFiled: May 31, 2006Date of Patent: November 27, 2012Assignee: Panasonic CorporationInventors: Masaya Nakatani, Takashi Yoshida, Masatoshi Kojima
-
Patent number: 8313947Abstract: A method of testing a contact structure including exposing a gold layer of at least one contact structure of a support structure to a solution including glacial acetic acid and nitric acid; and determining a porosity of the gold layer of at least one contact structure after the exposing.Type: GrantFiled: June 18, 2010Date of Patent: November 20, 2012Assignee: Freescale Semiconductor, Inc.Inventor: Rama I. Hegde
-
Publication number: 20120287507Abstract: Wire grid polarizers, methods of fabricating a wire grid polarizer and display panels including a wire grid polarizer are provided, the methods include preparing a mold having a lower surface in which a plurality of parallel fine grooves are formed, and arranging the mold on a transparent substrate. The plurality of parallel fine grooves are filled with a conductive liquid ink. A plurality of parallel conductive nano wires are formed on the transparent substrate by curing the conductive liquid ink. The mold is removed.Type: ApplicationFiled: January 16, 2012Publication date: November 15, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang-seung Lee, Jun-seong Kim, Ki-deok Bae
-
Patent number: 8308964Abstract: A planarization process may planarize a media disk that has data trenches between data features and larger servo trenches between servo features. A filler material layer is deposited on the media disk and provides step coverage of the trenches. The filler material has data recesses over the data trenches and servo recesses over the servo trenches that must be removed to produce a planar media surface. A first planarization process is used to remove the data recesses and a second planarization process is used to remove the servo recesses.Type: GrantFiled: September 30, 2010Date of Patent: November 13, 2012Assignee: Seagate Technology LLCInventors: Yuan Xu, Wei Hu, Justin Jia-Jen Hwu, Gene Gauzner, Koichi Wago, David Shiao-Min Kuo
-
Patent number: 8298432Abstract: A method and system of location specific processing on a substrate is described. The method comprises establishing a gas cluster ion beam (GCIB) according to a set of beam properties and measuring metrology data for a substrate. Thereafter, the method comprises determining at least one spatial gradient of the metrology data at one or more locations on the substrate and adjusting at least one beam property in the set of beam properties for the GCIB according to the determined at least one spatial gradient. Using the metrology data and the adjusted set of beam properties, correction data for the substrate is computed. Following the computing, the adjusted GCIB is applied to the substrate according to the correction data.Type: GrantFiled: September 28, 2007Date of Patent: October 30, 2012Assignee: TEL Epion Inc.Inventors: Ruairidh MacCrimmon, Nicolaus J. Hofmeester, Steven P. Caliendo
-
Patent number: 8293126Abstract: A method and system of location specific processing on a substrate is described. The method comprises acquiring metrology data for a substrate, and computing correction data for adjusting a first region of the metrology data on the substrate. Thereafter, a first gas cluster ion beam (GCIB) for treating the high gradient regions is established, and the first GCIB is applied to the substrate according to the correction data. The method further comprises optionally acquiring second metrology data following the applying of the first GCIB, and computing second correction data for adjusting a second region of the metrology data, or the second metrology data, or both on the substrate. Thereafter, a second gas cluster ion beam (GCIB) for treating the second region is established, and the second GCIB is applied to the substrate according to the second correction data.Type: GrantFiled: September 28, 2007Date of Patent: October 23, 2012Assignee: TEL Epion Inc.Inventors: Ruairidh MacCrimmon, Nicolaus J. Hofmeester, Steven P. Caliendo
-
Patent number: 8277668Abstract: A method of forming printed circuit boards and packaging substrates. After blind vias are created in a dielectric layer, a first seed layer is provided in the vias and on the dielectric layer. Copper is applied to fill the vias and to form a copper layer over the vias and over the first seed layer. The first seed layer and the copper layer are removed and a second seed layer is formed on the dielectric layer and the exposed surfaces of the vias. A wire pattern is then formed using a photo-sensitive thin film applied to the second seed layer, and the wires in the wire pattern are thickened. The photo-sensitive thin film and the exposed portions of the second seed layer are removed to form a first conductive pattern of wires. The process may be repeated to form a second conductive pattern of wires on the first pattern.Type: GrantFiled: March 25, 2008Date of Patent: October 2, 2012Assignee: Shanghai Meadville Science & Technology Co., Ltd.Inventors: FanXiong Cheng, Peifeng Chen, Haitao Fu, Yonghong Luo
-
Publication number: 20120231218Abstract: Provided is a substrate that can be made to have a suitable strength with low-cost and that can be bonded firmly to a piezoelectric substrate. The substrate, which is for SAW devices, consists of spinel, and the PV value of the difference in level of one of the main faces of the substrate is 2 nm to 8 nm inclusive. The average roughness (Ra) value of the one of the main faces of the substrate is preferably 0.01 nm to 3.0 nm inclusive, more preferably 0.01 nm to 0.5 nm inclusive. Also the Young's modulus of the spinel substrate, which is for the SAW device or other devices, is preferably 150 GPa to 350 GPa inclusive.Type: ApplicationFiled: September 16, 2010Publication date: September 13, 2012Applicant: Sumitomo Electric Industries, Ltd.Inventors: Shigeru Nakayama, Yutaka Tsuji
-
Publication number: 20120187084Abstract: A processing method of a substrate which includes: a first bonding step which bonds a ring-shaped first support member to a first surface of the substrate along the outer periphery of the substrate; a first processing step which processes the substrate; and a first separating step which separates the first support member from the substrate by separation at the bonded position.Type: ApplicationFiled: January 25, 2012Publication date: July 26, 2012Applicant: SEIKO EPSON CORPORATIONInventors: Tomohiro JIROMARU, Junichi TAKEUCHI
-
Patent number: 8192638Abstract: A method for manufacturing multiple layers of waveguides is disclosed. Initially, a first cladding layer is deposited on a substrate, a first inner cladding layer is then deposited on the first cladding layer, and a first waveguide material is deposited on the first inner cladding layer. The first inner cladding layer and the first waveguide material are then selectively etched to form a first waveguide layer. Next, a second inner cladding layer followed by a second cladding layer are deposited on the first waveguide layer. The second inner cladding layer and the second cladding layer are removed by using a chemical-mechanical polishing process selective to the first waveguide material. A third inner cladding layer followed by a second waveguide material are deposited on the first waveguide material. The third inner cladding layer and the second waveguide material are then selectively etched to form a second waveguide layer.Type: GrantFiled: August 29, 2008Date of Patent: June 5, 2012Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Andrew T. S. Pomerene, Timothy J. Conway, Craig M. Hill, Mark Jaso
-
Publication number: 20120080402Abstract: A planarization process may planarize a media disk that has data trenches between data features and larger servo trenches between servo features. A filler material layer is deposited on the media disk and provides step coverage of the trenches. The filler material has data recesses over the data trenches and servo recesses over the servo trenches that must be removed to produce a planar media surface. A first planarization process is used to remove the data recesses and a second planarization process is used to remove the servo recesses.Type: ApplicationFiled: September 30, 2010Publication date: April 5, 2012Applicant: Seagate Technology LLCInventors: Yuan Xu, Wei Hu, Justin Jia-Jen Hwu, Gene Gauzner, Koichi Wago, David Shiao-Min Kuo
-
Patent number: 8142675Abstract: A composition for chemical-mechanical planarization comprises periodic acid and an abrasive present in a combined amount sufficient to planarize a substrate surface having a feature thereon comprising a noble metal, noble metal alloy, noble metal oxide, or any combination thereof. In one embodiment, the periodic acid is present in an amount in a range of from about 0.05 to about 0.3 moles/kilogram, and the abrasive is present in an amount in a range of from about 0.2 to about 6 weight percent. In another embodiment, the composition further comprises a pH-adjusting agent present in an amount sufficient to cause the pH of the composition to be in a range of from about pH 5 to about pH 10, or of from about pH 1 to about pH 4.Type: GrantFiled: April 28, 2009Date of Patent: March 27, 2012Assignee: Air Products and Chemicals, Inc.Inventors: Robert J. Small, Zhefei J. Chen
-
Patent number: 8136228Abstract: A method for manufacturing a magnetic write head that avoids the challenges associated with the formation of fence structures during write pole definition. A magnetic write pole material is deposited. A mask structure is deposited over the magnetic write pole material. The mask structure includes a first hard mask, a marker layer, a physically robust, inorganic RIEable image transfer layer, a second hard mask structure over the image transfer layer and a photoresist layer over the second hard mask. A reactive ion etching process can be used to transfer the image of the photoresist mask and second hard mask layer onto the image transfer layer. An ion milling is performed to define the write pole. A layer of non-magnetic material such as alumina is deposited. An ion milling is performed until the marker layer has been reached, and another reactive ion etching is performed to remove the remaining hard mask.Type: GrantFiled: December 24, 2008Date of Patent: March 20, 2012Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Aron Pentek, Sue Siyang Zhang, Yi Zheng
-
Patent number: 8137574Abstract: The present invention is to provide a processing method for manufacturing a highly flat and highly smooth glass substrate with good productivity. A highly flat and highly smooth glass substrate is obtained with good productivity by processing of a glass substrate, which comprises a step of measuring the surface shape of the glass substrate prior to processing, a step of processing the surface of the substrate by changing a processing condition for each site (first processing step), and a step of finish-polishing the surface of the glass substrate that has been subjected to the first processing step (second processing step).Type: GrantFiled: September 19, 2008Date of Patent: March 20, 2012Assignee: Asahi Glass Company, LimitedInventors: Koji Otsuka, Hiroshi Kojima, Masabumi Ito
-
Patent number: 8105705Abstract: An improved magnetic shield for a perpendicular magnetic write head is disclosed. Its main feature is a pair of tabs at the shield's bottom corners. Said tabs are significantly wider at their point of attachment to the shield than further away from the shield. The end portions of each tab slope upwards (away from the ABS) at an angle of about ten degrees. A process for manufacturing the shield is also disclosed.Type: GrantFiled: October 26, 2009Date of Patent: January 31, 2012Assignee: Headway Technologies, Inc.Inventors: Zhigang Bai, Yuchen Zhou, Joe Smyth, Moris Dovek, Yan Wu
-
Patent number: 8075788Abstract: A printed circuit board fabrication method allows a fabrication time and a fabrication cost to be reduced. The fabrication method of the printed circuit board includes steps of forming a resist layer on a surface of the printed circuit board whose surface is made of an insulator, of forming a hole that is connected from the surface of the resist layer to a conductor pattern of an inner layer and a hole and grooves having a depth not connected with the conductor layer of the inner layer by irradiating lasers, of filling a conductive material into the holes and the grooves to form a conductor pattern and of removing the resist layer to project a portion of the conductor pattern out of the surface of the insulating layer.Type: GrantFiled: December 6, 2007Date of Patent: December 13, 2011Assignee: Hitachiviamechanics, Ltd.Inventors: Kunio Arai, Hiroshi Aoyama, Yasuhiko Kanaya
-
Method for planarization of wafer and method for formation of isolation structure in top metal layer
Patent number: 8058175Abstract: The invention discloses a planarization method for a wafer having a surface layer with a recess, comprises: forming an etching-resist layer on the surface layer to fill the entire recess; etching the etching-resist layer and the surface layer, till the surface layer outside the recess is flush to or lower than the bottom of the recess, the etching speed of the surface layer being higher than that of the etching-resist layer; removing the etching-resist layer; and etching the surface layer to a predetermined depth. The method can avoid concentric ring recesses on the surface of the wafer resulted from a chemical mechanical polishing (CMP) process in the prior art, and can be used to obtain a wafer surface suitable for optical applications.Type: GrantFiled: September 10, 2007Date of Patent: November 15, 2011Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Herb He Huang, Xianyong Pu, Yi'nan Han, Yiqun Chen -
Patent number: 8029687Abstract: The present invention provides a low-cost polishing slurry having excellent effect with respect to defects and smoothness of the surface to be polished. The polishing slurry comprises a silica abrasive and a ceria abrasive, wherein the silica abrasive content is less than 3 mass % and the ceria abrasive content is less than 1 mass %, based on the entire polishing slurry. Further, the present invention provides a method for producing a crystallized glass substrate for an information recording medium, wherein the method use a polishing slurry of the present invention. Furthermore, the present invention provides a method for producing an information recording medium, comprising forming a recording layer on a crystallized glass substrate for an information recording medium obtained by the present method.Type: GrantFiled: August 29, 2005Date of Patent: October 4, 2011Assignee: Showa Denko K.K.Inventors: Katsuaki Aida, Hiroyuki Machida, Kazuyuki Haneda
-
Patent number: 7955510Abstract: The present invention generally provides apparatus and methods for selectively removing various oxides on a semiconductor substrate. One embodiment of the invention provides a method for selectively removing an oxide on a substrate at a desired removal rate using an etching gas mixture. The etching gas mixture comprises a first gas and a second gas, and a ratio of the first gas and a second gas is determined by the desired removal rate.Type: GrantFiled: December 18, 2009Date of Patent: June 7, 2011Assignee: Applied Materials, Inc.Inventors: Reza Arghavani, Chien-Teh Kao, Xinliang Lu
-
Publication number: 20110128535Abstract: A nano-porous composition, a substrate thereof, and an article thereof, that can be used, for example, for Surface Enhanced Raman spectroscopy (SERS), and like applications. The disclosure also provides methods of making the nano-porous compositions, articles, and methods for SERS imaging, as defined herein.Type: ApplicationFiled: November 23, 2010Publication date: June 2, 2011Inventors: David Eugene Baker, Carl Wilson Ponader, Marcel Potuzak, Alranzo Boh Ruffin, Millicent Kaye Weldon Ruffin
-
Patent number: 7950136Abstract: A process to manufacturing a TMR read head with improved voltage breakdown is performed by laying down the AP1 layer as two or more layers. Each AP1 sub-layer is exposed to a low energy plasma for a short time before the next layer is deposited. This results in a smooth surface, onto which to deposit the tunneling barrier layer, with no disruption of the surface crystal structure of the completed AP1 layer.Type: GrantFiled: May 12, 2008Date of Patent: May 31, 2011Assignee: Headway Technologies, Inc.Inventors: Tong Zhao, Chyu-Jiuh Torng, Hui-Chuan Wang
-
Patent number: 7947190Abstract: An apparatus for applying different amounts of pressure to different locations of a backside of a semiconductor device structure during polishing thereof. The apparatus is configured to be associated with a wafer carrier of a polishing apparatus and includes pressurization structures configured to be biased against the backside of the semiconductor device structure during polishing thereof. The pressurization structures are independently movable with respect to one another. The amount of force or pressure applied by each pressurization structure to the backside of the semiconductor device structure is controlled by at least one corresponding actuator. The actuator may magnetically facilitate movement of the corresponding pressurization structure toward or away from the backside of the semiconductor device structure. The actuator may alternatively comprise a positive or negative pressure source.Type: GrantFiled: November 17, 2003Date of Patent: May 24, 2011Assignee: Round Rock Research, LLCInventor: Nathan R. Brown
-
Publication number: 20110097602Abstract: An improved magnetic shield for a perpendicular magnetic write head is disclosed. Its main feature is a pair of tabs at the shield's bottom corners. Said tabs are significantly wider at their point of attachment to the shield than further away from the shield. The end portions of each tab slope upwards (away from the ABS) at an angle of about ten degrees. A process for manufacturing the shield is also disclosed.Type: ApplicationFiled: October 26, 2009Publication date: April 28, 2011Inventors: Zhigang Bai, Yuchen Zhou, Joe Smyth, Moris Dovek, Yan Wu
-
Publication number: 20110079579Abstract: Molecular glass based planarizing compositions for lithographic processing are disclosed. The processes generally include casting the planarizing composition onto a surface comprised of lithographic features, the planarizing composition comprising at least one molecular glass and at least one solvent; and heating the planarizing composition to a temperature greater than a glass transition temperature of the at least one molecular glass. Exemplary molecular glasses include polyhedral oligomeric silsesquioxane derivatives, calixarenes, cyclodextrin derivatives, and other non-polymeric large molecules.Type: ApplicationFiled: October 6, 2009Publication date: April 7, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert D. Allen, Mark W. Hart, Ratnam Sooriyakumaran
-
Publication number: 20110068003Abstract: Disclosed are an indium Tin Oxide (ITO) target, a method for manufacturing the same, a transparent conductive film of ITO, and a method for manufacturing the transparent conductive film of ITO. The ITO target includes at least one oxide selected from the group consisting of Sm2O3 and Yb2O3, wherein an amount of the oxide is about 0.5 wt. % to about 10 wt. % based on the weight of the target.Type: ApplicationFiled: November 24, 2010Publication date: March 24, 2011Applicant: SAMSUNG CORNING PRECISION GLASS CO., LTD.Inventors: Bon Kyung KOO, Han Ho Yoon, Ju Ok Park, Hyung Ryul Park, Hyun Su Kim, Sung Ryong Choi, Joong Ryeol Choi, Pung Keun Song, Joon-Hong Park
-
Patent number: 7884021Abstract: A method for fabricating a micro structure includes disposing a sacrificial material in a recess formed in a lower layer and forming a layer of compensatory material on the sacrificial material in the recess. The compensatory material is higher than the upper surface of the lower layer. A first portion of the compensatory material is removed to form a substantially flat surface on the sacrificial material. The substantially flat surface is substantially co-planar with the upper surface of the lower layer. An upper layer is formed on the lower layer and the substantially flat surface.Type: GrantFiled: February 27, 2007Date of Patent: February 8, 2011Assignee: Spartial Photonics, Inc.Inventors: Shaoher X. Pan, Chii Guang Lee
-
Patent number: 7883634Abstract: An elevator load bearing member assembly includes at least one traction enhancing surface (46) on a jacket (44). In one example, a mechanical removal process is used to strip away at least some of an amide-rich layer from the surface (46) after the jacket has been extruded onto tension members (42). In another example, a chemical removal process is used. Another disclosed example includes disrupting the surface.Type: GrantFiled: February 9, 2005Date of Patent: February 8, 2011Assignee: Otis Elevator CompanyInventors: Mark S. Thompson, John P. Wesson, William A. Veronesi, Hugh J. O'Donnell, John Pitts, William C. Perron, Ary O. Mello, Kathryn Rauss
-
Publication number: 20100327987Abstract: The present invention relates to a crystal element manufacturing method for manufacturing a plurality of crystal elements at a wafer level, and to a crystal resonator manufactured by this method. The method is comprised when the frequencies of the crystal elements are adjusted by adjusting the thickness of a crystal wafer that constitutes the crystal element in two stages by partial wet etching, the thicknesses of a large number of the step sections are coarse-adjusted in a first stage by collectively subjecting the step sections to partial wet etching, and then variations in the thicknesses of each group of a small number of the step sections are fine-adjusted in a second stage by collectively subjecting the step sections to partial wet etching.Type: ApplicationFiled: June 18, 2010Publication date: December 30, 2010Applicant: NIHON DEMPA KOGYO CO., LTD.Inventor: Takehiro Takahashi
-
Patent number: 7799692Abstract: Treatment of a semiconductor wafer employs: a) position-dependent measuring of a parameter characterizing the semiconductor wafer to determine a position-dependent value of the parameter over an entire surface of the semiconductor wafer, b) oxidizing the entire surface of the semiconductor wafer under the action of an oxidizing agent with simultaneous exposure of the entire surface, the oxidation rate and thus the thickness of the resulting oxide layer dependent on the light intensity at the surface of the semiconductor wafer, and c) removing of the oxide layer, the light intensity in step b) predefined in a position-dependent manner such that differences in the position-dependent values of the parameter measured are reduced by the position-dependent oxidation rate resulting in step b) and subsequent removal of the oxide layer in step c).Type: GrantFiled: May 17, 2007Date of Patent: September 21, 2010Assignee: Siltronic AGInventors: Brian Murphy, Diego Feijóo, Reinhold Wahlich
-
Patent number: 7771603Abstract: A process for polishing a glass substrate, which enables to polish a glass substrate having a large waviness formed by mechanical polishing, to have a surface excellent in flatness, is provided. A process for polishing a glass substrate, comprising a step of measuring the surface profile of a mechanically polished glass substrate to identify the width of waviness present in the glass substrate, and a step of applying dry etching using a beam having a beam size in FWHM (full width of half maximum) value of at most the above size of waviness, to polish the surface of the glass substrate.Type: GrantFiled: July 18, 2007Date of Patent: August 10, 2010Assignee: Asahi Glass Company, LimitedInventors: Koji Otsuka, Masabumi Ito, Hiroshi Kojima
-
Publication number: 20100176084Abstract: Disclosed is a squeeze for a screen printer. The present invention provides a squeeze for a screen printer, which coats a printed circuit board with an adhesive paste while moving parallel over a metal mask on the printed circuit board, the printed circuit board being open through an opening of the metal mask, the squeeze including a solvent storage unit for storing solvents; and solvent discharging holes for discharging the solvents, stored in the solvent storage unit, to an adhesive paste. Accordingly, the squeeze for a screen printer of the present invention may be useful to prevent a dog ear phenomenon, namely that an adhesive paste layer is asymmetrically formed in an indented manner, by controlling a viscosity of an adhesive paste by discharging a solvent onto an adhesive paste layer that comes in contact with the squeeze when the adhesive paste layer is formed in the printed circuit board.Type: ApplicationFiled: March 25, 2010Publication date: July 15, 2010Inventors: Young-Ju KANG, Joon-Mo SEO, Goo-Yun CHUNG, Jeong-Ill CHOI, Seong-Hwan JANG
-
Patent number: 7740903Abstract: A method for manufacturing magnetic recording media is provided, by which a magnetic recording medium that has a recording layer formed in a concavo-convex pattern, a sufficiently flat surface, and good recording/reproducing properties can be manufactured. The method includes the steps of: depositing a first filling material over a workpiece to cover recording elements formed as convex portions of the concavo-convex pattern, and to fill at least part of a concave portion; depositing a detection material over the first filling material; depositing a second filling material over the detection material; and irradiating a surface of the workpiece with a process gas to flatten the surface. In the flattening step, a component of the detection material removed from and flying off the workpiece is detected to stop the irradiation with the process gas based on a result of detecting the component of the detection material.Type: GrantFiled: February 21, 2007Date of Patent: June 22, 2010Assignee: TDK CorporationInventors: Takahiro Suwa, Kazuhiro Hattori, Shuichi Okawa
-
Publication number: 20100140218Abstract: Methods of patterning a substrate including creating a multi-layered structure by forming, on the substrate, a patterned layer having protrusions and recessions are described. A polymerizable material composition is dispense on the patterned layer defining a conformal layer, with the multi-layered structure having a crown surface facing away from the substrate. Portions of the multi-layered structure are removed to expose regions of the substrate in superimposition with the protrusions, while forming a hard mask in areas of the crown surface in superimposition with the recessions.Type: ApplicationFiled: January 19, 2010Publication date: June 10, 2010Applicant: MOLECULAR IMPRINTS, INC.Inventor: Sidlgata V. Sreenivasan
-
Publication number: 20100126961Abstract: A highly aqueous, strongly basic planarizing solution and a process for its use to reducing or essentially eliminating protrusions or projections extending generally upwardly from a generally planar surface of polysilicon film produced by Low Temperature Poly Si (LTPS) annealing a film of amorphous silicon deposited on a substrate; the process including contacting the surface of the generally planar polysilicon film with the highly aqueous, strongly basic solution for a time sufficient to selectively etch the protrusions or projections from the surface of the generally planar polysilicon film without any significant etching of the generally planar polysilicon film, said highly aqueous, strongly basic solution being a solution having a pH of 12 or higher and comprising water, at least one strong base, and at least one etch rate control agent.Type: ApplicationFiled: February 19, 2008Publication date: May 27, 2010Inventors: Sang In Kim, Seong Jin Hong
-
Publication number: 20100089868Abstract: A method for producing a micromechanical component is proposed, a trench structure being substantially completely filled up by a first filler layer, and a first mask layer being applied on the first filler layer, on which in turn a second filler layer and a second mask layer are applied. A micromechanical component is also proposed, the first filler layer filling up the trench structure of the micromechanical component and at the same time forming a movable sensor structure.Type: ApplicationFiled: April 8, 2008Publication date: April 15, 2010Inventors: Roland Scheuerer, Heribert Weber, Eckhard Graf
-
Patent number: 7676904Abstract: A method of manufacturing a GMR, TMR or CPP GMR sensor having a smooth interface between magnetic and non-magnetic layers to improve sensor performance by exposing a layer to a low energy ion beam prior to depositing a subsequent layer.Type: GrantFiled: July 30, 2004Date of Patent: March 16, 2010Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Phong V. Chau, James Mac Freitag, Mustafa Michael Pinarbasi, Hua Ai Zeng
-
Publication number: 20100051581Abstract: A method for cleaning and refurbishing a chamber component includes placing a chamber component having process deposits on an exterior surface in a plasma vapor deposition chamber. The chamber component is bombarded with a plasma comprising Argon for a period of time sufficient to remove the process deposits from the exterior surface of the chamber component.Type: ApplicationFiled: August 26, 2008Publication date: March 4, 2010Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jian-Bin CHIOU, Wen-Cheng Cheng, Wen-Sheng Wu
-
Publication number: 20100051577Abstract: The present disclosure includes devices, methods, and systems for processing copper and, in particular, copper layer processing using sulfur plasma, One or more embodiments can include a method of forming a copper sulfur compound by reacting copper with a plasma gas including sulfur and removing at least a portion of the copper sulfur compound with water.Type: ApplicationFiled: September 3, 2008Publication date: March 4, 2010Applicant: Micron Technology, Inc.Inventor: Neal R. Rueger
-
Patent number: 7657983Abstract: In a method of producing an electrode for a resonator in thin-film technology, the electrode of the resonator is embedded in an insulating layer such that a surface of the electrode is exposed, and that a surface defined by the electrode and the insulating layer is substantially planar.Type: GrantFiled: July 9, 2004Date of Patent: February 9, 2010Assignee: Avago Technologies Wireless IP (Singapore) Pte. Ltd.Inventors: Robert Aigner, Lüder Elbrecht, Stephan Marksteiner, Winfried Nessler
-
Patent number: 7615164Abstract: The invention includes etching and contact opening forming methods. In one implementation, a plasma etching method includes providing a bottom powered plasma chamber that includes a plasma generating electrode powerable at different first and second frequencies, with the first frequency being lower than the second frequency. A substrate is positioned over the electrode. A plasma is generated over the substrate with the electrode from a first applied power at the first frequency and a second applied power at the second frequency. A ratio of the first applied power to the second applied power is from 0 to 0.25 or at least 6.0. Material is etched from the substrate with the plasma.Type: GrantFiled: June 23, 2004Date of Patent: November 10, 2009Assignee: Micron Technology, Inc.Inventors: Bradley J. Howard, Max F. Hineman
-
Patent number: 7582218Abstract: A method for merging sensor field-mill and electronic lapping guide material placement for a partial mill process and sensor formed according to the method is disclosed. An electronic lapping guide is formed coplanar with a sensor. The coplanar electronic lapping guide and sensor are processed to provide the electronic lapping guide and sensor with predetermined dimensions. The merging of the sensor field-mill and placement of the electronic lapping guide material for partial mill CPP eliminates steps and therefore the cycle time. Moreover, the electronic lapping guide region is raised to the height of the sensor plane to allow the sensor and electronic lapping guide to be defined in the same focal plane of the optics.Type: GrantFiled: April 3, 2006Date of Patent: September 1, 2009Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventor: David John Seagle
-
Publication number: 20090206348Abstract: A composite substrate (1) comprising a substrate body (2) and a utility layer (31) fixed on the substrate body (2). A planarization layer (4) is arranged between the utility layer (31) and the substrate body (2). A method for producing a composite substrate (1) applies a planarization layer (4) on a provided utility substrate (3). The utility substrate (3) is fixed on a substrate body (2) for the composite substrate (1). The utility substrate (3) is subsequently separated, wherein a utility layer (31) of the utility substrate (3) remains for the composite substrate (1) on the substrate body (2).Type: ApplicationFiled: April 20, 2007Publication date: August 20, 2009Applicant: Osram Opto Semiconductors GmbHInventors: Volker Hârle, Uwe Strauss, Georg Brüderl, Christoph Eichler, Adrian Avramescu
-
Publication number: 20090184325Abstract: A method of planarizing a substrate. An organic layer is formed on a base substrate to cover a metal line formed on the base substrate. A portion of the organic layer is removed to form a pre-planarization layer exposing the metal layer, so that a surface of the base substrate having the metal line is planarized. The pre-planarization layer is cured to flow toward a side surface of the metal line to form a planarization layer making contact with the side surface of the metal line. Therefore, a stepped portion between the base substrate and the metal line can be minimized or substantially eliminated, thereby increasing the surface uniformity of a subsequent layer, thereby improving the reliability of the manufacturing process.Type: ApplicationFiled: December 9, 2008Publication date: July 23, 2009Applicant: Samsung Electronic Co., Ltd.Inventors: Jeong-Min PARK, Doo-Hee JUNG, Hi-Kuk LEE, Young-Wook LEE
-
Publication number: 20090178563Abstract: Improved micro-columns and methods for producing micro-columns particularly suitable for use in gas chromatographs are disclosed. In particular, following deposition of the stationary phase coating, the micro-columns are subjected to a postcoating treatment with a molecule that binds to the active sites in the stationary phase micro-column thereby eliminating or reducing loss of gas chromatograph performance associated with those active sites. The postcoating treatment molecule binds to the same active sites as the analytes of interest.Type: ApplicationFiled: December 18, 2008Publication date: July 16, 2009Inventors: Richard I. Masel, Mark Shannon, Adarsh D. Radadia, Kuan-Lun Chu
-
Patent number: 7544305Abstract: A shallow trench isolation (STI) multistage chemical mechanical polishing (CMP) method for forming a shallow trench isolation structure is provided. The substrate comprising a dense region and an isolation region, a silicon nitride layer formed over the substrate, a plurality of trenches formed in the silicon nitride layer and the substrate, an oxide layer formed over the substrate, filling the trenches, wherein a width of the trenches in the dense region is smaller than that in the isolation region. A first polishing step is performed to remove a portion of the silicon oxide layer until a thickness of the remaining portion of the oxide layer reaches a predetermined thickness. A second polishing step is performed to remove a portion of the remaining portion of the silicon oxide layer until the silicon nitride layer is exposed.Type: GrantFiled: September 28, 2007Date of Patent: June 9, 2009Assignee: United Microelectronics Corp.Inventors: Chia-Jung Hsu, Art Yu, Hsiao-Ling Lu, Teng-Chun Tsai
-
Patent number: 7524427Abstract: Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material. Some embodiments use different seed layer materials and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while other embodiments apply the materials in blanket fashion. Some embodiments remove extraneous depositions (e.g. depositions to regions unintended to form part of a layer) via planarization operations while other embodiments remove the extraneous material via etching operations.Type: GrantFiled: January 3, 2005Date of Patent: April 28, 2009Assignee: Microfabrica Inc.Inventors: Adam L. Cohen, Michael S. Lockard, Kieun Kim, Qui T. Le, Gang Zhang, Uri Frodis, Dale S. McPherson, Dennis R. Smalley
-
Publication number: 20090101625Abstract: Improved silicon carbide particles, improved silicon carbide abrasive particles, and abrasive slurry compositions for use chemical mechanical planarization (CMP) processes. The particles can comprise nano-sized silicon carbide particles, particularly silicon carbide particles having a surface chemistry similar to silica.Type: ApplicationFiled: October 3, 2008Publication date: April 23, 2009Applicant: Saint-Gobain Ceramics and Plastics, Inc.Inventors: Abhaya K. Bakshi, Isaac K. Cherian
-
Patent number: 7517462Abstract: Some embodiments of the present invention are directed to techniques for building up single layer or multi-layer structures on dielectric or partially dielectric substrates. Certain embodiments deposit seed layer material directly onto substrate materials while other embodiments use an intervening adhesion layer material. Some embodiments use different seed layer materials and/or adhesion layer materials for sacrificial and structural conductive building materials. Some embodiments apply seed layer and/or adhesion layer materials in what are effectively selective manners while other embodiments apply the materials in blanket fashion. Some embodiments remove extraneous depositions (e.g. depositions to regions unintended to form part of a layer) via planarization operations while other embodiments remove the extraneous material via etching operations.Type: GrantFiled: January 3, 2005Date of Patent: April 14, 2009Assignee: Microfabrica Inc.Inventors: Adam L. Cohen, Michael S. Lockard, Kieun Kim, Qui T. Le, Gang Zhang, Uri Frodis, Dale S. McPherson, Dennis R. Smalley
-
Patent number: 7510664Abstract: Fabrication apparatus and methods are disclosed for shaping and finishing difficult materials with no subsurface damage. The apparatus and methods use an atmospheric pressure mixed gas plasma discharge as a sub-aperture polisher of, for example, fused silica and single crystal silicon, silicon carbide and other materials. In one example, workpiece material is removed at the atomic level through reaction with fluorine atoms. In this example, these reactive species are produced by a noble gas plasma from trace constituent fluorocarbons or other fluorine containing gases added to the host argon matrix. The products of the reaction are gas phase compounds that flow from the surface of the workpiece, exposing fresh material to the etchant without condensation and redeposition on the newly created surface. The discharge provides a stable and predictable distribution of reactive species permitting the generation of a predetermined surface by translating the plasma across the workpiece along a calculated path.Type: GrantFiled: November 1, 2001Date of Patent: March 31, 2009Assignee: RAPT Industries, Inc.Inventor: Jeffrey W. Carr