Irradiating, Ion Implanting, Alloying, Diffusing, Or Chemically Reacting The Substrate Prior To Ethching To Change Properties Of Substrate Toward The Etchant Patents (Class 216/87)
-
Publication number: 20040104199Abstract: A combined wet etching method for stacked films which is capable of performing etching processes in a collective manner while controlling an amount of side-etching on each of stacked films and of making uniform side edges. In the wet etching method, two or more types of etching methods are performed in combination, on stacked films containing first and second films being deposited sequentially on a substrate and each having a different film property. The two or more types of wet etching methods include, at least, a first wet etching method in which side-etching on the first film is facilitated more than side-etching on the second film and a second wet etching method in which side-etching on the second film is facilitated more than side-etching on the first film.Type: ApplicationFiled: November 12, 2003Publication date: June 3, 2004Applicant: NEC LCD TECHNOLOGIES LTDInventors: Tadanori Uesugi, Shigeru Kimura
-
Patent number: 6743724Abstract: A method of manufacturing semiconductor devices using an improved chemical mechanical planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved chemical mechanical planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer filling in between the surface irregularities prior to the planarization of the surface through a chemical mechanical planarization process.Type: GrantFiled: April 11, 2001Date of Patent: June 1, 2004Assignee: Micron Technology, Inc.Inventors: Trung T. Doan, Guy T. Blalock, Mark Durcan, Scott G. Meikle
-
Publication number: 20040079730Abstract: Known electron beam lithography used for manufacturing male molds is cost-intensive and very time consuming. As a result, conventional highly sensitive electron beam resists have an insufficient plasma etching resistance and galvanic molding makes special demands on the structural profile and the thermal stability and solubility of the resist structures. The novel production and use of lithographically produced resist structures as male mold material for use in imprint lithography for producing microstructures and nanostructures should thus overcome the drawbacks associated with the conventional procedure for producing male molds. To this end, a negative resist system is used whose lithographically produced structures correspond to the demands made on a male mold for molding thin polymer layers. Lithographically produced structures comprised of curable materials are thus used for molding, preferably those based on photo-reactive epoxy resins.Type: ApplicationFiled: June 5, 2003Publication date: April 29, 2004Inventors: Gisel Ahrens, Gabi Gruetzner, Karl Pfeiffer, Freimuth Reuther
-
Patent number: 6723487Abstract: There can be provided a method for producing a pattern film-coated article which has excellent film formability, can remove unexposed portions of a film completely in the development step after exposing the film to light. and has excellent pattern accuracy; and a photosensitive composition. The method for producing a pattern film-coated article comprises the steps of coating a photosensitive composition comprising an organometallic or organosilicon compound having photosensitivity and a hydrolyzable metal or silicon alkoxide on a substrate, irradiating the coated film on the substrate with light to polymerize the exposed portions of the coated film and then dissolving unexposed portions to remove them, wherein a pattern film-coated article is produced from an allyl group-containing metal or silicon alkoxide as the organometallic or organosilicon compound.Type: GrantFiled: September 12, 2001Date of Patent: April 20, 2004Assignees: Nippon Sheet Glass Co., Ltd.Inventors: Tsutomu Minami, Masahiro Tatsumisago, Kiyoharu Tadanaga, Atsunori Matsuda, Mitsuhiro Kawadu, Koichiro Nakamura, Hiroaki Yamamoto
-
Publication number: 20040065545Abstract: Provided is a sputtering target, backing plate or apparatus inside a sputtering device in which an electrical discharge machining mark is formed on the face to which unwanted films during sputtering are deposited, and the electrical discharge machining mark is formed from numerous inclined protrusions having a depression angle of less than 90°. When necessary, chemical etching is further performed to the portions subject to such electrical discharge machining. Thereby, the separation and flying of deposits arising from the face to which unwanted films of the target, backing plate and apparatus inside the sputtering device are deposited can be prevented.Type: ApplicationFiled: August 11, 2003Publication date: April 8, 2004Inventor: Hideyuki Takahashi
-
Patent number: 6709605Abstract: Provided is an etching method of accurately forming a fine structure in a plastic substrate. A surface reformed layer insoluble by an etchant, for example, limonene is formed on a surface of a substrate soluble by the etchant by ion implantation treatment; an opening is formed in the surface reformed layer by dry etching treatment; and the substrate is subjected to wet etching treatment by dipping the substrate in the etchant. A peripheral portion, around the opening, of the surface reformed layer functions as a mask to allow the wet etching to anisotropically proceed, and a portion, on the side opposed to the opening, of the surface reformed layer functions as an end point of the wet etching. As a result, a recess having a uniform inner diameter in the depth direction can be formed in the substrate.Type: GrantFiled: December 21, 2001Date of Patent: March 23, 2004Assignee: Sony CorporationInventors: Minehiro Tonosaki, Koji Kitagawa
-
Patent number: 6696224Abstract: A method of masking and etching a semiconductor substrate includes forming a layer to be etched over a semiconductor substrate. An imaging layer is formed over the layer to be etched. Selected regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask. In one implementation, an ion implant lithography method of processing a semiconductor includes forming a layer to be etched over a semiconductor substrate. An imaging layer of a selected thickness is formed over the layer to be etched. Selected regions of the imaging layer are ion implanted to change solvent solubility of implanted regions versus non-implanted regions of the imaging layer, with the selected regions not extending entirely through the imaging layer thickness.Type: GrantFiled: November 12, 2002Date of Patent: February 24, 2004Assignee: Micron Technology, Inc.Inventor: J. Brett Rolfson
-
Patent number: 6673252Abstract: A method of fabricating a refractive silicon microlens by using micro-machining technology. The method of fabricating a refractive silicon microlens according to the present invention comprises the steps of forming a boron-doped region on a silicon substrate, and selectively removing regions of the substrate except for the boron-doped region to form a lens comprised of only the boron-doped region. With the method of the present invention, it is possible to fabricate a two-dimensional infrared silicon microlens array. By using such a two-dimensional infrared silicon microlens array in an infrared sensor, the detectivity of the infrared sensor can be increased by 3.4 times, which is the refraction index of silicon. In addition, the two-dimensional infrared silicon microlens array of the present invention can be used with commercial infrared telecommunication devices.Type: GrantFiled: December 29, 2000Date of Patent: January 6, 2004Assignee: Korea Advanced Institute of Science and TechnologyInventors: Choon Sup Lee, Chul Hi Han
-
Publication number: 20030235385Abstract: A sub-micron structure is fabricated in a transparent dielectric material by focusing femtosecond laser pulses into the dielectric to create a highly tapered modified zone with modified etch properties. The dielectric material is then selectively etched into the modified zone from the direction of the narrow end of the tapered zone so that as the selective etching proceeds longitudinally into the modified zone, the progressively increasing width of the modified zone compensates for lateral etching occurring closer to the narrow end so as to produce steep-walled holes. The unetched portion of the modified zone produced by translating the laser beam close to and parallel to the bottom surface of the dielectric can serve as an optical waveguide to collect light from or deliver light to the etched channel which can contain various biological, optical, or chemical materials for sensing applications.Type: ApplicationFiled: May 8, 2003Publication date: December 25, 2003Inventors: Rod Taylor, Cyril Hnatovsky, Paul Corkum, David Rayner, Ravi Bhardwaj
-
Patent number: 6663720Abstract: A method of prevention maintenance preventing parts of an etcher from being eroded is disclosed. First, a layer of hydrogen-free chemical compound is formed on surface of the parts of the etcher according to one embodiment of the present invention. Otherwise, the parts of the etcher are immersed into a tank containing hydrogen-free chemical compound according to another embodiment of the present invention. After that, a standard process of prevention maintenance is performed by a cleaning agent.Type: GrantFiled: June 26, 2001Date of Patent: December 16, 2003Assignee: Mosel Vitelic Inc.Inventors: Chiang Wen-Peng, Hsu Ching-Ho
-
Patent number: 6647995Abstract: A method and system for eliminating post etch residues is disclosed. In one method embodiment, the present invention recites disposing a surface, having post etch residues adhered thereto, proximate to an electron beam source which generates electrons. The present method embodiment then recites bombarding the post etch residues with the electrons such that the post etch residues are removed from the surface to which the post etch residues were adhered.Type: GrantFiled: June 27, 2001Date of Patent: November 18, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Jiahua Huang, Yue-Song He, Frank Mak
-
Patent number: 6641662Abstract: A method for fabricating ultra-thin single-crystal metal oxide wave retarder plates, such as a zeroth-order X-cut single-crystal LiNbO3 half-wave plate, comprises ion implanting a bulk birefringent metal oxide crystal at normal incidence through a planar major surface thereof to form a damage layer at a predetermined distance d below the planar major surface, and detaching a single-crystal wave retarder plate from the bulk crystal by either chemically etching away the damage layer or by subjecting the bulk crystal having the damage layer to a rapid temperature increase to effect thermally induced snap-off detachment of the wave retarder plate. The detached wave retarder plate has a predetermined thickness d dependent on the ion implantation energy.Type: GrantFiled: March 30, 2001Date of Patent: November 4, 2003Assignee: The Trustees of Columbia University in the City of New YorkInventors: Antonije M. Radojevic, Richard M. Osgood, Jr., Miguel Levy
-
Patent number: 6641745Abstract: A method of forming a manifold through a substrate of a printhead substructure is disclosed. The substrate has an ink reservoir-facing side and an opposing transducer-supporting side. The transducer-supporting side of the substrate is introduced to an etchant. A laser beam is used to irradiate the etchant contacting side of the substrate. The irradiated areas of the substrate are thereby etched to define a first portion of the manifold therein. A second portion of the manifold is formed, preferably by sand blasting, to connect to the first portion. A printhead substructure that includes a substrate having a manifold formed according to the method is also disclosed.Type: GrantFiled: November 16, 2001Date of Patent: November 4, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventors: Kee Cheong Tan, Pean Lim, Kiong Chin Chng
-
Patent number: 6638895Abstract: A method of fabricating high aspect ratio ceramic structures in which a selected portion of perovskite or perovskite-like crystalline material is exposed to a high energy ion beam for a time sufficient to cause the crystalline material contacted by the ion beam to have substantially parallel columnar defects. Then selected portions of the material having substantially parallel columnar defects are etched leaving material with and without substantially parallel columnar defects in a predetermined shape having high aspect ratios of not less than 2 to 1. Etching is accomplished by optical or PMMA lithography. There is also disclosed a structure of a ceramic which is superconducting at a temperature in the range of from about 10° K. to about 90° K. with substantially parallel columnar defects in which the smallest lateral dimension of the structure is less than about 5 microns, and the thickness of the structure is greater than 2 times the smallest lateral dimension of the structure.Type: GrantFiled: October 25, 2000Date of Patent: October 28, 2003Assignee: The University of ChicagoInventors: Goran T. Karapetrov, Wai-Kwong Kwok, George W. Crabtree, Maria Iavarone
-
Patent number: 6620331Abstract: The invention relates to a method for etching an opening, and more precisely, to etching in a silicon plate for creating a nozzle opening. According to the invention, one side of the silicon plate (1) is protected by a protective layer (2), and a recess (5) is made in the protective layer. Etching is made anisotropically through the recess so as to create a cavity (4) in the shape of a truncated pyramid of a predetermined depth in the silicon plate. The cavity is doped so as to create a doped layer (3) at the predetermined depth. The etching is then continued until the bottom surface of the cavity has passed the doped layer. Subsequently, etching is performed from the other side, while a voltage is applied to the doped layer, so as to free the nozzle opening at the other side. The invention enables an accurate control of the surface area of the nozzle opening. Through this, the amount of discharged fluid and the directional precision can be controlled very accurately.Type: GrantFiled: January 9, 2001Date of Patent: September 16, 2003Inventors: Thomas Laurell, Johan Drott, Johan Nilsson, Lars Wallman
-
Patent number: 6602427Abstract: A method for fabricating a micromachined optical mechanical modulator based WDM transmitter/receiver module is described. The Fabry-Perot cavity of the mechanical modulator is structured from a three-polysilicon-layer stack formed on the surface of a single crystalline silicon substrate. The polysilicon membrane and its supporting polysilicon beams of the cavity are cut from the top polysilicon layer of the stack and are released by selective etching of their underlying polysilicon. The etched underlying polysilicon layer is heavily doped and then converted into porous polysilicon by anodization in HF solution. The polysilicon membrane and its supporting polysilicon are finally released using a reactive ion etch process to avoid stiction often generated in a wet etch process. A conic hole is formed on the backside of the single crystalline silicon substrate for receiving an optical fiber that can be passively aligned with the Fabry-Perot cavity.Type: GrantFiled: August 28, 2000Date of Patent: August 5, 2003Inventor: Xiang Zheng Tu
-
Patent number: 6596642Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.Type: GrantFiled: July 11, 2002Date of Patent: July 22, 2003Assignee: Micron Technology, Inc.Inventors: Zhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan, Alan R. Reinberg, Kin F. Ma
-
Patent number: 6589438Abstract: A device for detection of one or more analytes in a sample is disclosed. The device can simultaneously detect and quantitate multiple analytes in a sample. The device comprises an eletromagnetic radiation generator having one or more chemical sensors thereon. The chemical sensor interacts with or reacts with specific analytes in a sample. The presence of an analyte is detected by a comparison of the spectroscopic properties of the chemical sensor in the absence and presence of the analyte. A method is also disclosed for the detection and quantitation of analytes using the device of the present invention. In addition, a method of making the device of the present invention is also disclosed.Type: GrantFiled: September 25, 2002Date of Patent: July 8, 2003Assignee: The Research Foundation of State University of New YorkInventors: Frank V. Bright, Brett R. Wenner, Meagan A. Doody, Gary A. Baker
-
Patent number: 6547919Abstract: There is provided a grating fabrication device and method to form gratings on a semiconductor substrate. The substrate is loaded into a reactor filled with an etchant solution, and an array of parallel light of interference light with different periods is projected onto the substrate to etch the portion of the substrate that is exposed to the light via an oxidation-reduction reaction. At the same time, the inclination angle of the substrate is selectively varied to obtain the different grating periods.Type: GrantFiled: April 6, 2001Date of Patent: April 15, 2003Assignee: Samsung Electronics Co., Ltd.Inventor: Dong-Soo Bang
-
Patent number: 6544431Abstract: A method of forming thin film waveguide regions in lithium niobate uses an ion implant process to create an etch stop at a predetermined distance below the lithium niobate surface. Subsequent to the ion implantation, a heat treatment process is used to modify the etch rate of the implanted layer to be in the range of about 20 times slower than the bulk lithium niobate material. A conventional etch process (such as a wet chemical etch) can then be used to remove the virgin substrate material and will naturally stop when the implanted material is reached. By driving the ions only a shallow distance into the substrate, a backside etch can be used to remove most of the lithium niobate material and thus form an extremely thin film waveguide that is defined by the depth of the ion implant. Other structural features (e.g., ridge waveguides) may also be formed using this method.Type: GrantFiled: January 16, 2001Date of Patent: April 8, 2003Assignee: TriQuint Technology Holding Co.Inventors: Douglas M. Gill, Dale Conrad Jacobson
-
Patent number: 6540827Abstract: A method is provided for detaching a single-crystal film from an epilayer/substrate or bulk crystal structure. The method includes the steps of implanting ions into the crystal structure to form a damage layer within the crystal structure at an implantation depth below a top surface of the crystal structure, and chemically etching the damage layer to effect detachment the single-crystal film from the crystal structure. The thin film may be detached by subjecting the crystal structure with the ion implanted damage layer to a rapid temperature increase without chemical etching. The method of the present invention is especially useful for detaching single-crystal metal oxide films from metal oxide crystal structures. Methods for enhancing the crystal slicing etch-rate are also disclosed.Type: GrantFiled: July 18, 2000Date of Patent: April 1, 2003Assignee: Trustees of Columbia University in the City of New YorkInventors: Miguel Levy, Richard M. Osgood, Jr., Antonije M. Radojevic
-
Patent number: 6527919Abstract: A method for fabricating a stent or other medical device by creating a free standing thin film of metal.Type: GrantFiled: July 28, 2000Date of Patent: March 4, 2003Assignee: Micro Therapeutics, Inc.Inventor: Noah M. Roth
-
Publication number: 20030029839Abstract: A method of reducing the wet etch rate of silicon nitride relative to that of silicon oxide is disclosed. The method comprises implanting nitrogen-containing ions into silicon nitride films, followed by thermal annealing to repair the implant damage and concurrently promote Si—N bonding in the nitrogen-implanted films. The silicon nitride films thus treated are more resistant to oxide etchants such as HF. The present invention is particularly useful in reducing the wet etch rate of the silicon nitride formed by reacting hexachlorodisilane (Si2Cl6) with ammonia (NH3) at below 650° C.Type: ApplicationFiled: November 1, 2001Publication date: February 13, 2003Applicant: Winbond Electronics Corp.Inventor: Pao-Hwa Chou
-
Patent number: 6511609Abstract: A novel method of Cu seed layer deposition for ULSI metalization is disclosed. The method of Cu seed layer deposition for ULSI metalization comprises forming a diffusion barrier on a substrate, forming a poly silicon layer, amorphous silicon layer or TaSix layer on said diffusion barrier, replacing said poly silicon layer with copper to form a copper seed layer, and electroplating a thick copper film on said copper seed layer. In this invention, a chemical replacing solution comprising a replacing reactant and at least one etchant is used to replace the poly silicon layer with copper and to reduce the quantity of byproducts of the reaction.Type: GrantFiled: February 20, 2001Date of Patent: January 28, 2003Assignee: Industrial Technology Research InstituteInventors: Ching-Han Jan, Fon-Shan Huang, Jih-Wen Wang
-
Publication number: 20020189756Abstract: A system to fabricate precise, high aspect ratio polymeric molds by photolithograpic process is described. The molds for producing micro-scale parts from engineering materials by the LIGA process. The invention is a developer system for developing a PMMA photoresist having exposed patterns comprising features having both very small sizes, and very high aspect ratios between part minimum feature size and part overall dimension. The developer system of the present invention comprises a developer tank, an intermediate rinse tank and a final rinse tank, each tank having a source of high frequency sonic agitation, temperature control, and continuous filtration.Type: ApplicationFiled: August 12, 2002Publication date: December 19, 2002Inventors: Dale R. Boehme, Michelle A. Bankert, Todd R. Christenson
-
Publication number: 20020160298Abstract: There can be provided a method for producing a pattern film-coated article which has excellent film formability, can remove unexposed portions of a film completely in the development step after exposing the film to light. and has excellent pattern accuracy; and a photosensitive composition.Type: ApplicationFiled: September 12, 2001Publication date: October 31, 2002Inventors: Tsutomu Minami, Masahiro Tatsumisago, Kiyoharu Tadanaga, Atsunori Matsuda, Mitsuhiro Kawadu, Koichiro Nakamura, Hiroaki Yamamoto
-
Patent number: 6465156Abstract: The present invention relates to a method for mitigating formation of silicon grass. A silylation process is performed on a semiconductor structure, the structure including a photoresist layer, an underlayer under the photoresist layer, and a substrate under the underlayer. A chemical mechanical polishing process is employed to remove a portion of the photoresist layer.Type: GrantFiled: October 21, 1999Date of Patent: October 15, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Bhanwar Singh, Bharath Rangarajan, Steven Avanzino
-
Patent number: 6461967Abstract: Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and the high stress masked portion of the material is selectively removed, preferably by an etching process. The low stress portion of the material remains and forms a shaped structure. One preferred selective etching process uses a basic etchant. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.Type: GrantFiled: July 16, 2001Date of Patent: October 8, 2002Assignee: Micron Technology, Inc.Inventors: Zhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan, Alan R. Reinberg, Kin F. Ma
-
Publication number: 20020139769Abstract: A laser direct write method creates true three dimensional structures within photocerams using an focused pulsed ultraviolet laser with a wavelength in a weakly absorbing region of the photoceram material. A critical dose of focused laser UV light selectively exposes embedded volumes of the material for subsequent selective etching. The photoceram material exposure is nonlinear with the laser fluence and the critical dose depends on the square of the per shot fluence and the number of pulses. The laser light is focused to a focal depth for selective volumetric exposure of the material within a focal volume within the remaining collateral volumes that is critically dosed for selecting etching and batch fabrication of highly defined embedded structures.Type: ApplicationFiled: March 30, 2001Publication date: October 3, 2002Applicant: The Aerospace CorporationInventors: Henry Helvajian, Peter D. Fuqua, William W. Hansen
-
Patent number: 6453914Abstract: A method for removing organometallic and organosilicate residues remaining after a dry etch process from semiconductor substrates. The substrate is exposed to a conditioning solution of phosphoric acid, hydrofluoric acid, and a carboxylic acid, such as acetic acid, which removes the remaining dry etch residues while minimizing removal of material from desired substrate features. The approximate proportions of the conditioning solution are typically 80 to 95 percent acetic acid, 1 to 15 percent phosphoric acid, and 0.01 to 5.0 percent hydrofluoric acid.Type: GrantFiled: June 29, 1999Date of Patent: September 24, 2002Assignee: Micron Technology, Inc.Inventors: Kevin J. Torek, Donald L. Yates
-
Patent number: 6451451Abstract: There are provided methods of making hardmask assemblies or other layered structures, and other masks, including providing an annular seal member between a first surface of layered structure, preferably a hardmask assembly, and a firs clamp element, the hardmask assembly comprising at least a hardmask layer; and applying a force between the first clamp element and a second clamp element to hold the hardmask assembly between the annular seal member and the second clamp element In addition, there are provided methods further comprising etching the first surface of the hardmask assembly within the bounds of an interior space defined by the annular seal member. Furthermore, there are provided methods further comprising etching the substrate layer through the hardmask layer and/or removing the hardmask layer after etching the substrate layer.Type: GrantFiled: March 27, 2001Date of Patent: September 17, 2002Assignee: Micron Technology, Inc.Inventor: J. Brett Rolfson
-
Publication number: 20020113038Abstract: A novel method of Cu seed layer deposition for ULSI metalization is disclosed. The method of Cu seed layer deposition for ULSI metalization comprises forming a diffusion barrier on a substrate, forming a poly silicon layer, amorphous silicon layer or TaSix layer on said diffusion barrier, replacing said poly silicon layer with copper to form a copper seed layer, and electroplating a thick copper film on said copper seed layer. In this invention, a chemical replacing solution comprising a replacing reactant and at least one etchant is used to replace the poly silicon layer with copper and to reduce the quantity of byproducts of the reaction.Type: ApplicationFiled: February 20, 2001Publication date: August 22, 2002Inventors: Ching-Han Jan, Fon-Shan Huang, Jih-Wen Wang
-
Publication number: 20020096496Abstract: The invention provides a method for etching gallium nitride (GaN) comprising the steps of: providing a GaN film; imagewise amorphizing a portion of the GaN film by ion implantation to form an amorphized portion; and wet etching of the GaN film having an amorphized portion to remove the amorphized portion. When the imagewise amorphizing process can be done without a mask, such as with a focused implantation ion beam, the process itself becomes maskless.Type: ApplicationFiled: November 29, 2000Publication date: July 25, 2002Inventors: Bela Molnar, Stefanie Schiestel, Carmine Carosella
-
Patent number: 6383937Abstract: A method is disclosed for fabricating a semiconductor device structure which include a thin foot charge drain beneath the device on a silicon substrate. The structures retain high speed operation of SOI devices. In various embodiments, the invention includes forming a first diffusion-barrier layer on a semiconductor substrate, patterning the said first diffusion-barrier layer and the said silicon substrate to certain depth to form a trench, forming a second diffusion-barrier layer and patterning the said second diffusion-barrier layer to form a first spacer on the sidewall of the trench. Performing a directional etching to expose a portion of the sidewall of the trench. Introducing dopants into the said exposed sidewall to form a doped regions near the sidewall. Performing an isotropic etching using halogen gas plasma.Type: GrantFiled: November 17, 2000Date of Patent: May 7, 2002Assignee: Vanguard International Semiconductor Corp.Inventor: Horng-Huei Tseng
-
Patent number: 6365525Abstract: The invention defines a method for fabricating a semiconductor insulation layer: A semiconductor substrate is first provided; an insulation layer is applied by way of region-by-region or whole-area application to the semiconductor substrate; impurity ions are selectively implanted into at least one predetermined zone of the insulation layer; then the insulation layer is selectively etched, and the insulation layer is thereby patterned in accordance with the zone or zones of the selectively implanted impurity ions.Type: GrantFiled: December 5, 2000Date of Patent: April 2, 2002Assignee: Siemens AktiengesellschaftInventor: Karlheinz Müller
-
Patent number: 6358430Abstract: A method of etching a layer of electrical insulating material including a layer of strontium titanate on a surface of a semiconductor substrate. The layer of strontium titanate is immersed in a passivated etching solution including an acid and HF and focused light is directed onto the surface of the layer of strontium titanate at areas to be etched, so as to depassivate the passivated surface and to etch the layer of strontium titanate only at the surface receiving collimated light. In a preferred embodiment, the passivated etching solution includes HCl and less than 1000 ppm of HF.Type: GrantFiled: July 28, 1999Date of Patent: March 19, 2002Assignee: Motorola, Inc.Inventors: Daniel Scott Marshall, Lucia R. Salem, Harland G. Tompkins
-
Patent number: 6352647Abstract: Methods of making hardmask assemblies or other layered structures, and other masks, include providing an annular seal member between a first surface of layered structure, preferably a hardmask assembly, and a first clamp element, the hardmask assembly comprising at least a hardmask layer; and applying a force between the first clamp element and a second clamp element to hold the hardmask assembly between the annular seal member and the second clamp element. In addition, there are provided methods further comprising etching the first surface of the hardmask assembly within the bounds of an interior space defined by the annular seal member. Methods further comprise etching the substrate layer through the hardmask layer and/or removing the hardmask layer after etching the substrate layer.Type: GrantFiled: May 5, 1999Date of Patent: March 5, 2002Assignee: Micron Technology, Inc.Inventor: J. Brett Rolfson
-
Patent number: 6335290Abstract: In a method of etching an Al or Al alloy layer, an Al or Al alloy layer is formed on an underlying surface, the surface of the Al or Al alloy layer is processed with TMAH, a resist pattern is formed on the surface of the Al or Al alloy layer processed with TMAH, and by using the resist pattern as an etching mask, the Al or Al alloy layer is wet-etched.Type: GrantFiled: March 29, 1999Date of Patent: January 1, 2002Assignee: Fujitsu LimitedInventor: Yukimasa Ishida
-
Patent number: 6331488Abstract: A method of manufacturing semiconductor devices using an improved chemical mechanical planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved chemical mechanical planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer filling in between the surface irregularities prior to the planarization of the surface through a chemical mechanical planarization process.Type: GrantFiled: May 23, 1997Date of Patent: December 18, 2001Assignee: Micron Technology, Inc.Inventors: Trung T. Doan, Guy T. Blalock, Mark Durcan, Scott G. Meikle
-
Patent number: 6323046Abstract: A method and apparatus for endpointing a planarization process of a microelectronic substrate. In one embodiment, the apparatus may include a species analyzer that receives a slurry resulting from the planarization process and analyzes the slurry to determine the presence of an endpointing material implanted beneath the surface of the microelectronic substrate. The species analyzer may include a mass spectrometer or a spectrum analyzer. In another embodiment, the apparatus may include a radiation source that directs impinging radiation toward the microelectronic substrate, exciting atoms of the substrate, which in turn produce an emitted radiation. A radiation detector is positioned proximate to the substrate to receive the emitted radiation and determine the endpoint by determining the intensity of the radiation emitted by the endpointing material.Type: GrantFiled: August 25, 1998Date of Patent: November 27, 2001Assignee: Micron Technology, Inc.Inventor: Vishnu K. Agarwal
-
Patent number: 6315803Abstract: Object: To provide a polishing composition which is capable of polishing a tantalum-containing compound at a high stock removal rate and whereby the copper surface after polishing is scarcely corroded, and to provide a polishing process where dishing can be minimized. Means to accomplish the object: A polishing composition comprising an abrasive, oxalic acid, an ethylenediamine derivative, a benzotriazole derivative and water and not containing an oxidizing agent, and a polishing composition comprising an abrasive, oxalic acid, an ethylenediamine derivative, a benzotriazole derivative, water and hydrogen peroxide.Type: GrantFiled: December 1, 1999Date of Patent: November 13, 2001Assignee: Fujimi IncorporatedInventors: Katsuyoshi Ina, Tadahiro Kitamura
-
Patent number: 6309975Abstract: Methods are disclosed for forming shaped structures of silicon-containing material with ion implantation and an etching process which is selective to silicon-containing material implanted to a certain concentration of ions or with an etching process which is selective to relatively unimplanted silicon-containing material. In general, the methods initially involve providing a layer of silicon-containing material such as polysilicon or epitaxial silicon on a semiconductor substrate. The layer of silicon-containing material is then masked, and ions are implanted into exposed portions of the layer of silicon-containing material. The mask is removed, and the aforementioned selective etching process is conducted to result in one of an implanted and a relatively unimplanted portion of the layer of silicon-containing material being etched away and the other left standing to form a shaped structure of silicon-containing material.Type: GrantFiled: March 14, 1997Date of Patent: October 30, 2001Assignee: Micron Technology, Inc.Inventors: Zhiqiang Wu, Li Li, Thomas A. Figura, Kunal R. Parekh, Pai-Hung Pan, Alan R. Reinberg, Kin F. Ma
-
Patent number: 6279585Abstract: In a method for manufacturing a semiconductor device, a barrier metal disposed on a metallic thin film for forming a thin film resistor is patterned by wet-etching. The wet-etching produces a residue of the barrier metal. The residue is removed after the oxidation thereof. Accordingly the residue is completely removed. As a result, the patterning of the thin film resistor is stably performed, and short-circuit does not occur to a wiring pattern disposed above the barrier metal.Type: GrantFiled: September 7, 1999Date of Patent: August 28, 2001Assignee: Denso CorporationInventors: Satoshi Shiraki, Makoto Ohkawa
-
Publication number: 20010015210Abstract: A wet etching apparatus and method to shorten processing time and to eliminate formation of unintended mask pattern are described. In the conventional art, after a mask pattern is formed, alien substances such as water mist or stain are left on the substrate. The alien substances act as an etching block in the wet etching process. This generates an unintended mask pattern. The present invention uses ultraviolet light to remove the alien substances prior to the etching process. When the alien substances are removed, the intended mask pattern is generated after the etching process. The wet etching device according to the present invention includes an ultraviolet cleaner and a conveyor to convey substrates to and from the ultraviolet cleaner. Spaces for the ultraviolet cleaner and the conveyor are created in the wet etching apparatus by reducing space for cassettes and reducing space required by the loader.Type: ApplicationFiled: December 8, 2000Publication date: August 23, 2001Inventors: Soon Ho Choi, Jae Hyeob Seo
-
Patent number: 6277659Abstract: A substrate removal approach involves sensing acoustic energy in a semiconductor device as a function of substrate thickness in the device as substrate is being removed. According to an example embodiment of the present invention, a semiconductor chip having substrate at a back side that is opposite circuitry at a circuit side is analyzed. Some or all of the substrate in the back side of the semiconductor chip is removed, and a thinned region having a bottom area is formed. A laser is directed to the bottom area, and a thermal parameter characterizing target circuitry in the device is detected in response to the laser. The detected parameter is used and an indication of the remaining substrate thickness between the bottom area and the circuitry is determined. In response to the indicated thickness, the substrate removal process is controlled, making possible effective control of the substrate removal process.Type: GrantFiled: September 29, 1999Date of Patent: August 21, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Rama R. Goruganthu, Jeffrey D. Birdsley, Michael R. Bruce, Brennan V. Davis, Rosalinda M. Ring
-
Patent number: 6258497Abstract: A homogeneous marker is formed, possibly by the adsorption of trace amounts of an ambient material such as carbon monoxide gas, at a surface of a deposited material when the plasma in momentarily interrupted during plasma enhanced chemical vapor deposition or other deposition processes involving the presence of a plasma. When the deposited material is etched, the resulting crystal dislocations or adsorbed gas is detected as a marker by optical emission spectroscopy techniques. The accuracy of an end point determination of the etching process can be increased by providing a sequence of such markers within the bulk or volume of the deposited material. The markers, being merely an interface such as a slight crystal dislocation in otherwise homogeneous material, do not affect the electrical, chemical or optical properties of the remainder of the predetermined deposited material and thus the homogeneity of the deposited material is not significantly affected.Type: GrantFiled: May 24, 1995Date of Patent: July 10, 2001Assignee: International Business Machines CorporationInventors: Lawrence Andrew Kropp, David Stanasolovich, Marc Jay Weiss, Dennis Sek-On Yee
-
Patent number: 6254794Abstract: A method for preparing a semiconductor member comprises: forming a substrate having a non-porous silicon monocrystalline layer and a porous silicon layer; bonding another substrate having a surface made of an insulating material to the surface of the monocrystalline layer; and etching to remove the porous silicon layer by immersing in an etching solution.Type: GrantFiled: April 22, 1999Date of Patent: July 3, 2001Assignee: Canon Kabushiki KaishaInventors: Kiyofumi Sakaguchi, Takao Yonehara, Nobuhiko Sato
-
Patent number: 6254796Abstract: A silicate glass is selectively etched employing a composition containing a fluoride containing compound and certain organic solvents. Preferred compositions also include water.Type: GrantFiled: December 29, 1998Date of Patent: July 3, 2001Assignee: International Business Machines CorporationInventors: David L. Rath, Glenn W. Gale, Rangarajan Jagannathan, Kenneth J. McCullough, Karen P. Madden, Harald F. Okorn-Schmidt, Keith R. Pope
-
Patent number: 6253447Abstract: A method for manufacturing a thermal head comprises forming a heat generating resistor on an insulative substrate, and disposing conductors having different material properties on the heat generating resistor for supplying power to the heat generating resistor. The conductors are then etched to form a wiring electrode having a tapered peripheral edge portion as a result of the different material properties of the conductors. A protective film is then formed over the heat generating resistor and the wiring electrode.Type: GrantFiled: March 16, 1999Date of Patent: July 3, 2001Assignee: Seiko Instruments Inc.Inventors: Yuji Nakamura, Yoshinori Sato, Yoshiaki Saita
-
Patent number: 6238586Abstract: A method for preparing a semiconductor member comprises: forming a substrate having a non-porous silicon monocrystalline layer and a porous silicon layer; bonding another substrate having a surface made of an insulating material to the surface of the monocrystalline layer; and etching to remove the porous silicon layer by immersing in an etching solution.Type: GrantFiled: April 22, 1999Date of Patent: May 29, 2001Assignee: Canon Kabushiki KaishaInventors: Kiyofumi Sakaguchi, Takao Yonehara, Nobuhiko Sato