By Confining Filler Patents (Class 228/215)
  • Patent number: 11167380
    Abstract: Provided are: a flux that is for a solder paste and that can inhibit occurrence of voids; and a solder paste using the flux. This flux for a solder paste contains rosin, an imidazole compound, and a solvent, wherein the contained amount of the imidazole compound is 25-35 mass %. The flux also contains 0-20 mass % of a block organic acid and 0-3 mass % of an activator.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: November 9, 2021
    Assignee: SENJU METAL INDUSTRY CO., LTD.
    Inventors: Toru Hayashida, Rina Horikoshi
  • Patent number: 10804021
    Abstract: A chip electronic component includes a magnetic body including an insulating substrate, and an internal coil part formed on at least one surface of the insulating substrate. The internal coil part includes first coil patterns formed on the insulating substrate, second coil patterns disposed on the first coil patterns, and third coil patterns disposed on the second coil patterns, and interface parts distinguished from the first to third coil patterns are disposed on at least one of interfaces between the first and second coil patterns and interfaces between the second and third coil patterns.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: October 13, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Dong Jin Jeong
  • Patent number: 10804218
    Abstract: A semiconductor package includes a semiconductor chip that includes a first region and a second region spaced apart from the first region; a plurality of connection bumps disposed under the first region of the semiconductor chip; and a protection layer that covers a bottom surface of the semiconductor chip in the second region, wherein the protection layer does not cover the bottom surface of the semiconductor chip in the first region and is not disposed between the plurality of connection bumps. The semiconductor chip of the semiconductor package is protected by the protection layer.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: October 13, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Lyong Kim, Seung-Duk Baek
  • Patent number: 10128123
    Abstract: Micro bump interconnection structures for semiconductor devices, and more specifically, a substrate structure comprising an array of micrometer scale copper pillar based structures or micro bumps eventually comprising a solder material and a method for manufacturing the same are provided.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: November 13, 2018
    Assignee: IMEC VZW
    Inventors: Bivragh Majeed, Philippe Soussan
  • Patent number: 9777107
    Abstract: An epoxy resin represented by the following formula (1) wherein R1 represents an alkylene group having 2 to 6 carbon atoms and optionally containing an ester or ether bond; R2 represents a monovalent aliphatic hydrocarbon group having 1 to 6 carbon atoms or a monovalent aromatic hydrocarbon group having 6 to 12 carbon atoms; R3 represents an oxygen atom or a phenylene group; k represents 1 to 10 as an average value; m represents an integer of 0 to 2; n represents 0 to 10 as an average value; and a plurality of groups R1, R2, R3, k, or m present in the formula may be the same or different from each other.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: October 3, 2017
    Assignees: Shin-Etsu Chemical Co., Ltd., Nippon Kayaku Kabushiki Kaisha
    Inventors: Toshio Shiobara, Junichi Sawada, Miyuki Wakao, Tsutomu Kashiwagi, Naofusa Miyagawa, Yoshihiro Kawada, Chie Sasaki, Masataka Nakanishi, Kenichi Kuboki
  • Patent number: 9768105
    Abstract: System and method are disclosed for creating a rigid interconnect between two substrate mounted packages to create a package-on-package assembly. A solid interconnect may have a predetermined length configured to provide a predetermined package separation, may be cylindrical, conical or stepped, may be formed by extrusion, casting, drawing or milling and may have an anti-oxidation coating. The interconnect may be attached to mounting pads on the top and bottom packages via an electrically conductive adhesive, including, but not limited to solder and solder paste. A solder preservative or other anti-oxidation coating may be applied to the mounting pad. A package-on-package assembly with solid interconnects may have a top package configured to accept at least one electronic device, with the solid interconnects mounted between the top package and a bottom package to rigidly hold the package about parallel to each other.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mirng-Ji Lii, Chen-Hua Yu, Chien-Hsiun Lee, Yung Ching Chen, Jiun Yi Wu
  • Publication number: 20150115020
    Abstract: Provided is a solder bump forming method capable of forming solder bumps having a desired constant thickness, without any failure such as copper corrosion, on a mounting board such as a printed circuit board having fine copper electrodes. The solder bump forming method includes: a process in which a prepared mask (5) is placed on a prepared substrate (1) and then a molten solder jet is blown to fill an opening of the mask (5) with molten solder (11a) until the molten solder (11a) exceeds the thickness of the mask (5); a process of removing a part of the molten solder (11a) that exceeds the thickness of the mask (5) to form a solder bump (11) having a predetermined thickness; and a process of removing the mask (5). The molten solder (11a) is molten lead-free solder that includes tin as a main ingredient and at least nickel as a sub ingredient, and further includes one or more other ingredients such as silver, copper, and germanium.
    Type: Application
    Filed: April 17, 2012
    Publication date: April 30, 2015
    Applicant: TANIGUROGUMI CORPORATION
    Inventor: Katsumori Taniguro
  • Patent number: 8794502
    Abstract: Disclosed are a method of forming a solder on pad on a fine pitch PCB and a method of flip chip bonding a semiconductor device using the same. The method of forming a solder on pad on a fine pitch PCB includes: applying a solder bump maker (SBM) paste with a predetermined thickness to an entire surface of a PCB including a metal pad and a solder mask; heating the SBM paste at a temperature higher than a melting point of solder contained in the SBM paste and then cooling the SBM paste to form a solder on pad; and washing a residual polymer resin and residual solder particles of the SBM paste by using a solvent.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: August 5, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yong Sung Eom, Kwang-Seong Choi, Jung Hyun Noh
  • Patent number: 8777091
    Abstract: A light emitting member mounting method includes: causing a friction material to contact a substrate including at least an optical waveguide member mounted on a base and to contact a light emitting member that is to be mounted to the substrate and that is equipped with a light emitting component, so as to suppress relative movement between the substrate and the light emitting member using frictional force exerted on the substrate and the light emitting member, and positionally aligning the light emitting member to the substrate by employing light emitted from the light emitting component; and bonding the substrate and the light emitting member together by melting a bonding material interposed between the substrate and the light emitting member.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: July 15, 2014
    Assignee: Fujitsu Limited
    Inventors: Yoshiyuki Hiroshima, Naoki Nakamura, Akiko Matsui, Tetsuro Yamada, Takahiro Ooi, Kohei Choraku
  • Patent number: 8757474
    Abstract: A soldering method capable of alleviating positional displacement between substrates even though a step of removing flux can be omitted is provided. A temporary bonding agent 55 is applied onto multiple substrates 50a, 50b, and a heater 33 heats the substrates while the substrates are temporarily bonded with the temporary bonding agent 55 interposed therebetween, and before the solder 54 is melted or while the solder 54 is melted, the temporary bonding agent 55 is evaporated, and the substrates 50a, 50b are bonded with solder with the melted solder 54 interposed therebetween.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: June 24, 2014
    Assignee: Ayumi Industry Co., Ltd.
    Inventors: Hideyuki Abe, Kazuaki Mawatari
  • Patent number: 8584924
    Abstract: The invention relates to a novel process for producing a metal ceramic substrate, especially a copper-ceramic substrate, in which at least one metal foil at a time is applied to the surface sides of a ceramic layer or a ceramic substrate using a high temperature bonding process and the metal foil is structured on at least one surface side for forming conductive tracks, contact surfaces, and the like.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: November 19, 2013
    Assignee: Curamik Electronics GmbH
    Inventor: Jürgen Schulz-Harder
  • Patent number: 8561880
    Abstract: A process and tools for forming and/or releasing metal preforms, metal shapes and solder balls is described incorporating flexible molds or sheets, injection molded metal such as solder and in the case of solder balls, a liquid or gaseous environment to reduce or remove metal oxides prior to or during metal (solder) reflow to increase surface tension to form spherical or substantially spherical solder-balls.
    Type: Grant
    Filed: February 11, 2012
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Peter Alfred Gruber, Paul Alfred Lauro, Jae-Woong Nah
  • Patent number: 8453714
    Abstract: An exemplary heat dissipation device includes a fin assembly, a heat pipe, and a protective member. The fin assembly includes stacked fins and air passages between fins. Each fin includes a main body, an extending hole defined in the main body, and a flange extending from the main body around the extending hole. The heat pipe is received in the extending holes of the fins and abuts the flanges of the fins. The protective member includes a plurality pairs of elastic arms. Each pair of elastic arms is sandwiched between a free end of the flange of a corresponding fin and the main body of a corresponding adjacent fin to prevent solder associated with the heat pipe from flowing into the corresponding air passage.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: June 4, 2013
    Assignees: Fu Zhun Precision Industry (Shen Zhen) Co., Ltd., Foxconn Technology Co., Ltd.
    Inventors: Wei Li, Yi-Qiang Wu, Chun-Chi Chen
  • Patent number: 8408448
    Abstract: A process and tools for forming spherical metal balls is described incorporating molds, injection molded solder, a liquid or gaseous environment to reduce or remove metal oxides and an unconstrained reflow of metal in a heated liquid or gas and solidification of molten metal in a cooler liquid or gas.
    Type: Grant
    Filed: February 11, 2012
    Date of Patent: April 2, 2013
    Assignee: International Business Machines Corporation
    Inventors: Claudius Feger, Peter Alfred Gruber, Mark Harrison McLeod, Jae-Woong Nah
  • Patent number: 8408449
    Abstract: A method of controlling a bump printing apparatus includes securing a board having air holes therein to a printing table by vacuum suction using suction nozzles; bringing a mask into close contact with the board; printing solder bumps by compressing and moving a solder paste across an upper surface of the mask using a squeegee; spraying air through spray nozzles to separate the mask from the board; and terminating air spraying using the spray nozzles and terminating air suction using the suction nozzles to remove the board.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: April 2, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Joon Kon Kim
  • Patent number: 8403202
    Abstract: A method for soldering an LED to a circuit board includes firstly providing a solder-applying pattern overlaying the circuit board. First holes and second holes are defined in the solder-applying patter. Then, solder pastes are filled in the first holes and the second holes. The solder-applying pattern is removed and a plurality of first solder poles and second solder poles are remained on the circuit board. An LED is then put on the first solder poles and the second solder poles. The first solder poles and the second solder poles are heated to form a first solder ball and a second solder ball respectively after the heated first and second solder poles are cooled. The first and second solder balls electrically connect positive and second electrodes of the LED with the circuit board.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: March 26, 2013
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Chih-Chen Lai
  • Patent number: 8181846
    Abstract: A method and apparatus are provided to deposit conductive bonding material into cavities in a mold. A fill head is placed in substantial contact with a mold that includes cavities. The fill head includes a sealing member that substantially encompasses an entire area to be filled with conductive bonding material. The conductive bonding material is forced out of the fill head toward the mold. The conductive bonding material is provided into at least one cavity of the cavities contemporaneous with the at least one cavity being in proximity to the fill head.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: May 22, 2012
    Assignee: International Business Machines Corporation
    Inventors: Russell A. Budd, John P. Karidis, Mark D. Schultz
  • Patent number: 8178156
    Abstract: A surface treatment process for a circuit board is provided. The circuit board includes a substrate, a first circuit layer disposed on an upper surface of the substrate, and a second circuit layer disposed on a lower surface of the substrate. The first circuit layer is electrically connected to the second circuit layer. In the surface treatment process for the circuit board, a first oxidation protection layer and a second oxidation protection layer are respectively formed on a portion of the first circuit layer and a portion of the second circuit layer by immersion. Afterwards, the first circuit layer exposed by the first oxidation protection layer is subjected to black oxidation to form a black oxide layer. The thickness of the first oxidation protection layer is thinner than or equal to the thickness of the black oxide layer.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: May 15, 2012
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Chien-Hao Wang
  • Patent number: 8127979
    Abstract: Electronic assemblies including coreless substrates and their manufacture using electrolytic plating, are described. One method includes providing a core comprising a metal, and forming a dielectric material on the core. The method also includes forming vias in the dielectric material, the vias positioned to expose metal regions. The method also performing an electrolytic plating of metal into the vias and on the metal regions, wherein the core is electrically coupled to a power supply during the electrolytic plating of metal into the vias and delivers current to the metal regions. The method also includes removing the metal core after the electrolytic plating of metal into the vias. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 25, 2010
    Date of Patent: March 6, 2012
    Assignee: Intel Corporation
    Inventors: Tao Wu, Nicolas R. Watts
  • Patent number: 8083121
    Abstract: In the soldering method, metal-powder-contained flux is disposed between bumps and circuit electrodes when electronic parts are mounted by soldering, the metal powder comprising a core metal formed of metal such as tin and zinc and a surface metal covering surfaces of the core metal formed of noble metal such as gold and silver. Accordingly, metal powder will not remain as residue that is liable to cause migration after the reflow process, and it is possible to assure both soldering effect and insulation effect.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: December 27, 2011
    Assignee: Panasonic Corporation
    Inventors: Tadashi Maeda, Tadahiko Sakai
  • Patent number: 8083123
    Abstract: A method of manufacturing a printed wiring board having at least one solder bump includes forming a solder resist layer on a conductor layer. The solder resist layer has at least one opening that exposes a connection pad of the conductor layer, and the at least one opening in the solder resist layer has a depth D, from the solder resist layer to the exposed connection pad, of from 3 ?m to 18 ?m. The method also includes loading a solder ball into each of the at least one opening in the solder resist layer, and forming a bump on the exposed connection pad by heating the solder ball to a reflow temperature.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: December 27, 2011
    Assignee: IBIDEN Co., Ltd.
    Inventors: Katsuhiko Tanno, Youichirou Kawamura
  • Patent number: 8052035
    Abstract: A method for forming solder bodies on a substrate includes: positioning a first mask plate, which is formed with at least one first through-hole, on the substrate; filling the first through-hole with a first solder paste so as to form a first solder body on the substrate; positioning a second mask plate, which is formed with at least one second through-hole and at least one recess spaced apart from the second through-hole, on the substrate in such a manner that the first solder body is received in the recess; and filling the second through-hole with a second solder paste so as to form a second solder body on the substrate.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: November 8, 2011
    Assignees: Universal Scientific Industrial (Shanghai) Co., Ltd., Universal Global Scientific Industrial Co., Ltd.
    Inventors: Chi-Hsiung Cheng, Wan-Chen Chan, Hsun-Fa Li
  • Patent number: 7931187
    Abstract: A flexible unitary mask has a plurality of through holes. A substrate has a plurality of wettable pads in recessed regions defining volumes. The through holes are aligned with the wettable pads. Molten solder is directly injected through the through holes of the flexible unitary mask into the volumes with the wettable pads, such that the through holes and the volumes with the wettable pads are filled with solder. The solder is allowed to solidify, forming a plurality of solder structures adhered to the wettable pads. The flexible unitary mask is peeled from the substrate after the solder has solidified.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: April 26, 2011
    Assignee: International Business Machines Corporation
    Inventors: Peter A. Gruber, Paul A. Lauro, Jae-Woong Nah, Kazushige Toriyama
  • Patent number: 7900809
    Abstract: A method for assembling, and the resultant electronic module, includes attaching a chip to a substrate using a first solder interconnection array, and attaching a board to the substrate using a second solder interconnection array, which may be a single-melt or a dual-melt solder array. The second solder interconnection array resides entirely within a space defined between the board and substrate. A creep resistant structure is provided within this space for maintaining the defined space and optimizing integrity of the second solder interconnection array. The creep resistant structure may include an underfill material, balls, brackets, frames, collars or combinations thereof. Wherein the creep resistant structure is an underfill material, it is crucial that the substrate be attached to the board before either entirely encapsulating the second interconnection array with underfill material, or partially encapsulating the second solder interconnection array at discrete locations with underfill material.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: March 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Glenn G. Daves, David L. Edwards, Mukta G. Farooq, Frank L. Pompeo
  • Patent number: 7886957
    Abstract: In a method of manufacturing bonding probes, bump layer patterns are formed on terminals of a multi-layered substrate. A first wetting layer pattern having a wettability with respect to a solder paste, and a non-wetting layer pattern having a non-wettability with respect to the solder paste are formed on the bump layer patterns. The solder paste is formed on the first wetting layer and the non-wetting layer pattern. The probes, which make contact with an object, are bonded to the solder paste. The solder paste on the non-wetting layer pattern reflows along a surface of the first wetting layer pattern to form an adhesive layer on the first wetting layer pattern. Thus, a sufficient amount of the solder paste, which is required for bonding the probes, may be provided to firmly bond the probes.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: February 15, 2011
    Assignee: Phicom Corporation
    Inventors: Ki-Joon Kim, Yong-Hwi Jo
  • Patent number: 7878385
    Abstract: Embodiments of invention are directed to the formation of microprobes (i.e. compliant electrical or electronic contact elements) on a temporary substrate, dicing individual probe arrays, and then transferring the arrays to space transformers or other permanent substrates. Some embodiments of the invention transfer probes to permanent substrates prior to separating the probes from a temporary substrate on which the probes were formed while other embodiments do the opposite. Some embodiments, remove sacrificial material prior to transfer while other embodiments remove sacrificial material after transfer. Some embodiments are directed to the bonding of first and second electric components together using one or more solder bumps with enhanced aspect ratios (i.e. height to width ratios) obtained as a result of surrounding the bumps at least in part with rings of a retention material. The retention material may act be a solder mask material.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: February 1, 2011
    Assignee: Microfabrica Inc.
    Inventors: Ananda H. Kumar, Ezekiel J. J. Kruglick, Adam L. Cohen, Kieun Kim, Gang Zhang, Richard T. Chen, Christopher A. Bang, Vacit Arat, Michael S. Lockard, Uri Frodis, Pavel B. Lembrikov, Jeffrey A. Thompson
  • Patent number: 7854365
    Abstract: A method is provided for bonding a die comprising a solder layer which has a melting point Tm. A bond head is heated to a bond head setting temperature T1, which is higher than Tm, and a substrate is heated to a substrate setting temperature T2, which is lower than Tm. The bond head then picks up the die and heats the die towards temperature T1 so as to melt the solder layer. The solder layer of the die is pressed onto the substrate so as to bond the die to the substrate, and thereafter the bond head is separated from the die so that the solder layer is cooled towards T2 and solidifies.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: December 21, 2010
    Assignee: ASM Assembly Automation Ltd
    Inventors: Ming Li, Ying Ding, Ping Liang Tu, King Ming Lo, Kwok Kee Chung
  • Patent number: 7845547
    Abstract: A method for manufacturing a printed wiring board having a bump. The method includes forming a solder-resist layer having a small-diameter aperture and a large-diameter aperture, each aperture exposing a respective conductive pad of the printed wiring board, and printing a solder paste in the large-diameter aperture in the solder-resist layer, but not printing the solder paste in the small-diameter aperture in the solder resist layer. The method also includes loading a solder ball in each of the large-diameter aperture and the small-diameter aperture using a mask having aperture areas that correspond to the small-diameter aperture and large-diameter aperture of the solder-resist layer, and forming a small-diameter bump from the solder ball in the small-diameter aperture and a large-diameter bump from both the solder paste and the solder ball in the large-diameter aperture.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: December 7, 2010
    Assignee: IBIDEN Co., Ltd.
    Inventor: Katsuhiko Tanno
  • Patent number: 7780063
    Abstract: A mask having a plurality of through holes and a mold having a plurality of cavities are provided, and the through holes and the cavities are aligned. Conductive balls are dispensed into the aligned through holes and cavities Substantially one ball is dispensed into each aligned through hole and cavity, and the mask with the holes and the cavities in the mold are configured and dimensioned such that the balls are substantially flush with, or recessed below, an outer surface of the mask. The mask is removed, the conductive balls are aligned with pads of a semiconductor device, and the conductive balls are transferred to the pads by fluxless reflow in a formic acid environment. Vibrational, electrostatic, and direct transfer aspects are also disclosed.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: August 24, 2010
    Assignee: International Business Machines Corporation
    Inventors: Russell A. Budd, Frank R. Libsch, Jae-Woong Nah
  • Patent number: 7740161
    Abstract: An engine wall structure includes an inner wall to which hot gas is admitted during engine operation, an outer wall, which is colder than the inner wall during engine operation, and at least two webs that connect the inner wall with the outer wall and delimit a cooling duct between the walls. The webs are mainly formed by a first material and the inner wall is mainly formed by a second material of other composition and other heat conductivity than the first material.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: June 22, 2010
    Assignee: Volvo Aero Corporation
    Inventor: Arne Boman
  • Patent number: 7731076
    Abstract: A semiconductor device manufacturing apparatus includes a substrate holding section that holds a semiconductor wafer substrate, a discharge mechanism that discharges liquid drops of metal paste from a discharge nozzle toward a surface of the semiconductor wafer substrate, and a driving mechanism that moves at least one of the substrate holding section and the discharge nozzle. A control section is provided to control the discharge and driving mechanisms so as to adhere the metal paste to the surface. The semiconductor wafer substrate includes a terminal unit formed from two or more electrically separated terminals connected to a device circuit and an insulation layer having an opening in a formation position of the terminal unit. Further, the control section controls the discharge and driving mechanisms to selectively coat the opening of the semiconductor wafer substrate with the metal paste overlying the terminal unit to be electrically connected.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: June 8, 2010
    Assignee: Ricoh Company, Ltd.
    Inventor: Kazunari Kimino
  • Publication number: 20090321651
    Abstract: A device includes (a) radiation detector including a semiconductor substrate having opposing front and rear surfaces, a cathode electrode located on the front surface of said semiconductor substrate, and a plurality of anode electrodes on the rear surface of said semiconductor substrate, (b) a printed circuit board, and (c) an electrically conductive polymeric film disposed between circuit board and the anode electrodes. The polymeric film contains electrically conductive wires. The film bonds and electrically connects the printed circuit board and anode electrodes.
    Type: Application
    Filed: April 29, 2008
    Publication date: December 31, 2009
    Inventors: Pinghe LU, Henry Chen, Glenn Bindley
  • Publication number: 20080277456
    Abstract: An assembly including a solder wettable surface is provided. The assembly also includes a metal mask configured to restrict solder from flowing outside the solder wettable surface.
    Type: Application
    Filed: May 9, 2007
    Publication date: November 13, 2008
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: ARUN VIRUPAKSHA GOWDA, KEVIN MATTHEW DUROCHER, JAMES WILSON ROSE, PAUL JEFFREY GILLESPIE, RICHARD ALFRED BEAUPRE, DAVID RICHARD ESLER
  • Patent number: 7445141
    Abstract: A method for assembling, and the resultant electronic module, includes attaching a chip to a substrate using a first solder interconnection array, and attaching a board to the substrate using a second solder interconnection array, which may be a single-melt or a dual-melt solder array. The second solder interconnection array resides entirely within a space defined between the board and substrate. A creep resistant structure is provided within this space for maintaining the defined space and optimizing integrity of the second solder interconnection array. The creep resistant structure may include an underfill material, balls, brackets, frames, collars or combinations thereof. Wherein the creep resistant structure is an underfill material, it is crucial that the substrate be attached to the board before either entirely encapsulating the second interconnection array with underfill material, or partially encapsulating the second solder interconnection array at discrete locations with underfill material.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: November 4, 2008
    Assignee: International Business Machines Corporation
    Inventors: Glenn G. Daves, David L. Edwards, Mukta G. Farooq, Frank L. Pompeo
  • Patent number: 7419084
    Abstract: A method for surface mount solder of a comparatively large component is provided wherein a first intermediate component is soldered to a printed wring board and a larger second component is positioned and soldered to the printed wiring board using the intermediate component. An electrical contact made this way is covered as well as its use in an electrostatographic printer.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: September 2, 2008
    Assignee: Xerox Corporation
    Inventor: Hendrikus A. A. Verheijen
  • Patent number: 7416106
    Abstract: A technique for processing a circuit board involves placing a mask layer on the circuit board, where the mask layer defines a set of pad profiles for a component mounting location. Each pad profile has a set of rounded corners. The technique further involves forming, for each pad profile, a soldering pad having a set of radii corresponding to the set of rounded corners of that pad profile to create a set of soldering pads for the component mounting location. Each soldering pad is configured for a high bond strength solder joint. The technique further involves removing the mask layer from the circuit board and soldering a component to the component mounting location. This technique is well-suited for robustly mounting the component to the circuit board at solder joints with relatively high solder joint bond strengths.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: August 26, 2008
    Assignee: EMC Corporation
    Inventors: Stuart D. Downes, Jin Liang, Larry Norris
  • Patent number: 7258263
    Abstract: A method for making a current collector plate includes providing a first sheet of material having a first bonding face and a first outer face. A second sheet of material is provided having a second bonding face and a second outer face. A work area is defined on at least one of the first bonding face and the second bonding face. The first and second sheets are bonded together at a bonding area which is different from the work area. The bonded first and second sheet is placed into a die having a pattern defining at least one flow channel. Fluid is injected between the first and second sheets thereby causing at least one of the first and second sheets to project outward at the work area causing at least one flow channel to be formed in the work area as defined by the die pattern.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: August 21, 2007
    Assignee: General Motors Corporation
    Inventors: David R Sigler, Yen-Lung Chen, Xiaohong Gayden
  • Patent number: 7252218
    Abstract: An anti-bonding material is placed in a desired pattern onto a first sheet of conductive material. A second sheet of conductive material is roll bonded with the first sheet of material. Fluid is injected between the bonded first and second sheets of material to expand the sheets of material at the desired pattern. A flow channel is formed at the desired pattern between the first and second sheet during fluid injection.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: August 7, 2007
    Assignee: General Motors Corporation
    Inventors: Xiaohong Gayden, Yen-Lung Chen, David R Sigler
  • Patent number: 7124931
    Abstract: The invention provides thermally conductive material so that less heat traveling from one side of a layer will reach connection material on another side of a layer. Rather, some of the heat will be conducted away by the thermally conductive material and dissipated.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: October 24, 2006
    Assignee: Intel Corporation
    Inventors: J. Shelton Lewis, Shawn Lloyd, Michael Kochanowski, John Oldendorf
  • Patent number: 7028881
    Abstract: Method for welding objects having limited backside access to a cavity behind a region to be welded. The method includes inserting a fugitive backing material in an installation state into a first portion of the cavity proximate the region to be welded and then transforming the fugitive backing material to a rigid state. The method further includes forming a weld in the region and then transforming the fugitive backing material to a removable state and removing the fugitive backing material from the cavity. The method may also include placing a pre-formed weld backing in the cavity and filling the cavity with a fugitive backing material. The method further includes transforming the fugitive backing material to a rigid state, forming a weld, and transforming the fugitive backing material to a removable state. The method may further include removing the fugitive backing material and removing the pre-formed weld backing from the cavity.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: April 18, 2006
    Assignee: Siemens Power Generation, Inc.
    Inventors: Peter J. Ditzel, Paul J. Zombo
  • Patent number: 7004376
    Abstract: There is provided a mask for use in printing solder on a plurality of terminals formed on a substrate so as to correspond to a plurality of terminals of an IC package. The mask has openings through which the solder is applied, and the openings are larger than the terminals. Although a wiring line adjacent to the terminals may be covered with the solder, a reflow process causes the solder to be divided into a first portion and a second portion, thus preventing short-circuits between the wiring line and the terminals.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: February 28, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Takeshi Ashida
  • Patent number: 7004375
    Abstract: The present invention relates to a pressure sensitive fluxing underfill composition that may be pre-applied to electronic components, such as CSP's, in order to increase the reliability of the component against mechanical stresses such as impact and bending. The composition contains an epoxy resin, a solid anhydride curing agent, and catalyst. Other materials, such as air release agents and fillers, may also be added as desired. The composition may be applied selectively to parts of the CSP, for example to the solder bumps. The composition provides sufficient tack in order to hold the electronic assembly together during the assembly process.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: February 28, 2006
    Assignee: National Starch and Chemical Investment Holding Corporation
    Inventors: Jayesh Shah, Brian Wheelock, Quinn K. Tong
  • Patent number: 6994243
    Abstract: A solder interconnection uses preferably lead-rich solder balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate. After a solder ball has been formed using standard processes, a thin cap layer of preferably pure tin is deposited on a surface of the solder balls. An interconnecting eutectic alloy is formed upon reflow. Subsequent annealing causes tin to diffuse into the lead, or vice versa, and intermix, thereby raising the melting point temperature of the cap layer of the resulting assembly. This structure and process avoids secondary reflow problems during subsequent processing.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: February 7, 2006
    Assignee: International Business Machines Corporation
    Inventors: Joseph M. Milewski, Charles G. Woychik
  • Patent number: 6966482
    Abstract: Lands formed on a flexible printed circuit board are electrically connected with lands formed on a rigid printed circuit board through solder. At this point, solder resist is formed between neighboring two lands on the rigid printed circuit board, and is terminated with an end portion that is interposed between the rigid printed circuit board and the flexible printed circuit board. Accordingly, even when surplus solder is extruded onto the rigid printed circuit board, the solder resist can prevent solder bridges from being formed between the lands.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: November 22, 2005
    Assignee: Denso Corporation
    Inventors: Makoto Totani, Toshihiro Miyake, Tomohiro Yokochi, Takehito Teramae, Yoshitaro Yazaki, Kazuyuki Deguchi, Hajime Nakagawa
  • Patent number: 6935553
    Abstract: A soldering method includes exposing a solder paste including a solder powder and a flux on a member to a free radical gas and heating the solder paste to reflow the solder paste and vaporize any active components in the solder paste. Any flux residue is free of active components, so it is not necessary to perform cleaning after soldering to remove flux residue.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: August 30, 2005
    Assignees: Senju Metal Industry Co., Ltd., Shinko Seiki Co., Ltd.
    Inventors: Tadatomo Suga, Keisuke Saito, Yoshikazu Matsuura, Tatsuya Takeuchi, Johji Kagami, Rikiya Kato, Sakie Yamagata
  • Patent number: 6926190
    Abstract: A method for assembling chips onto substrates includes applying a flux-free, no-flow underfill material. In an embodiment, the method includes removing oxide from interconnects without the use of a flux and applying a flux-free, no-flow underfill. In an embodiment, the method includes removing oxide from bumps, applying no-flow underfill to a substrate, and fluxlessly connecting the bumps to pads on the substrate. In an embodiment, oxide is removed from the bumps by a plasma treatment. In an embodiment, oxide is removed from the bumps by a subjecting the bumps to an oxide reduction process. The assembly of the chips and substrate is free from flux residue and/or flux cleaning solution residue.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: August 9, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Tongbi Jiang, Tsuyoshi Yamashita
  • Patent number: 6910615
    Abstract: In a solder reflow type building of modular electrical apparatus involving integrated circuit and discrete components, fabrication operations are arranged to include the providing of a general type series of steps for each component element involving a reflow or joining step at the highest joining temperature, immediately followed by a solder flux cleaning step and immediately followed by a testing of the entire module constructed thus far. There is provided a further specific type operation for each different type of component element that includes the providing of a loop for the introduction of a replacement for any broken discrete component with joining being achieved with use of a lower fusion temperature solder, flux cleaning and testing at each joining followed by reinsertion into the module. There is further provided an operation at the encapsulation stage of the module building for introducing underfill between the component and supporting carrier.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: June 28, 2005
    Assignee: International Business Machines Corporation
    Inventors: Peter A. Gruber, Minkailu A Jalloh, Chon Cheong Lei
  • Patent number: 6902098
    Abstract: A device including a first solder pad and a second solder pad comprised of a post-soldering alloy composition on a substrate is provided. The alloy composition comprises two or more elements, and the post soldering alloy composition of the first solder pad has different amounts of the two or more elements than the alloy composition of the second solder pad. A method of making a solder pad comprises masking a substrate comprising at least a first solder pad and a second solder pad, wherein the mask exposes a greater area of the first solder pad so that the deposited element becomes part of an alloy composition of the first solder pad upon soldering thereby changing the melting point of the first solder pad.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: June 7, 2005
    Assignee: Shipley Company, L.L.C.
    Inventor: Mindaugas F. Dautartas
  • Patent number: 6896173
    Abstract: The present invention provides a method of fabricating a circuit substrate. First, a substrate having first pads and second pads is provided, wherein the first pads and second pads are arranged respectively on a first surface and a second surface of the substrate. The first pads are electrically connected to the second pads. Next, a conductive seed layer is formed on the second surface of the circuit substrate. Thereafter, a first conductive layer and a second conductive layer are electroplated respectively over the first pads and the second pads. Afterwards, the conductive seed layer is patterned.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: May 24, 2005
    Assignee: VIA Technologies, Inc.
    Inventors: Kwun-Yao Ho, Moriss Kung
  • Patent number: 6871775
    Abstract: A barrier metal layer is provided on at least one of two electrodes, with one formed on a substrate and the other connected to an electronic component, so as to coat a base material of the electrode, which base material is made of a material containing Cu. Soldering between the electrode of the electronic component and the electrode on the substrate is conducted by supplying a solder material containing Sn and Bi, contacting the solder material with the barrier metal layer while the solder material is in a molten state; and solidifying the solder material. Thereby, when the electronic component is soldered to the substrate with the solder material such as an Sn—Bi based material or an Sb—Ag based material containing Bi, the degradation of a soldering part is avoided, and thus a sufficient thermal fatigue strength of the soldering part is obtained.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: March 29, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Atsushi Yamaguchi, Masato Hirano