Abstract: The present invention is a method and an apparatus for optical modulation, for example for use in optical communications links. In one embodiment, an apparatus for optical modulation includes a first silicon layer having one or more trenches formed therein, a dielectric layer lining the first silicon layer, and a second silicon layer disposed on the dielectric layer and filling the trenches.

Abstract: The present invention relates to integration of lateral high-voltage devices, such as a lateral high-voltage diode (LHVD) or a lateral high-voltage thyristor, with other circuitry on a semiconductor wafer, which may be fabricated using low-voltage foundry technology, such as a low-voltage complementary metal oxide semiconductor (LV-CMOS) process. The other circuitry may include low-voltage devices, such as switching transistors used in logic circuits, computer circuitry, or the like, or other high-voltage devices, such as a microelectromechanical system (MEMS) switch. The reverse breakdown voltage capability of the LHVD may be increased by using an intrinsic material between the anode and the cathode. Similarly, in a lateral high-voltage thyristor, such as a lateral high-voltage Silicon-controlled rectifier (LHV-SCR), the withstand voltage capability of the LHV-SCR may be increased by using an intrinsic material between the anode and the cathode.

Abstract: A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer thereon. The TVS device further includes a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate wherein the drain region interfaces with the body region constituting a junction diode and the drain region encompassed in the body region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode.

Abstract: A multi-terminal electrically actuated switch comprises a source electrode, a drain electrode, and an active region physically connected to both electrodes. The active region comprises at least one primary active region comprising at least one material that can be doped or undoped to change its electrical conductivity, and a secondary active region comprising at least one material for providing a source/sink of ionic species that act as dopants for the primary active region(s). A gate electrode is physically connected to the source/sink region. Methods of operating the switch are also provided.

Abstract: The present invention has provided a new diode and transistor by employing the characteristic of the tunnel diode. The new diode and transistor are field interacted and can be a solarcell, light sensor, thermal device, Hall device, pressure device or acoustic device which outputs self-excited multi-band waveforms with broad bandwidth. The present invention has also revealed a precisional switch which can works at high speeds and a capacitor whose capacitance can be actively controlled.

Abstract: In one embodiment, a mandrel and an outer dummy spacer may be employed to form a first conductivity type region. The mandrel is removed to form a recessed region wherein a second conductivity type region is formed. In another embodiment, a mandrel is removed from within shallow trench isolation to form a recessed region, in which an inner dummy spacer is formed. A first conductivity type region and a second conductivity region are formed within the remainder of the recessed region. An anneal is performed so that the first conductivity type region and the second conductivity type region abut each other by diffusion. A gate electrode is formed in self-alignment to the p-n junction between the first and second conductivity regions. The p-n junction controlled by the gate electrode, which may be sublithographic, constitutes an inventive tunneling effect transistor.

Abstract: In one embodiment, a mandrel and an outer dummy spacer may be employed to form a first conductivity type region. The mandrel is removed to form a recessed region wherein a second conductivity type region is formed. In another embodiment, a mandrel is removed from within shallow trench isolation to form a recessed region, in which an inner dummy spacer is formed. A first conductivity type region and a second conductivity region are formed within the remainder of the recessed region. An anneal is performed so that the first conductivity type region and the second conductivity type region abut each other by diffusion. A gate electrode is formed in self-alignment to the p-n junction between the first and second conductivity regions. The p-n junction controlled by the gate electrode, which may be sublithographic, constitutes an inventive tunneling effect transistor.

Abstract: An epitaxial silicon carbide layer is fabricated by forming first features in a surface of a silicon carbide substrate having an off-axis orientation toward a crystallographic direction. The first features include at least one sidewall that is orientated nonparallel (i.e., oblique or perpendicular) to the crystallographic direction. A first epitaxial silicon carbide layer is then grown on the surface of the silicon carbide substrate that includes first features therein. Second features are then formed in the first epitaxial layer. The second features include at least one sidewall that is oriented nonparallel to the crystallographic direction. A second epitaxial silicon carbide layer is then grown on the surface of the first epitaxial silicon carbide layer that includes the second features therein.

Abstract: An epitaxial silicon carbide layer is fabricated by forming first features in a surface of a silicon carbide substrate having an off-axis orientation toward a crystallographic direction. The first features include at least one sidewall that is orientated nonparallel (i.e., oblique or perpendicular) to the crystallographic direction. A first epitaxial silicon carbide layer is then grown on the surface of the silicon carbide substrate that includes first features therein. Second features are then formed in the first epitaxial layer. The second features include at least one sidewall that is oriented nonparallel to the crystallographic direction. A second epitaxial silicon carbide layer is then grown on the surface of the first epitaxial silicon carbide layer that includes the second features therein.

Abstract: Hermetically sealed high-voltage assemblies are made up of series-connected diodes. Exposed tabs bonding adjacent diodes allow for greater thermal dissipation than previous products. This allows higher current-carrying capacity especially if used in oil.

Abstract: A cascaded diode structure with a deep N-well for effectively reducing the leakage current of the P-type substrate by floating the base of a parasitic transistor in the cascaded diode structure. The cascaded diode structure includes a P-type substrate, a deep N-well formed on the P-type substrate, a plurality of elemental diodes formed on the deep N-well, and a plurality of connecting parts for cascading the elemental diodes. Each elemental diode includes a P-well formed on the deep N-well, a heavily doped P-type region formed on the P-well, and a heavily doped N-type region formed on the P-well.

Abstract: A semiconductor device of this invention is a single-layer gate nonvolatile semiconductor memory in which a floating gate having a predetermined shape is formed on a semiconductor substrate. This floating gate opposes a diffusion layer serving as a control gate via a gate oxide film and is capacitively coupled with the diffusion layer by using the gate oxide film as a dielectric film. The diffusion layer immediately below the dielectric film is insulated from the semiconductor substrate by an insulating film such as a silicon oxide film. A pair of diffusion layers are formed in surface regions of the semiconductor substrate on the two sides of the floating gate extending on a tunnel oxide film.

Abstract: The present invention provides a high voltage semiconductor device capable of withstanding excessive breakdown and clamping voltages. The device includes a high resistivity substrate, and an epitaxially grown, low resistivity layer having a stress-relieving dopant. During production, the low conductivity region has one surface that is etched before a high conductivity region is diffused into it or epitaxially deposited on it.

Abstract: A method for producing laterally varying multiple diodes and their device embodiment are presented herein. As demonstrated, multiple resonant tunneling diodes are fabricated together utilizing a single epitaxial structure. Shallow, ion-implanted regions having varying depths, dx, define the collector contacts. Each diode is isolated electrically from the others by methods such as conventional mesa etching into the emitter layer. The varying depths, dx, provide means for varying the peak voltage of each individual diode. The peak voltage strongly depends on the depths, dx, because it comprises a space charge region where the electric field is high, and therefore the voltage drop is high. The invention disclosed herein is useful in applications such as high-speed circuits such as comparators, analog to digital converters, sample and hold circuits, logic devices, and frequency multipliers.

Abstract: A gate oxide film formed on the surface of a silicon substrate is partly reduced in thickness or “thinned” at its specified part overlying a source region. In a gate region, a multilayer structure is formed which includes a first polycrystalline silicon or “polysilicon” film of a p-type conductivity, a tunnel oxide film, and a second p-type polysilicon film in this order of lamination. The source region and the first polysilicon film make up a high-concentration impurity-doped pn junction with a thin silicon oxide film laid therebetween, providing a tunnel diode also known as Esaki diode. The diode is used for a negative differential resistance. Further, a portion between the first and second polysilicon films is a non-linear tunnel resistor, which serves as a load.

Abstract: A silicon-based light-emitting device is described and comprises an active region, an excitation system which can bring about a condition of inversion of the population of carriers within the active region, and semi-reflective elements which can define a resonant optical structure in which the active region is inserted so as to bring about stimulated emission of coherent light. The active region comprises silicon nanostructures immersed in a silicon-dioxide-based dielectric matrix.

Abstract: A method of fabricating a diode device, such as a PIN diode, includes forming top and bottom regions of opposite conductivity types and includes anisotropically etching into the top surface to form a pit having side walls that converge with approach to the bottom surface. However, the pit does not extend to the bottom surface. In the PIN diode embodiment, the pit terminates within an intrinsic region that separates a bottom surface diffusion region from a diffusion region along the walls of the anisotropically etched pit. The anisotropic etching approach provides a degree of self regulation with regard to the geometries of the pit. A process flow of steps is described, which allows thicker and larger diameter wafers to be used in the formation of an array of such diode device.

Abstract: A semiconductor device of this invention is a single-layer gate nonvolatile semiconductor memory in which a floating gate having a predetermined shape is formed on a semiconductor substrate. This floating gate opposes a diffusion layer serving as a control gate via a gate oxide film and is capacitively coupled with the diffusion layer by using the gate oxide film as a dielectric film. The diffusion layer immediately below the dielectric film is insulated from the semiconductor substrate by an insulating film such as a silicon oxide film. A pair of diffusion layers are formed in surface regions of the semiconductor substrate on the two sides of the floating gate extending on a tunnel oxide film.

Abstract: A semiconductor component includes a semiconductor layer (210) and at least one diode (220) in the semiconductor layer. The semiconductor component also includes an electrically insulative layer (230) over the semiconductor layer and the diode. The semiconductor component further includes at least one more diode (240, 250, 280, 290, 440, 450) over the electrically insulative layer, the semiconductor layer, and the diode in the semiconductor layer.

Abstract: A method of epitaxially growing backward diodes as well as apparatus grown by the method are presented herein. More specifically, the invention utilizes epitaxial-growth techniques such as molecular beam epitaxy in order to produce a thin, highly doped layer at the p-n junction in order to steepen the voltage drop at the junction, and thereby increase the electric field. By tailoring the p and n doping levels as well as adjusting the thin, highly doped layer, backward diodes may be consistently produced and may be tailored in a relatively easy and controllable fashion for a variety of applications. The use of the thin, highly doped layer provided by the present invention is discussed particularly in the context of InGaAs backward diode structures, but may be tailored to many diode types.

Abstract: A semiconductor device includes a plurality of diodes including a substrate of a first conductivity type biased to a reference potential, a well region of a second conductivity type formed in a surface region of the substrate, and a first diffusion region of the first conductivity type formed in a surface region of the well region, wherein the plurality of diodes have sizes of at least two kinds and are cascade-connected to each other.

Abstract: A pin diode includes an inner zone, a cathode zone and an anode zone. A boundary surface between the inner zone and the anode zone is at least partly curved and/or at least one floating region having the same conduction type and a higher dopant concentration than in the inner zone is provided in the inner zone. The turnoff performance in such geometrically coupled power diodes, in contrast to the turnoff performance of pin power diodes (in the Read-diode version) with spaced charge coupling, is largely temperature-independent. Hybrid diodes with optimized conducting-state and turnoff performance can be made from such FCI diodes. FCI diodes are preferably used in conjunction with switching power semiconductor elements, as voltage limiters or free running diodes.

Abstract: An inventive semiconductor memory device includes a memory circuit and a logic circuit that are formed on a single semiconductor substrate. The memory circuit includes a storage element having a memory gate structure. The memory gate structure includes: a tunnel insulating film formed on the substrate; and a control gate electrode formed out of a gate prototype film. The logic circuit includes a logical element having a logic gate structure. The logic gate structure includes: a lower gate electrode formed out of the gate prototype film; and an upper gate electrode formed out of a conductor film on the lower gate electrode. The conductor film contains a metal. The memory gate structure includes no metal films.

Abstract: The present invention provides a compact structure for the above-discussed SRAM cell as well as a method for fabricating the structure. The structure is preferably implemented in silicon. The standby power consumption of the cell is only approximately 0.5 nanowatts. The cell structure allows an SRAM cell to be fabricated in only a 16 feature-square area using planar technology. The structure of the cell according to one embodiment of the present invention is comprised of two bus bars of minimum feature size width, each of which has a tunnel diode implanted therein, and an elongated center land area (also of minimum feature size width) between the two bus bars. The transistor is constructed along the elongated center land area. In a preferred embodiment, transistors of neighboring cells share a common drain area and bit line contact. A corresponding method for fabricating the structure is also provided.

Abstract: A gate oxide film formed on the surface of a silicon substrate is partly reduced in thickness or “thinned” at its specified part overlying a source region. In a gate region, a multilayer structure is formed which includes a first polycrystalline silicon or “polysilicon” film of a p-type conductivity, a tunnel oxide film, and a second p-type polysilicon film in this order of lamination. The source region and the first polysilicon film make up a high-concentration impurity-doped pn junction with a thin silicon oxide film laid therebetween, providing a tunnel diode also known as Esaki diode. The diode is used for a negative differential resistance. Further, a portion between the first and second polysilicon films is a non-linear tunnel resistor, which serves as a load.

Abstract: A semiconductor light emitting device, such as the light emitting diode (LED) or the laser diode (LD), having a structure in which a light emitting area is a double heterostructure or a multi-layer quantum well structure. The light emitting area is formed on a substrate. Subsequently, an electrically conductive oxide layer as a transparent window layer to eliminate the crowding effect is formed on the light emitting area. The substrate layer consists of a GaAs substrate and a GaAsP layer to increasing the band gap energy of the substrate. The electrically conductive oxide layer is formed of AlZnO(x) material, having a lower electrical resistivity and a high transparency in the visible wavelength region. The window layer is formed using a physical vapor deposition or a metalorganic chemical vapor deposition.

Abstract: A GaAs-InGaP triangular-barrier optoelectronic switch (TBOS) is disclosed, wherein two i-InGaP layers are formed on both sides of the p.sup.+ -GaAs layer in the conventional triangular-barrier structure. By introducing avalanche multiplication and carrier confinement into the device operation, S-shaped negative-differential-resistance (NDR) performances are observed in the I-V (current-voltage) characteristic curves under normal and reverse operation modes. Moreover, the TBOS of the present invention shows a flexible optical function because the barrier height is associated with incident light. Owing to the incident light changing the potential barrier height for the electrons thermionically emitted over it, the I-V characteristics of the TBOS are optically controllable.

Abstract: A liquid crystal display panel includes a counter substrate having a counter electrode and a multi-layered dielectric film both formed thereon, and an array substrate formed with pixel electrodes and thin-film transistors serving as switching elements. A layer of polymer dispersed liquid crystal material containing a UV-curable resin component and a liquid crystal component is sandwiched and sealed between the counter and array substrates. A light shielding film is formed over each thin-film transistor. The multi-layered dielectric film is a laminated structure of alternating thin-films of SiO.sub.2 and HfO.sub.2. Since the multi-layered dielectric film is of a nature capable of transmitting UV-rays of light therethrough, the UV-curable resin component positioned underneath the multi-layered dielectric film can be cured during the manufacture.

Abstract: A functional semiconductor element, which is designed to perform an ultrafast amplifying, bistable, similar functional operation by initiating and stopping an avalanche multiplication in one of i-type layers of what is called a triangular barrier diode (TBD) structure having an n-i-p-i-n, p-i-n-i-p, n-i-p-i-p, n-i-n-i-p, n-i-n-i-n, p-i-n-i-n, p-i-p-i-p, or p-i-p-i-n configuration. By forming a light absorbing layer and a light emitting layer or light modulating layer in this structure, it is possible to function the element as an optical functional element. Furthermore, the addition of a resonant tunneling diode implements a novel function.

Abstract: A semiconductor device includes a semiconductor substrate having an element region on the main surface thereof, an element isolation region formed to surround the element region on the main surface of the semiconductor substrate, a gate electrode formed over the element region with a gate insulating film disposed therebetween, a first and a second impurity diffusion region formed on a surface of the element region on both sides of at least part of the gate electrode, a first channel region formed in the surface of the element region below the gate electrode between the first and the second impurity diffusion region when a first preset voltage is applied to the gate electrode, and a first tunnel diode formed in a first interface region between the first impurity diffusion region and the first channel region when the first preset voltage is applied to the gate electrode, wherein the first interface region in which the first tunnel diode is formed is formed in position separated from the element isolation region

Abstract: A semiconductor memory has bit lines, word lines, ground lines, and memory cells. The bit lines intersect the word and ground lines, to form intersections where the memory cells are arranged, respectively. Each of the memory cells consists of a double-emitter transistor. This transistor has a collector, a first emitter, and a second emitter. Each base-emitter junction of the transistor has an N-shaped negative differential current-voltage characteristic that shows a relatively small gain up to a peak current and a relatively large gain after a valley current. The first emitter of each transistor is connected to a corresponding one of the ground lines. The second emitter is connected to a corresponding one of the word lines. The collector is connected to a corresponding one of the bit lines. Each of the memory cells has a small number of elements and requires only a small area.

Abstract: A double electron layer tunneling device is presented. Electrons tunnel from a two dimensional emitter layer to a two dimensional tunneling layer and continue traveling to a collector at a lower voltage. The emitter layer is interrupted by an isolation etch, a depletion gate, or an ion implant to prevent electrons from traveling from the source along the emitter to the drain. The collector is similarly interrupted by a backgate, an isolation etch, or an ion implant. When the device is used as a transistor, a control gate is added to control the allowed energy states of the emitter layer. The tunnel gate may be recessed to change the operating range of the device and allow for integrated complementary devices. Methods of forming the device are also set forth, utilizing epoxy-bond and stop etch (EBASE), pre-growth implantation of the backgate or post-growth implantation.

Abstract: The tunnel transistor of the present invention has either a junction structure wherein a degenerated first semiconductor having one conduction type, a non-degenerated second semiconductor and a degenerated third semiconductor having the reverse conduction type to that of the first semiconductor are connected on a substrate or a laminated layer structure comprising a degenerated first semiconductor having one conduction type, a non-degenerated second semiconductor and a degenerated third semiconductor of the reverse conduction type to that of the first semiconductor all laminated on a part of a substrate. The tunnel transistor further includes a fourth semiconductor layer formed on an exposed surface of the second semiconductor, having a forbidden band wider than that of the second semiconductor and containing an ionized impurity therein, a gate electrode formed on the fourth semiconductor layer, and a pair of electrodes individually forming ohmic junctions to the first and third semiconductors.

Abstract: Disclosed is a three terminal tunnel device exhibiting a tunneling of carriers in a forward direction. The device comprises an intrinsic semiconductor region, an n-type degenerate semiconductor source region abutting one side of the intrinsic semiconductor region, a p-type degenerate semiconductor drain region abutting an opposite side of the intrinsic semiconductor region, an insulation region separating the three semiconductor regions from a semiconductor substrate, and a gate electrode being provided over the intrinsic semiconductor region through an insulation layer, whereby voltage signals to be applied to the gate electrode permit controlling a carrier concentration at a surface of the intrinsic semiconductor region. The device permits controlling a tunneling current of a forward-biased degenerate p-n junction and a current-voltage characteristic manifesting a negative differential resistance with the gate voltage signals.

Abstract: A tunnel transistor comprises a semiconductor film (27) between a gate isolating film (17) and parts of first (13) and second (15) semiconductor layers which are formed in a substrate (11) to serve as source and drain regions with a spacer region left therebetween and covered with the semiconductor film. The gate isolating film is over the part of the first semiconductor layer and is made of either an insulating material or a semiconductor material, each of which materials should have a wider forbidden bandwidth than a semiconductor material of the semiconductor film, such as silicon dioxide, silicon nitride, or aluminium nitride, or gallium phosphide for silicon, or AlGaAs fox gallium arsenide. A source electrode is formed on an uncovered area of the first semiconductor layer. The semiconductor film forms a tunnel junction with the first semiconductor layer and an ohmic junction with the second semiconductor layer, which junction may be either a homojunction or a heterojunction.

Abstract: A new static memory cell based on the bistable operation of a three-terminal four layer semiconductor device working in the forward blocking state is disclosed. The power consumption of the memory cell is low. The switching speed of the memory cell is in the nanosecond range. The memory cell may be integrated into VLSI processes and is of a size suitable for VLSI applications. The memory cell comprises a semiconductor device which comprises: an n-type semiconductor cathode region; a p-type semiconductor gate region; a third semiconductor region adjacent the gate region; a fourth region adjacent the third semiconductor region; and a hole-injecting boundary between the third semiconductor region and the fourth region. The semiconductor device is preferably a p-n-p-n device. The gate current-voltage characteristics of the device comprise a negative resistance region. The device is designed to operate in a forward blocking low current state.

Abstract: A semiconductor device having a voltage sensing element is disclosed which allows reduction of power consumption in comparison with a conventional device and enables to obtain a sufficient output voltage to secure sensing accuracy even when an input voltage is small. In the voltage sensing element of the semiconductor device, an n.sup.- layer is formed on a front surface of a p.sup.- substrate. A p type diffused region and an n type diffused region are formed at a main surface of n.sup.- layer, spaced apart by a prescribed distance. An electrode is formed on p type diffused region, and an electrode is formed on n type diffused region. An electrode is formed on a rear surface of p.sup.- substrate. P.sup.- substrate and n.sup.- layer constitute a diode in a reversely biased state. As a result, power consumption is reduced in comparison with a conventional voltage dividing resistor circuit.

Abstract: A semiconductor devive comprises;a collector region of first conductivity type;a base region of second conductivity type;an emitter region of the first conductivity type;a thin film provided on the emitter region and capable of flowing therein a tunnel current; anda polycrystalline layer laminated on the thin film.An energy .DELTA..phi..sub.B of potential barrier formed at a grain boundary is not less than a heat energy kT at a temperature therein.

Abstract: An interband single-electron tunnel/transistor utilizes an interband single-electron tunneling phenomenon between a valence band and a conduction band through a p-n junction. The transistor includes the combination of microcapacities as fundamental constituent elements each formed by joining a p-type semiconductor material doped with an impurity in the degree of concentration with which a Fermi level overlaps a valence band and an n-type semiconductor material doped with an impurity in the degree of concentration with which the Fermi level overlaps a conduction band. The microcapacity includes a p-n junction having a junction area with which interband electron tunneling is inhibited due to Coulomb blockade.

Abstract: A new static memory cell based on the bistable operation of a three-terminal four layer semiconductor device working in the forward blocking state is disclosed. The power consumption of the memory cell is low. The switching speed of the memory cell is in the nanosecond range. The memory cell may be integrated into VLSI processes and is of a size suitable for VLSI applications. The memory cell comprises a semiconductor device which comprises: an n-type semiconductor cathode region; a p-type semiconductor gate region; a third semiconductor region adjacent the gate region; a fourth region adjacent the third semiconductor region; and a hole-injecting boundary between the third semiconductor region and the fourth region. The semiconductor device is preferably a p-n-p-n device. The gate current-voltage characteristics of the device comprise a negative resistance region. The device is designed to operate in a forward blocking low current state.

Abstract: A semiconductor device consisting of epitaxial material is provided with at least one monoatomic layer of doping atoms, i.e. with a layer which is just one atom thick. A preferred device is a bipolar transistor in which case the Dirac-delta doped p-type layer 38 is directly between n-type collector and emitter layers (32, 33). The bipolar transistor described herein has an extremely low base width and is capable of operating at high frequencies.

Abstract: A semiconductor device of band-to-band tunneling type including a silicon substrate, a first gate electrode formed by a highly doped surface region of the silicon substrate, a first silicon oxide film formed on a surface of the surface region, a silicon thin film formed on the first silicon oxide film, a second silicon oxide film formed on a surface of the thin silicon film, and a second gate electrode formed by a metal film applied on a surface of the second silicon oxide film. In the thin silicon film, there are formed P and N type regions side by side to constitute a PN junction. When a gate bias voltage is applied across the first and second gate electrodes, a band bend having a large height and inclination in a direction perpendicular to the thin silicon film is produced in the depletion region in the vicinity of the PN junction.

Abstract: An interband single-electron tunnel transistor utilizes an interband single-electron tunneling phenomenon between a valence band and a conduction band through a p-n junction. The transistor includes the combination of microcapacities as fundamental constituent elements each formed by joining a p-type semiconductor material doped with an impurity in the degree of concentration with which a Fermi level overlaps a valence band and an n-type semiconductor material doped with an impurity in the degree of concentration with which the Fermi level overlaps a conduction band. The microcapacity includes a p-n junction having a junction area with which interband electron tunneling is inhibited due to Coulomb blockade.