Abstract: Stacked integrated circuit devices may include standard cells including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each of the standard cells may include an upper transistor and a lower transistor. The upper transistor may include an upper active region, an upper gate structure, and an upper source/drain region. The lower transistor may include a lower active region, a lower gate structure, and a lower source/drain region. Each of the standard cells may also include a power line and a power via electrically connecting the power line to the lower source/drain region. The power via of the first standard cell and the power via of the second standard cell may be aligned with each other along the first direction.

Abstract: Examples described herein generally relate to forming and/or configuring a die stack in a multi-chip device. An example is a method of forming a multi-chip device. Dies are formed. At least two or more of the dies are interchangeable. Characteristics of the at least two or more of the dies that are interchangeable are determined. A die stack comprising the at least two or more of the dies that are interchangeable is formed. Respective placements within the die stack of the at least two or more of the dies that are interchangeable are based on the characteristics.

Abstract: A bidirectional switch is formed in a semiconductor substrate of a first conductivity type. The switch includes first and second thyristors connected in antiparallel extending vertically between front and rear surfaces of the substrate. A vertical peripheral wall of the second conductivity type connects the front surface to the rear surface and surrounds the thyristors. On the front surface, in a ring-shaped region of the substrate separating the vertical peripheral wall from the thyristors, a first region of the first conductivity type is provided having a doping level greater than the substrate and having the shape of a ring-shaped band portion partially surrounding the first thyristor and stopping at the level of the adjacent region between the first and second thyristors.

Abstract: A microelectronic assembly includes a first unit and a second unit overlying the first unit. Each of the units include a dielectric element that includes first and second apertures, first and second microelectronic elements, first leads extending from contacts of the first microelectronic element through the first aperture, and second leads extending from contacts of the second microelectronic element through the second aperture. The microelectronic assembly further includes a heat spreader that is thermally coupled to at least one of the first microelectronic element or the second microelectronic element of the first unit. The heat spreader may be a monolithic structure having apertures substantially aligned with the contacts of the first and second microelectronic elements of the first unit.

Abstract: A method for packaging an integrated circuit (IC) device in which conventional manufacturing steps of mechanically bonding a die to a corresponding interconnecting substrate, wire bonding the die, and encapsulating the die in a protective shell are replaced by a single manufacturing step that includes thermally treating an appropriate assembly of parts to both form proper electrical connections for the die in the resulting IC package and cause the molding compound(s) to encapsulate the die in a protective enclosure.

Abstract: Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: [ ? i = 1 n ? ( R Mi × k Mi ) - ? i = 1 n ? ( R Si × k Si ) ] / ? i = 1 n ? ( R Mi × k Mi ) where a temperature-dependent resistance changing rate of an i-th semiconductor layer (i=1 to n) of the main element domain is RMi; a resistance ratio of the i-th semiconductor layer of the main element domain relative to the entire main element domain is kMi; a temperature-dependent resistance changing rate of the i-th semiconductor layer of the sense element domain is RSi; and a resistance ratio of the i-th semiconductor layer of the sense element domain to the entire sense element domain is kSi.

Abstract: The ESD protection circuit is electrically connected between a first power rail and a second power rail, and includes an ESD protection device, a switching device electrically connected between the ESD protection device and a first power rail, and a low-pass filter electrically connected between the first power rail and the first switching device. The ESD protection device includes a BJT and a first resistor electrically connected between a base of the BJT and a first power rail. When no ESD event occurs, a potential of the base is larger than or equal to a potential of an emitter of the BJT. When the ESD event occurs, the potential of the base is smaller than the potential of the emitter.

Abstract: A modified MOSFET structure comprises an integrated field effect rectifier connected between the source and drain of the MOSFET to shunt current during switching of the MOSFET. The integrated FER provides faster switching of the MOSFET due to the absence of injected carriers during switching while also decreasing the level of EMI relative to discrete solutions. The integrated structure of the MOSFET and FER can be fabricated using N-, multi-epitaxial and supertrench technologies, including 0.25 ?m technology. Self-aligned processing can be used.

Abstract: A semiconductor light-emitting element includes: a substrate; and a nitride semiconductor multilayer film provided on an upper surface of the substrate and including an active layer. A recess, a stepped portion, or a protruding portion is formed in an active layer or a layer that contacts a lower surface of the active layer. A ridge stripe, which has a front end facet and a rear end facet and serves as an optical waveguide, is formed in an upper part of the nitride semiconductor multilayer film. The distance from a lateral center of the ridge stripe to a lateral center of the recess, the stepped portion, or the protruding portion changes continuously or in stages from the front end facet toward the rear end facet. Bandgap energy of the active layer changes continuously or in stages from the front end facet toward the rear end facet.

Abstract: A rectifier building block has four electrodes: source, drain, gate and probe. The main current flows between the source and drain electrodes. The gate voltage controls the conductivity of a narrow channel under a MOS gate and can switch the RBB between OFF and ON states. Used in pairs, the RBB can be configured as a three terminal half-bridge rectifier which exhibits better than ideal diode performance, similar to synchronous rectifiers but without the need for control circuits. N-type and P-type pairs can be configured as a full bridge rectifier. Other combinations are possible to create a variety of devices.

Abstract: Method and apparatus for an integrated circuit having memory including thyristor-based memory cells is described. A pair of the thyristor-based memory cells are commonly coupled via a bitline region, where a parasitic bipolar junction transistor is defined therebetween responsive to the bitline region being common. In another implementation, the pair of the thyristor-based memory cells are commonly coupled via the anode region, where a parasitic bipolar junction transistor is defined therebetween responsive to the anode region being common. The common bitline or anode region, respectively, has a locally thinned region to inhibit charge transfer between the pair via the parasitic bipolar junction transistor. Moreover, a method for forming a field-effect transistor on a silicon-on-insulator wafer is described, where charge transfer facilitated by a parasitic bipolar transistor is reduced responsive to an increase in dopants at least proximate to an insulator layer.

Abstract: An Adjustable Field Effect Rectifier uses aspects of MOSFET structure together with an adjustment pocket or region to result in a device that functions reliably and efficiently at high voltages without significant negative resistance, while also permitting fast recovery and operation at high frequency without large electromagnetic interference.

Abstract: The present invention is directed to novel front side illuminated, back side contact photodiodes and arrays thereof. In one embodiment, the photodiode has a substrate with at least a first and a second side and a plurality of electrical contacts physically confined to the second side. The electrical contacts are in electrical communication with the first side through a doped region of a first type and a doped region of a second type, each of the regions substantially extending from the first side through to the second side. In another embodiment, the photodiode comprises a wafer with at least a first and a second side; and a plurality of electrical contacts physically confined to the second side, where the electrical contacts are in electrical communication with the first side through a diffusion of a p+ region through the wafer and a diffusion of an n+ region through the wafer.

Abstract: A nitrided region is formed on a surface of a polysilicon layer by a nitriding treatment wherein plasma of a processing gas is generated by introducing microwaves into a processing chamber by a planar antenna having a plurality of slots. Then, a CVD oxide film or the like is formed on the nitrided region and after patterning the polysilicon layer and the like after the prescribed shape, and then, a thermal oxide film is formed by thermal oxidation on exposed side walls and the like of the polysilicon layer by having the nitrided region as an oxidation barrier layer. Thus, generation of bird's beak can be suppressed in the process at a temperature lower than the temperature in a conventional process.

Abstract: A partition-wall structure having a concave portion corresponding to a pattern formed by a functional liquid, including: a first concave portion provided corresponding to a first pattern; a second concave portion provided corresponding to a second pattern that is coupled to the first pattern and whose width is smaller than a width of the first pattern; and a convex portion provided in the first pattern.

Abstract: A chip embedded package structure and a fabrication method thereof are proposed. An adhesive layer is formed on a bottom surface of a carrier board having at least one cavity to seal one end of the cavity. At least one semiconductor chip is mounted via its non-active surface on the adhesive layer and received in the cavity. A protection layer is formed on an active surface of the semiconductor chip. A conductive layer is formed on a top surface of the carrier board, the protection layer and the cavity. A patterned resist layer is applied on the conductive layer and is formed with an electroplating opening at a position corresponding to a gap between the cavity and the semiconductor chip. An electroplating process is performed to form a metal layer in the electroplating opening, such that the semiconductor chip can be effectively fixed in the cavity by the metal layer.

Abstract: The present invention provides a photoresist stripper including about 5 wt % to about 20 wt % alcohol amine, about 40 wt % to about 70 wt % glycol ether, about 20 wt % to about 40 wt % N-methyl pyrrolidone, and about 0.2 wt % to about 6 wt % chelating agent.

Abstract: A method for making an integrated circuit includes forming spaced-apart trenches on a surface of a single crystal silicon substrate, lining the trenches with a silicon oxide layer, forming a first polysilicon layer over the silicon oxide layer, forming a second polysilicon layer over the first polysilicon layer, and removing a thickness of the single crystal silicon substrate to expose tubs of single crystal silicon in the second polysilicon layer.

Abstract: A semiconductor multi-package module having stacked first and second packages, each package including a die attached to a substrate, in which the first and second substrates are interconnected by wire bonding, and wherein at least one said package comprises a stacked die package. Also, a method for making a semiconductor multi-package module, by providing a stacked die molded first package including a first package substrate, affixing a second molded package including a second substrate onto an upper surface of the first package, and forming z-interconnects between the first and second substrates.

Abstract: A method of forming a LDMOS semiconductor device and structure for same. A preferred embodiment comprises forming a first guard ring around and proximate the drain of a LDMOS device, and forming a second guard ring around the first guard ring. The first guard ring comprises a P+ base guard ring, and the second guard ring comprises an N+ collector guard ring formed in a deep N-well, in one embodiment. The first guard ring and second guard ring prevent leakage current from flowing from the drain of the LDMOS device to the substrate.

Abstract: A pnpn thyristor element Thy1 and six pn diode elements D1, D2, D3, D4, D5, and D6 are formed in a semiconductor substrate of a first conductivity type, and separated into six regions by a diffusion layer of a second conductivity type which also functions as the anode of the thyristor element Thy1. A double isolation diffusion layer is disposed between the region of the thyristor element Thy1 and three pn diode elements D1 ·D2 and D6, and the region of the three remaining pn diodes D3, D4, and D5. Surface connection is performed to provide a balance type surge protection circuit.

Abstract: A thyristor-based semiconductor device exhibits a relatively increased base-emitter capacitance. According to an example embodiment of the present invention, a base region and an adjacent emitter region of a thyristor are doped such that the emitter region has a lightly-doped portion having a light dopant concentration, relative to the base region. In one embodiment, the thyristor is implemented in a memory circuit, wherein the emitter region is coupled to a reference voltage line and a control port is arranged for capacitively coupling to the thyristor for controlling current flow therein. In another implementation, the thyristor is formed on a buried insulator layer of a silicon-on-insulator (SOI) structure. With these approaches, current flow in the thyristor, e.g., for data storage therein, can be tightly controlled.

Abstract: Systems and methods for encapsulating a stack of semiconductor dice are described. A stack of semiconductor dice may be formed, for example by attaching die to flexible printed circuit supports attached to frames and stacking the supports, and then encapsulated by flowing a liquid encapsulant around the stack of dice and solidifying the liquid encapsulant. The die supports may contain encapsulant flow openings, such as rectangular slits, that allow the liquid encapsulant to flow around the stack of dice.

Abstract: Methods for making a semiconductor assembly and, specifically, interconnecting a semiconductor die to a carrier substrate. The carrier substrate includes a first surface and a second surface with at least one opening therethrough. The die includes an active surface and a back surface, wherein the die is attached facedown to the first surface of the carrier substrate with conductive bumps therebetween. In addition, a plurality of bond wires is attached through the at least one opening in the carrier substrate between the active surface of the die and the second surface of the carrier substrate. With this arrangement, both the conductive bumps and the bond wires share in the electrical interconnection between the die and the carrier substrate, thereby allowing more space for bond pads to interconnect with bond wires and/or allowing for smaller die sizes.

Abstract: A vertical voltage-controlled bidirectional monolithic switch formed between the upper and lower surfaces of a semiconductor substrate surrounded with a peripheral wall, including: a first multiple-cell vertical IGBT transistor extending between a cathode formed on the upper surface side and an anode formed on the lower surface side; and a second multiple-cell vertical IGBT transistor extending between a cathode formed on the lower surface side and an anode formed on the upper surface side, in which the cells of each transistor are arranged so that portions of the cells of a transistor are active upon operation of the other transistor.

Abstract: An electrostatic discharge protection circuit, comprising a semiconductor-controlled rectifier and a PMOS device. The semiconductor-controlled rectifier, coupled between two nodes, has an N-type semiconductor layer. The PMOS device, integrated with the semiconductor-controlled rectifier to share a first P-type doped region, has a PNP device located in the N-type semiconductor layer. When one of the nodes is coupled to the electrostatic discharge power, the PNP device will conduct to trigger the semiconductor-controlled rectifier.

Abstract: A vehicle wheel lift includes a base, a substantially upright member, a linear actuator, and a lift arm. The linear actuator is coupled to the upright member, which is attached to and extends from the base. The lift arm is pivotally coupled to the upright member proximate a first end of the lift arm and above the linear actuator. The lift arm includes a wheel cradle shaped for receiving a vehicle wheel proximate a second end of the lift arm that is opposite the first end of the lift arm and is connected to a ram of the linear actuator between the first and second ends of the lift arm.

Abstract: A semiconductor rectifier includes a substrate of a first conductivity type; a current path layer of the first conductivity type formed near the surface of the substrate; a current block layer of a second conductivity type laterally enclosing the current path layer and extending to a depth deeper than the current path layer; and first and second metal layers formed respectively contacting upper and lower surfaces of the substrate. The current path layer has an impurity concentration higher than that of the substrate, and the current block layer has an impurity concentration higher than that of the current path layer. The current path layer is small enough for the portion below the current path layer to be completely blocked by the depletion region formed around the current block layer when a reverse bias or no is applied to the rectifier.

Abstract: The present invention relates to an isolating wall for separating elementary components formed in different wells, a component located in at least one of the wells being capable of operating with a high current density. The isolating wall exhibits in its median portion a concentration of carriers higher than 1016 atoms/cm3. Preferably, the width of the openings from which the dopant diffusions are formed in the upper and lower surfaces of the substrate is higher than 1.3 times the half-thickness of the substrate.

Abstract: An improved bond pad structure for semiconductor devices provides improved electrical isolation between adjacent bond pads by incorporating a pair of pn junctions between the pad and substrate. The pn junctions are defined by a first well of either P of N type material, formed within a substrate, and a second well or region of a P or N type material formed wholly within the first well. A bond wire is secured to an upper surface of the second region such that the wire, first and second regions and substrate are connected in electrical series relationship and provide an equivalent circuit of two series connected diodes reversed in polarity so as to block both negative and positive components of an applied voltage, thus providing electrical isolation for the bond pad structure.

Abstract: An electrostatic discharge protective circuit of the invention includes a silicon controller rectifier (SCR) and a current diverter. The current diverter is used to bypass an initial low current thereby to prevent the SCR from being triggered by the low current. Thus, a trigger current required to activate the SCR can be greatly increased thereby to maintain an internal circuit at a normal operating state.

Abstract: An electrostatic discharge protection device for protecting a mixed voltage integrated circuit against damage is provided which includes at least on pair of NMOS transistors connected in a cascode configuration. Each NMOS transistor pair includes a first transistor, having a drain region coupled to and I/O stage of the mixed voltage integrated circuit, and a gate region coupled to the mixed voltage integrated circuit's low power supply. The second NMOS transistor of the pair is merged into the same active area as the first transistor and has a gate region and a source region coupled to the ground plane of the mixed voltage integrated circuit. The source region of the first transistor and the drain region of the second transistor are constructed of a shared NMOS diffusion region.

Abstract: A specification is given of a bidirectionally controllable thyristor which is distinguished by improved decoupling between the two thyristor structures. In particular, the intention is that the switched-off structure cannot be triggered in an uncontrolled manner by undesirable migration of charge carriers. This is achieved by virtue of the fact that the degree of shorting of the cathode region increases toward the isolation region. In particular, this can be achieved by virtue of the fact that the density per unit area of the short-circuit regions tends to a maximum value toward the isolation region. The use of a linear, continuous short-circuit region running along the isolation region is particularly favorable. (FIG. 1).

Abstract: A monolithic component for protection against over-currents liable to occur on a line in series with which is connected a detection resistor, comprises a first cathode-gate thyristor associated with an avalanche diode and a second anode-gate thyristor of the gate triggering type or forward breakover type, its breakover voltage being substantially equal to the avalanche voltage of the avalanche diode.

Abstract: A circuit for protecting a bonding pad of a semiconductor device from ESD voltages is located under the pad to permit the space otherwise used for a protection circuit to be used for normal operating components. The protection circuit has a compact layout that provides maximum ability to handle an ESD current within this limited space. The semiconductor structure for the circuit has separate parts for two SCR circuits, one for each polarity of ESD current. Each SCR circuit comprises two symmetrical SCR structures.

Abstract: A reverse conducting gate-turnoff thyristor includes a switching device section, a diode section, and an isolating section located between the switching device section and the diode section. The isolating section includes an impurity layer formed by controlling impurity diffusion and having an impurity concentration lower than those of the switching device section and the diode section.

Abstract: An a.c. switch includes across first and second main terminals a first thyristor disposed in parallel with, but in an opposite direction of, a first diode and in series with a second thyristor disposed in parallel with but in an opposite direction of, a second diode. The first thyristor has a gate terminal connected to its gate area. The second thyristor and second diode are vertically realized in the same substrate, their conduction areas being closely interlaced, whereby a polarity inversion following a conduction period of the second diode causes the second thyristor to become conductive.

Abstract: An a.c. switch includes across first and second main terminals a first thyristor disposed in parallel with, but in an opposite direction of, a first diode and in series with a second thyristor disposed in parallel with but in an opposite direction of, a second diode. The first thyristor has a gate terminal connected to its gate area. The second thyristor and second diode are vertically realized in the same substrate, their conduction areas being closely interlaced, whereby a polarity inversion following a conduction period of the second diode causes the second thyristor to become conductive.

Abstract: An a.c. switch includes across first and second main terminals a first thyristor disposed in parallel with, but in an opposite direction of, a first diode and in series with a second thyristor disposed in parallel with, but in an opposite direction of, a second diode. The first thyristor has a gate terminal connected to its gate area. The second thyristor and second diode are vertically realized in the same substrate, their conduction areas being closely interlaced, whereby a polarity inversion following a conduction period of the second diode causes the second thyristor to become conductive.

Abstract: In a bidirectional semiconductor switch which can be switched on and off, printed conductors which form the main term terminals (1, 2) and the control terminals (3, 4) are applied to a baseplate (9). Applied to the printed conductors, which form the main terminals (1, 2), are at least two reverse-blocking semiconductor components (5a-h) which can be switched on and off. The control electrodes (8a, 8e) and the second main electrodes (7a, 7e) of the semiconductor components (5a-h) are interconnected in such a way that the semiconductor switch has the required bidirectional switching function.