Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes multiple chip regions and a strip line for separating the chip regions. A test key is formed in the strip line and is used for a bit line contact (BLC) resistance test. The test key includes active regions and connecting structures. The active regions are formed in the semiconductor substrate. The connecting structures are located at ends of the active regions. The multiple active regions located on the same column are sequentially connected end to end by the connecting structures.

Abstract: A highly integrated semiconductor device is provided. The semiconductor device includes a substrate, a prism-like insulator, a memory cell string including a plurality of transistors connected in series. The prism-like insulator is provided over the substrate. The memory cell string is provided on the side surface of the prism-like insulator. The plurality of transistors each include a gate insulator and a gate electrode. The gate insulator includes a first insulator, a second insulator, and a charge accumulation layer. The charge accumulation layer is positioned between the first insulator and the second insulator.

Abstract: An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.

Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.

Abstract: A semiconductor device includes a target layer disposed on a substrate, and a crack sensor for detecting a crack generated in the target layer. The crack sensor includes a first conductive pattern positioned at a bottom surface of the target layer, a second conductive pattern positioned on a top surface of the target layer, the top surface being opposite to the bottom surface of the target layer, a plurality of resistors, and nodes. The plurality of resistors are connected in parallel to each other through the first conductive pattern and the second conductive pattern. Each of the plurality of resistors is disposed to substantially penetrate the target layer.

Abstract: An apparatus includes a protection circuit electrically connected to first and second voltage domains. The protection circuit includes a first silicon-controlled rectifier (SCR) and a second SCR connected in anti-parallel configuration. The first SCR is configured to connect the first voltage domain and the second voltage domain based on detection of a first triggering condition. The second SCR is configured to connect the second voltage domain and the first voltage domain based on detection of a second triggering condition. The protection circuit is configured to isolate the first and second voltage domains without the triggering conditions.

Abstract: A TVS circuit having a first diode with a cathode coupled to a first terminal and an anode coupled to a first node. A second diode has an anode coupled to a second node and a cathode coupled to a third node. A third diode is coupled between the first node and second node. A fourth diode is coupled between the first node and third node. A fifth diode is coupled between the second node and a second terminal. A sixth diode is coupled between the second terminal and the third node. A seventh diode can be coupled between the second terminal and an intermediate node between the fifth diode and sixth diode. The first diode is disposed on a first semiconductor die, while the second diode is disposed on a second semiconductor die. Alternatively, the first diode and second diode are disposed on a single semiconductor die.

Abstract: An IC structure includes a first cell and a first and second rail. The first cell includes a first and second active region and a first, a second and a third gate structure. The first active region having a first dopant type. The second active region having a second dopant type. The first gate structure extending in a second direction, overlapping the first or the second active region. The second gate structure extending in the second direction, and overlapping a first edge of the first or second active region. The third gate structure extending in the second direction, and overlapping at least a second edge of the first or second active region. The first rail extending in the first direction and overlapping a middle portion of the first active region. The second rail extending in the first direction and overlapping a middle portion of the second active region.

Abstract: An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.

Abstract: A fabrication method for a semiconductor device includes measuring a thickness of a semiconductor substrate in which a bulk donor of a first conductivity type is entirely distributed, adjusting an implantation condition in accordance with the thickness of the semiconductor substrate and implanting hydrogen ions from a lower surface of the semiconductor substrate to an upper surface side of the semiconductor substrate, and annealing the semiconductor substrate and forming, in a passage region through which the hydrogen ions have passed, a first high concentration region of the first conductivity type in which a donor concentration is higher than a doping concentration of the bulk donor.

Abstract: A gate-turn-off thyristor is provided. The gate-turn-off thyristor includes a plurality of strips formed by repeatedly arranging a plurality of N-type emitter regions with high doping concentration of an upper transistor on an upper surface of an N-type silicon substrate with high resistivity, wherein a periphery of each strip of the plurality of strips is surrounded with a P-type dense base region bus bar of the upper transistor, a cathode metal layer is disposed on an N-type emitter region of the plurality of N-type emitter regions of the upper transistor, and a P-type base region of the upper transistor is disposed below the N-type emitter region of the upper transistor; a side of the P-type base region of the upper transistor is connected to a P-type dense base region of the upper transistor or a P-type dense base region bus bar of the upper transistor.

Abstract: A semiconductor device includes: a semiconductor base substrate including a semiconductor layer; a first main electrode; a second main electrode; a plurality of peripheral trenches formed on a surface of the semiconductor layer and having bottom portions covered by the semiconductor layer in a peripheral region; and a plurality of in-trench electrodes each embedded in each of the plurality of peripheral trenches byway of an insulation layer formed on an inner surface of the each peripheral trench, wherein the semiconductor base substrate further includes, in the peripheral region, a plurality of second conductive type floating regions disposed in the semiconductor layer at a depth position deeper than the bottom portions of the peripheral trenches in a spaced apart manner from the peripheral trenches and having a potential in a floating state.

Abstract: A semiconductor device includes: a housing; a substrate inside the housing; first and second semiconductor circuits on the substrate; and first and second planar terminals electrically connected to the first and second semiconductor circuits, respectively, the first and second planar terminals stacked on top of each other, wherein each of the first and second planar terminals extends away from the housing.

Abstract: Structures that include a distributed Bragg reflector and methods of fabricating a structure that includes a distributed Bragg reflector. The structure includes a substrate, an optical component, and a distributed Bragg reflector positioned between the optical component and the substrate. The distributed Bragg reflector includes airgaps and silicon layers that alternate in a vertical direction with the airgaps to define a plurality of periods.

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JEFT also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

Abstract: The present disclosure relates to a bidirectional semiconductor circuit breaker including a primary circuit unit connected between a power supply and a load and in which a first semiconductor switch and a second semiconductor switch are arranged in series and a snubber circuit unit of which one end is connected to the front end of the first semiconductor switch and the other end is connected to the rear end of the second semiconductor switch, in parallel. The snubber circuit unit includes a first circuit line, a second circuit line, and a third circuit line of which one end and the other end are connected to the first circuit line and the second circuit line, respectively, and in which a first resistor and a second resistor are arranged in series, and provide a snubber circuit which is applicable to a bidirectional fault current and satisfies semiconductor protection and current restraining performance.

Abstract: A floating base silicon controlled rectifier is provided, which at least comprises a first conductivity type layer; a second conductivity type well formed in the first conductivity type layer; a first conductivity type heavily doped region coupled to a first node and formed in the second conductivity type well; and a second conductivity type heavily doped region coupled to a second node and formed in the first conductivity type layer. The first conductivity type and the second conductivity type are opposite. When the first conductivity type is N type, the second conductivity type is P type. Alternatively, when the first conductivity type is P type, the second conductivity type is N type. By employing the proposed present invention, the floating base silicon controlled rectifier acts as a forward diode, and an input capacitance can be greatly reduced.

Abstract: An apparatus includes a protection circuit electrically connected to first and second voltage domains. The protection circuit includes a first silicon-controlled rectifier (SCR) and a second SCR connected in anti-parallel configuration. The first SCR is configured to connect the first voltage domain and the second voltage domain based on detection of a first triggering condition. The second SCR is configured to connect the second voltage domain and the first voltage domain based on detection of a second triggering condition. The protection circuit is configured to isolate the first and second voltage domains without the triggering conditions.

Abstract: Integrated circuit architectures for load and input matching that include a capacitance selectable between a plurality of discrete levels, which are associated with a number of field effect transistors (FET) capacitor structures that are in an on-state. The capacitance comprises a metal-oxide-semiconductor (MOS) capacitance associated with each of the FET capacitor structures, and may be selectable through application of a bias voltage applied between a first circuit node and a second circuit node. Gate electrodes of the FET capacitor structures may be coupled in electrical parallel to the first circuit node, while source/drains of the FET capacitor structures are coupled in electrical parallel to the second circuit node. Where the FET capacitor structures have different gate-source threshold voltages, the number of FET capacitor structures in the on-state may be varied according to the bias voltage, and the capacitance correspondingly tuned to a desired value.

Abstract: A semiconductor device includes first and second electrodes, a semiconductor part therebetween and first to third control electrodes between the first electrode and the semiconductor part. The semiconductor part includes first and third layers of a first-conductivity-type and second and fourth layers of a second-conductivity-type. The second, third and fourth layers are provided between the first layer and the first electrode, between the second layer and the first electrode, and between the first layer and the second electrode, respectively. To the first to third control electrodes, first to third voltages greater than the threshold voltage thereof are applied at first to third timings, respectively. The third, second and first voltages are reduced to a lower level than the threshold voltage at a fourth timing after the first to third timings, at a fifth timing after the fourth timing and at a sixth timing after the fifth timing, respectively.

Abstract: In one embodiment, an overvoltage protection device (100) may include a crowbar device (106), where the crowbar device (106) includes a first crowbar terminal (115), the first crowbar terminal (115) connected with a first external voltage line (102). The overvoltage protection device (100) may further include a transient voltage suppression (TVS) device (108), where the TVS device (108) includes a second TVS terminal (121), the second TVS terminal (121) connected with a second external voltage line (104). The crowbar device (106) and the TVS device (108) may be arranged in electrical series between the first crowbar terminal (115) and the second TVS terminal (121).

Abstract: The present disclosure introduces, among other things, an electronic device, e.g. an integrated circuit (IC). The IC includes a semiconductor substrate comprising a first doped layer of a first conductivity type. A second doped layer of the first conductivity type is located within the first doped layer. The second doped layer has first and second layer portions with a greater dopant concentration than the first doped layer, with the first layer portion being spaced apart from the second layer portion laterally with respect to a surface of the substrate. The IC further includes a lightly doped portion of the first doped layer, the lightly doped portion being located between the first and second layer portions. A dielectric isolation structure is located between the first and second layer portions, and directly contacts the lightly doped portion.

Abstract: A diode semiconductor structure is described. In one example, a diode device includes a substrate, a layer of first semiconductor material of a first doping type, a layer of intrinsic semiconductor material, and a layer of second semiconductor material of a second doping type. The diode device also includes a metal contact formed on the layer of first semiconductor material and a metal via formed from a backside of the substrate, through the substrate, and through the layer of first semiconductor material, where the metal via contacts a bottom surface of the metal contact on the layer of first semiconductor material. In this configuration, a direct electrical connection can be achieved between the backside of the substrate and the metal contact on the layer of first semiconductor material without the need for an additional metal connection, such as a metal air bridge, to the metal contact.

Abstract: According to an embodiment of the present invention, a method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a second barrier layer on the first barrier layer; forming a first hard mask on the second barrier layer; removing the first hard mask and the second barrier layer to form a recess; and forming a p-type semiconductor layer in the recess.

Abstract: In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.

Abstract: A semiconductor integrated circuit includes: a semiconductor base body of a first conductivity type; a first well region of a second conductivity type, deposited at an upper portion of the semiconductor base body, to which a first potential is applied; a second well region of the first conductivity type, deposited at an upper portion of the first well region, to which a second potential lower than the first potential is applied; a main electrode region to which the second potential is applied, the main electrode region being deposited at the upper portion of the first well region and away from the second well region; a first buried layer of the second conductivity type buried locally under the second well region; and a second buried layer of the second conductivity type buried locally under the main electrode region and away from the first buried layer.

Abstract: A vertical isolated gate FET transistor integrated in the front end of line of a semiconductor chip is disclosed. In one aspect, the transistor includes a modified version of a buried power rail and back side TSV (through semiconductor via) connection for connecting the front end of line to a back side signal delivery network, such as a power delivery network (PDN), the PDN being arranged on the backside of the semiconductor substrate that carries the active devices of the FEOL on its front side. In contrast to standard power rail/TSV combinations, the TSV is not electrically connected to the rail, but isolated therefrom by a dielectric plug at the bottom of the rail. The TSV is isolated from the semiconductor substrate by a dielectric liner. Well regions are furthermore provided on the front side, enveloping the rail and the dielectric plug, and on the backside, surrounding the TSV and liner. On the back side, the well includes a contact area adjacent the TSV.

Abstract: A semiconductor device having a P type substrate, an N type layer on the P type substrate that forms a PN junction therewith and the P type region, N type region and P type substrate form at least one parasitic PNP transistor.

Abstract: A floating base silicon controlled rectifier is provided, which at least comprises a first conductivity type layer; a second conductivity type well formed in the first conductivity type layer; a first conductivity type heavily doped region coupled to a first node and formed in the second conductivity type well; and a second conductivity type heavily doped region coupled to a second node and formed in the first conductivity type layer. The first conductivity type and the second conductivity type are opposite. When the first conductivity type is N type, the second conductivity type is P type. Alternatively, when the first conductivity type is P type, the second conductivity type is N type. By employing the proposed present invention, the floating base silicon controlled rectifier acts as a forward diode, and an input capacitance can be greatly reduced.

Abstract: Apparatuses and methods to provide a fully self-aligned via are described. Some embodiments of the disclosure utilize a cap layer to protect an insulating layer in order to minimize bowing of the side walls during metal recess in a fully self-aligned via. The cap layer can be selectively removed, thus increasing the aspect ratio, by exposing the substrate to a hot phosphoric acid solution.

Abstract: An improved DC circuit breaker is provided for automatically detecting and isolating a fault between a source and a ground. The DC circuit breaker comprises at least one switch, in electrical series with a first inductor between the source and a load, and a second inductor magnetically coupled to the first inductor wherein a first side of the second inductor is electrically connected to the load and a second side of the second inductor is grounded through a capacitor.

Abstract: An integrated circuit (IC) chip having circuitry adapted to detect and unlatch a latched transistor, and methods for operating the same are provided. In one example, an IC chip includes a body, a power rail disposed in the body and coupled to at least one of a plurality of contact pads disposed on the body, and a first core circuit disposed in the body. The first core circuit includes a first current limiting circuit, a silicon controlled rectifier (SCR) device having a first transistor, a second transistor, and a first latch sensing circuit. The first current limiting circuit is coupled to the power rail. First terminals of the first and second transistors are coupled to the first current limiting circuit. The first latch sensing circuit has a first input terminal coupled to second terminals of the first and second transistors. The first latch sensing circuit also has an output terminal coupled to the first current limiting circuit.

Abstract: The present disclosure discloses a feedback field-effect electronic device using a feedback loop operation and an array circuit using the feedback field-effect electronic device. According to one embodiment of the present disclosure, the array circuit includes a plurality of feedback field-effect electronic devices in which the source region of a diode structure and the drain region of an access electronic device are connected in series, wherein the diode structure is connected to a bit line and a first word line, the access electronic device is connected to a source line and a second word line, and a random access operation is performed by selectively applying voltage to the bit line and the first and second word lines.

Abstract: A semiconductor device includes: a substrate; a drift region formed on a main surface of the substrate; a well region formed in a main surface of the drift region; a source region formed in the well region; a gate groove formed from the main surface of the drift region in a perpendicular direction while being in contact with the source region, the well region, and the drift region; a drain region formed in the main surface of the drift region; a gate electrode formed on a surface of the gate groove with a gate insulating film interposed therebetween; a protection region formed on a surface of the gate insulating film facing the drain region; and a connection region formed in contact with the well region and the protection region.

Abstract: Provided are a neuromorphic device and a neuromorphic circuit using the neuromorphic device. The neuromorphic device is configured to include a first semiconductor region formed on a substrate in a wall shape or a dumbbell shape; first, second, third, and fourth doped regions sequentially formed in the first semiconductor region; first and second gate insulating film stacks disposed on the respective side surfaces of the second doped region; first and second gate electrodes respectively disposed on the respective side surfaces of the second doped region; the first and second gate electrodes disposed on the respective side surface of the second doped region, the first and second gate electrodes being electrically insulated from the second doped, region by the first and second gate insulating film stacks; and first and second electrodes electrically connected to the first and fourth doped regions, respectively.

Abstract: A modular electronics package is disclosed that includes a first and second electronics packages, with each of the first and second electronics packages including a metallized insulating substrate and a solid-state switching device positioned on the metallized insulating substrate, the solid-state switching device comprising a plurality of contact pads electrically coupled to the first conductor layer of the metallized insulating substrate. A conductive joining material is positioned between the first electronics package and the second electronics package to electrically connect them together. The first electronics package and the second electronics package are stacked with one another to form a half-bridge unit cell, with the half-bridge unit cell having a current path through the solid-state switching device in the first electronics package and a close coupled return current path through the solid-state switching device in the second electronics package in opposite flow directions.

Abstract: Trenches each have longer sides extending in a longitudinal direction, and shorter sides linking the longer sides together. The trenches are periodically arranged in the longitudinal direction and a transverse direction. A first region is on a drift layer of a first conductivity type, has a second conductivity type, and is penetrated by the trenches. A second region is on the first region so as to be away from the drift layer, has the first conductivity type, and is in contact with the longer sides of each of the trenches so as to be away from the ends of the longer sides. A third region is on the first region, has the second conductivity type, and has a higher impurity concentration than the first region. The gate electrode is in the trench with a gate insulating film interposed therebetween.

Abstract: A level shifter includes a signal generator that generates differential signals on a first output and a second output. A first capacitor is coupled between the first output and a first node and a second capacitor is coupled between the second output and a second node. A third capacitor is coupled between the first node and a first voltage potential, wherein the capacitance of the third capacitor is variable. A fourth capacitor is coupled between the second node and the first voltage potential, wherein the capacitance of the fourth capacitor is variable.

Abstract: A semiconductor die and a process for fabricating the semiconductor die are disclosed. The semiconductor die has a substrate and a silicon carbide (SiC) epitaxial structure on the substrate. The SiC epitaxial structure includes at least a first N-type SiC layer, at least a first P-type SiC layer, and carbon vacancy reduction material, which has been implanted into a surface of the SiC epitaxial structure. Further, the SiC epitaxial structure has been annealed to mobilize the carbon vacancy reduction material to diffuse carbon atoms substantially throughout the SiC epitaxial structure, thereby increasing an average carrier lifetime in the SiC epitaxial structure.

Abstract: A semiconductor device includes a thyristor disposed in a semiconductor body. The thyristor has an anode, a cathode, a first bipolar transistor located on an anode side, and a second bipolar transistor located on a cathode side. The first and second bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is disposed in the semiconductor body. The MOS transistor is coupled between a collector region and an emitter region of the second bipolar transistor. The MOS transistor has a gate region connected to the cathode via a resistive semiconductor region that incorporates at least a part of a base region of the second bipolar transistor.

Abstract: In some embodiments, an apparatus comprises a semiconductor layer doped with a first-type dopant, a first region doped with the first-type dopant, a second region doped with the first-type dopant, and a third region doped with a second-type dopant, where the second-type dopant is opposite the first-type dopant. The first, second, and third regions are non-overlapping and are formed in the semiconductor layer. The third region is positioned between the first region and the second region. The apparatus also comprises a plurality of Zener implant regions buried in the semiconductor layer and the third region, where each of the plurality of Zener implant regions is configured to generate a different pinch-off region.

Abstract: A semiconductor die and a process for fabricating the semiconductor die are disclosed. The semiconductor die has a substrate and a silicon carbide (SiC) epitaxial structure on the substrate. The SiC epitaxial structure includes at least a first N-type SiC layer, at least a first P-type SiC layer, and carbon vacancy reduction material, which has been implanted into a surface of the SiC epitaxial structure. Further, the SiC epitaxial structure has been annealed to mobilize the carbon vacancy reduction material to diffuse carbon atoms substantially throughout the SiC epitaxial structure, thereby increasing an average carrier lifetime in the SiC epitaxial structure.

Abstract: An electrostatic protection device of an LDMOS silicon controlled structure comprises a P-type substrate (310), an N-well (320) and a P-well (330) on the substrate, a gate electrode (340) overlapping on the P-well (330) and extending to an edge of the N-well (320), a first N+ structure and a first P+ structure provided in the N-well (320), and a second N+ structure and a second P+ structure provided in the P-well (330), the first N+ structure being a drain electrode N+ structure (322), the first N+ structure being a drain electrode N+ structure (322), the first P+ structure being a drain electrode P+ structure (324), the second N+ structure being a source electrode N+ structure (332), the second P+ structure being a source P+ structure (334), and a distance from the drain electrode P+ structure (324) to the gate electrode (340) being greater than a distance from the drain electrode N+ structure (322) to the gate electrode (340).

Abstract: Double sided versions of several power transistor types are devices that are already known in the literature. Devices built in this configuration are generally required to have a separate driver circuit to control the front and rear control electrodes and provide the gate or base voltage and/or currents for the power switch. This is because there may be of the order of 1000V potential-difference between the frontside and rearside potentials when the transistor is in the off condition—and a single integrated circuit cannot generally sustain this within a single package. The NPN configuration is preferred in this case to benefit from electron conduction for the main power path between the emitters. However, problems arising when using a P-type wafer. The present invention seeks to avoid the use of P-type wafers while still getting the higher conduction performance of NPN operation.

Abstract: In some embodiments, an apparatus comprises a semiconductor layer doped with a first-type dopant, a first region doped with the first-type dopant, a second region doped with the first-type dopant, and a third region doped with a second-type dopant, where the second-type dopant is opposite the first-type dopant. The first, second, and third regions are non-overlapping and are formed in the semiconductor layer. The third region is positioned between the first region and the second region. The apparatus also comprises a plurality of Zener implant regions buried in the semiconductor layer and the third region, where each of the plurality of Zener implant regions is configured to generate a different pinch-off region.

Abstract: A semiconductor device includes: a printed substrate having a through hole from an upper face to a lower face thereof; a first semiconductor element mounted on the printed substrate; an interposer mounted on the upper face of the printed substrate; a second semiconductor element adjacent to the interposer and arranged to overlap with the through hole; and a bonding wire coupling a first pad to a second pad, the first pad being on an upper face of the interposer and being positioned on the second semiconductor element side, the second pad being on an upper face of the second semiconductor element and being positioned on the interposer side, wherein the interposer has an edge face protruding with respect to a wall face of the through hole of the printed substrate toward the second semiconductor element, and the edge face faces with an edge face of the second semiconductor element.

Abstract: A semiconductor device includes a silicon carbide semiconductor substrate, a first silicon carbide layer of a first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of the second conductivity type, a gate insulating film, a gate electrode, an interlayer insulating film, a source electrode, and a drain electrode. The third semiconductor region is thicker than the second semiconductor region and a width of a side of the third semiconductor region facing the first semiconductor region is narrower than a width of a side thereof facing the source electrode.

Abstract: A nonvolatile resistive switching memory includes an inert metal electrode, a resistive switching functional layer, and an easily oxidizable metal electrode. A graphene intercalation layer with nanopores, interposed between the easily oxidizable metal electrode and the resistive switching functional layer, is capable of controlling the metal ions, which are formed by the oxidation of the easily oxidizable metal electrode during the programming of the device, and only enter into the resistive switching functional layer through the position of the nanopores. Further, the graphene intercalation layer with nanopores is capable of blocking the diffusion of the metal ions, making the metal ions, which are formed after the oxidation of the easily oxidizable metal electrode, enter into the resistive switching functional layer only through the position of the nanopores during the programming of the device, thereby controlling the growing position of conductive filament.

Abstract: In a power semiconductor device, an IGBT has a collector electrode bonded to a metal plate by a bonding material. A diode has a cathode electrode bonded to the metal plate by the bonding material. An interconnection member is bonded to an emitter electrode of the IGBT by a bonding material. The bonding material includes a bonding material and a bonding material. The bonding material is interposed between the IGBT and the interconnection member. The bonding material fills a through hole formed in the interconnection member. The bonding material reaches the bonding material and is therefore connected to the bonding material.