Abstract: In a composite controlled semiconductor device having an insulated gate, a p type semiconductor region forming no channel is provided between a plurality of p type semiconductor regions forming a channel and the potential of the p type semiconductor region in an ON state takes a value high enough to inject holes into an n type semiconductor region adjacent to the p type semiconductor region.

Abstract: A shorted anode lateral insulated gate bipolar transistor includes a semiconductor layer of a first conductivity type, a first current electrode, a second current electrode, a first insulation layer, a first gate electrode, a second gate electrode, a first high concentration impurity region of a second conductivity type, a low concentration impurity region of the second conductivity type, a first high concentration impurity region of the first conductivity type, a second high concentration impurity region of the second conductivity type, a third high concentration impurity region of the second conductivity type, and a second high concentration impurity region of the first conductivity type.

Abstract: A semiconductor device made of a lightly doped region of a first conductivity type has a well formed of a second conductivity type. The well extends to the surface of the device. First, second and third heavily doped regions of the first conductivity type are in the surface of the well. An electrode is fixed to the first heavily doped region of the first conductivity type. The third heavily doped region of the first conductivity type adjoins the lightly doped region of the first conductivity type. The first and second heavily doped regions of the first conductivity type are spaced apart from one another so that a portion of the well extends to the surface of the device therebetween. A first gate electrode is fixed via an insulating layer to a portion of the well extending between the first and second heavily doped regions. The first and third heavily doped regions of the first conductivity type are spaced apart from one another so that a portion of the well extends therebetween.

Abstract: A sub-gate electrode is arranged to face, through a gate insulating film, a surface of a first p-type base layer which is interposed between a first n-type source layer and an n-type drift layer, and a surface of a second p-type base layer which is interposed between a second n-type source layer and the n-type drift layer and faces the first p-type base layer. A main gate electrode is arranged to face, through a gate insulating film, a surface of the second p-type base layer which is interposed between the second n-type source layer and the n-type drift layer and does not face the first p-type base layer. Three n-type MOSFETs are constructed such that one n-type channel is to be formed in the first p-type base layer and two n-type channels are to be formed in the second p-type base layer. The three channels are to be formed, so that the channel width is effectively enlarged and the current density is increased. The second p-type base layer has a length of 10 .mu.m or less in the drifting direction.

Abstract: The invention concerns a field-effect controlled semiconductor component with at least four regions of alternating opposite performance types: an anode-side emitter region, a first and a second base region connected to the emitter region, and a cathode-side emitter region; the cathode-side emitter region and the first base region from the source and drain of an MOS field effect transistor. The component also comprises an anode contact, a contact at the cathode-side emitter region and a control electrode contact of the MOS field effect transistor. The invention lies in the fact that a p+ region (36) which is adjacent to the cathode-side base region, separate, and accomodated in the anode-side n- base region (20), is connected via a separate component as a coupling element (80) with non-linear current/voltage characteristics to the cathode contact, the said region (36) being directly surrounded by the anode-side base region (20).

Abstract: A Semiconductor-On-Insulator (SOI) device includes a semiconductor substrate, a buried insulating layer on the substrate, and a lateral MOSFET on the buried insulating layer. The MOSFET includes a semiconductor surface layer on the buried insulating layer and has a source region of a first conductivity type, a channel region of a second conductivity type opposite to that of the first, an insulated gate electrode over the channel region and insulated therefrom, a lateral drift region of the second conductivity type, and a drain region of the first conductivity type laterally spaced apart from the channel region by the drift region. A semiconductor linkup region of the first conductivity type is provided between the channel region and the drift region and extends substantially through the semiconductor surface layer, and the source region of the device is electrically coupled to the drift region.

Abstract: An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.

Abstract: An input/output structure includes a microelectronic device connected in circuit between a contact pad and a reference potential, and a thyristor device for protecting the microelectronic device from electrostatic discharge. The thyristor device includes first and second terminals connected to the contact pad and to the reference potential respectively, a PNPN thyristor structure including a first P-region, a first N-region, a second P-region and a second N-region disposed in series between the first and second terminals, and an electrode for inducing an electric field into the second P-region. The induced electric field increases the number of charge carriers in the second P-region, and enables the device to be triggered at a lower voltage applied between the first and second terminals. The electrode includes an insulated gate, and can be connected to either the first or second terminal. The gate can include a thick field oxide layer, or a thin oxide layer to further reduce the triggering voltage.

Abstract: A lateral field effect transistor includes a semiconductor substrate, a source region further with source region stripes formed on the semiconductor substrate, and a drain region with drain region stripes formed on the semiconductor substrate and spaced laterally from the source region stripes. In addition, the lateral field effect transistor includes a source electrode having a first source electrode layer connected to the source region via a source contact and a second source electrode layer straddling the source region stripes and the drain region stripes. The first source electrode layer and the second source electrode layer are separated by an inter-layer insulation film and connected via a source connection hole formed through the inter-layer insulation film.

Abstract: An Input/Output (I/O) circuit (11) for an integrated circuit including Electrostatic Discharge Protection (ESD) circuitry is disclosed. A Silicon Controlled Rectifier SCR (30) is triggered by a transistor (36) which is scaled to an output transistor (24) of the I/O circuit (11) to shunt an ESD event. The SCR (30) couples between a pad (12) and a power supply line V.sub.SS. The transistor (36) is disabled. The triggering mechanism is voltage breakdown of the transistor (36) due to an ESD event. The SCR protection mechanism is process independent since the triggering mechanism is formed similarly to the output transistor (24) and thus breaks-down similarly. Zener diodes (26-29) are coupled to gates of the I/O circuit (11) and between the power supply lines. A phosphorous doping less than 5.0 E18 per cubic centimeter is used to form the cathode of zener diodes (26-29).

Abstract: A voltage-controlled power monolithic bidirectional switch has two main terminals and includes a control electrode whose voltage is referenced to one of the main terminals. The switch includes a lateral P-channel MOS transistor; a vertical N-channel MOS transistor, the source well of the vertical N-channel MOS transistor also constituting the source of the lateral transistor; a lateral thyristor whose first three regions correspond to the source, drain and channel of the lateral MOS transistor; a first vertical thyristor disposed in parallel with the lateral thyristor; and a second vertical thyristor having a polarity opposite to the first polarity and disposed in parallel with the vertical MOS transistor.

Abstract: A field-effect-controlled semiconductor device has a cathode, an anode, and a gate, and extends laterally on a first insulating layer covering a substrate. The device includes a main thyristor, a MOSFET switch and a diode which connects a highly doped region embedded in a first part of a second base region of the thyristor to the cathode of the device.

Abstract: An insulated-gate semiconductor device comprises a p type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.

Abstract: An electrostatic discharge (ESD) circuit for protecting a semiconductor integrated circuit (IC) device is disclosed. One ESD circuit is located between each I/O buffering pad that connects to one lead pin and the internal circuitry of IC. The ESD circuit is connected to both power terminals. The ESD circuit comprises first and second low-voltage-trigger SCRs (LVTSCRs), each having an anode, a cathode, an anode gate and a cathode gate. The anode and anode gate of the first SCR are connected to a first power terminal, the cathode of the first SCR is connected to its I/O buffering pad, and the cathode gate of the first SCR is connected to the second power terminal. The ESD circuit further comprises a PMOS transistor having drain, source, gate, and bulk terminals. The PMOS transistor's gate, source and bulk terminals are connected to the first power terminal, the PMOS transistor drain terminal is connected to the cathode gate of the first SCR.

Abstract: An insulated-gate bipolar transistor includes a semiconductor region of a first conductive type; a base layer of a second conductive type diffused from a surface of the semiconductor region; a source layer of the first conductive type diffused in a surface portion of the base layer; an insulated gate buried in a recess dug from the surface of the source layer through the base layer up to the semiconductor region; a collector layer of the second conductive type diffused from a surface of the semiconductor region on an opposite side of the insulated gate with respect to the source layer; an emitter terminal drawn from the base layer and the source layer; a collector terminal drawn from the collector layer; and a gate terminal drawn from the insulated gate.

Abstract: A semiconductor device which allows an ON-state voltage to be lower than that of a conventional device and a method of manufacturing such a device. In this semiconductor device, a gate electrode is formed to have a planar area of its region covering a first base layer larger than that of its region covering a second base layer, thereby increasing a cathode short-circuit ratio of a cathode-shorted diode equivalent to this semiconductor device. As a result, a lower voltage than conventional ON-state can be obtained.

Abstract: An integrated circuit is provided with particular application for high frequency modulation circuits, such as a mixer circuit, with reduced noise and gain. The circuit provides a novel application of a single device comprising a 4 or 5 terminal, gate controlled lateral bipolar junction transistor device, in the form of a merged MOS and lateral bipolar transistor. In a grounded base configuration, RF and LO signals are applied to the gate and emitter terminals respectively and provide for modulated output at the collector, and provides signal modulation with reduced noise compared with multi-device implementations of known mixer circuits using a summation circuit, diodes and FETs. Advantageously, operation of the device in the grounded base or grounded emitter configuration provides for strong modulation of the DC current gain, i.e. over 4 decades, as a function of gate voltage.

Abstract: In this semiconductor device, first, fifth and fourth impurity regions of a second conductivity type are formed on a main surface of a semiconductor layer of a first conductivity type with a predetermined space between each other. Second and third impurity regions of the first conductivity type are formed on the main surface of the first impurity region with a predetermined space between each other. A second gate electrode is formed between the second and third impurity regions. A first gate electrode is formed between the third impurity region and the semiconductor layer. A cathode electrode is connected to the third impurity region, and a short-circuit electrode is connected to first and second impurity regions. The first and fifth impurity regions are electrically short-circuited.

Abstract: In a collector side portion of an insulated gate bipolar transistor, there are provided, for example, a p-type collector layer diffused into an n-type semiconductor region, an n-type carrier extraction layer diffused into the semiconductor region opposite to an emitter side portion and a field effect transistor portion having an auxiliary gate disposed between the collector layer and the carrier extraction layer. The field effect transistor portion is controlled by the auxiliary gate in such a manner that during its "off" state the collector layer is separated from the carrier extraction layer connected to a collector terminal to cause its potential to float so that the majority carriers flowing in a transverse direction below the collector layer prevent minority carriers from being injected from the collector layer into the semiconductor region, thereby shortening the "off" operation time.

Abstract: A composite integrated circuit device includes a semiconductor element chip, a positioning guide formed on the semiconductor element chip, and an electronic element set in a preset position on the semiconductor element chip in a self-alignment manner by means of the positioning guide and mounted thereon. Also disclosed is are lateral, thin film devices with tapered shapes to reduce breakdown.

Abstract: A monolithically integrated, transistor bridge circuit of a type suiting power applications, comprises at least one pair of IGBT transistors (M1,M2) together with vertically-conducting bipolar junction transistors transistors (T1,T2). These IGBT transistors are laterally conducting, having drain terminals (9,19) formed on the surface of the integrated circuit (1), and through such terminals, they are connected to another pair of transistors (T1,T2) of the bipolar type.

Abstract: The present invention includes a BiMOS device having an MOS transistor that triggers a bipolar transistor, wherein the base and channel region are formed within a well region that electrically floats. The present invention also includes a BiMOS device having separate regions for the collector and drain regions and for the base and channel regions. The present invention further includes processes for forming the BiMOS devices. The BiMOS device may include a floating well region. The BiMOS device may include both low voltage MOS logic transistors and a high voltage or high power bipolar transistor. A low voltage or low power bipolar transistor may also be used. Separate drain, collector, base, and channel regions allow the bipolar transistor performance to be optimized independently of the MOS transistor, which may have its performance independently optimized, too. A plurality of MOS logic transistors, such as an AND or an OR gate may be used in the BiMOS device.

Abstract: A trench gate lateral MOSFET structure has the voltage supported along side walls and the bottom surface of the trench. With narrow source and drain mesa regions that are optimally doped, a uniform electric field is obtained vertically in the mesa regions and horizontally at the bottom of the trench, allowing a relative high doping level in an N-drift region resulting in specific on-resistances well below those of conventional lateral MOSFETs at a high breakdown voltage.

Abstract: A semiconductor switching device having gate-controlled regenerative and non-regenerative conduction modes includes a P-N-P-N thyristor and a diverter region in a semiconductor substrate. Regenerative conduction can be initiated by electrically connecting the thyristor's cathode region and first base region in response to a first bias signal. Non-regenerative conduction can also be initiated by electrically connecting the thyristor's second base region to the diverter region in response to a second bias signal, after regenerative conduction has been initiated. Alternative, non-regenerative conduction can be initiated by electrically connecting the thyristor's second base region to the diverter region and then electrically connecting the thyristor's first base region to the cathode region.

Abstract: A compound semiconductor device is provided which includes a thyristor region constructed by four continuous layers of p-n-p-n and an MOSFET region which is formed in the intermediate n layer of the thyristor region so as to be away from the intermediate p layer. The MOSFET is constructed by a p well layer, a source layer, and a drain layer. One main electrode of the device is in ohmic contact with the outside p layer of the thyristor region. While the other main electrode is in ohmic contact with the source layer and well layer of the MOSFET region. An arrangement is provided for electrically connecting the outside n layer of the thyristor region and the drain layer of the MOSFET region. Also, a first insulating gate is formed on the well layer between the source layer and the drain layer of the MOSFET region and a second insulating gate is formed on the intermediate p layer of the thyristor region; with the first and second insulating gates being electrically connected.

Abstract: A lateral insulated-gate bipolar transistor has a drift region having therein a base layer and a collector layer. An emitter layer is formed in the base layer. A gate electrode structure, comprising a control electrode and gate insulating layer, contacts the base layer, and also contacts the drift layer and the emitter layer. An emitter electrode contacts the emitter layer, and also the base layer, and a collector electrode contacts the collector layer. The emitter and collector electrodes are elongate and the ratio of their resistances per unit length is in the range of 0.5 to 2.0. This reduces the possibility of a localized high current density along the electrodes, thereby reducing the risk of latch-up due to parasitic thyristors. The collector and emitter electrodes may be of the same width and thickness, or of different widths and thicknesses, or may each have an auxiliary part (for example, in a multi-layer wiring arrangement), so that their resistances per unit length are in the desired range.

Abstract: On the p.sup.- substrate, the n.sup.- epitaxial layer is surrounded and isolated by the p well. In the surface of the n.sup.- epitaxial layer, there is provided the p floating region in the vicinity of the p well, on which the sense electrode is provided. The insulation film and the conductive film are formed on the n.sup.- epitaxial layer between the p well and the p floating region to overlap them. The conductive film and the p floating region serve as a composite field plate, which makes it hard that the surface electric field distribution is influenced by the state of electric charge in the surface and relieves the surface electric field by expanding the depletion layer, which extends from the pn junction between the n.sup.- epitaxial layer and the p well into the n.sup.- epitaxial layer in current blocking state, toward the center of the n.sup.- epitaxial layer.

Abstract: A semiconductor layer made of an epitaxial growing layer (16) is formed on the surface of a p.sup.- -type silicon semiconductor substrate (11), first impurity regions are formed by p.sup.+ -type buried regions (171, 172) and a p-type impurity regions (221, 222) throughout the semiconductor layer from its surface to the semiconductor substrate so as to divide said semiconductor layer into side element regions (161, 162) and a central island region (163). An anode layer obtained by alternately arranging n.sup.+ -type impurity regions (251 to 253) and p.sup.+ -type impurity regions (231, 232) is formed in surface regions of the pair of impurity regions, and cathode regions made of p-type impurity regions (231, 232) are formed in the element regions of the semiconductor layer. Gate electrodes are formed to be opposite to each other through a gate insulating film in p-n junction portions constituted by the n.sup.+ -type impurity regions (251, 252) the p-type impurity regions (221, 222), and an n.sup.

Abstract: A circuit for protecting a CMOS chip against damage from electrostatic discharges (ESD) has four SCRs connected between the line to be protected and the two power supply termiamls, V.sub.DD and V.sub.SS. The SCRs are poled to conduct ESD current of either polarity to each power supply terminal. The bipolar transistors for the SCRs and the associated component are arranged in the chip in an advantageous way that reduces the input/output parasitic capacitance and improves the protection capability of this proposed circuit with a low ESD trigger-on voltage.