Abstract: A semiconductor apparatus in accordance with the present teachings may include an identification information register configured to store identification information for identifying a semiconductor apparatus. The semiconductor apparatus may further include an identification information decoder configured to decode the identification information and output a decoding result as a select signal. The semiconductor apparatus may also include a word line enable control circuit configured to generate a word line control signal for enabling or disabling all word lines of the semiconductor apparatus simultaneously at a predetermined time according to the select signal.

Abstract: A TI-IGBT, comprising a first semiconductor substrate, a second semiconductor substrate, and a first doped layer; a short circuit region and a collector region disposed in parallel are formed in the first semiconductor substrate; the short circuit region and the collector region have different doping types; the second semiconductor substrate is located on the upper surface of the first semiconductor substrate, and has the same doping type with the short circuit region; the first doped layer is located between the first semiconductor substrate and the second semiconductor substrate, and covers at least the collector region; the first doped layer has the same doping type with the second semiconductor substrate, and has a doping concentration smaller than that of the second semiconductor substrate.

Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode, the switching layer comprising a first metal oxide having a first bandgap greater than 4 electron volts (eV), the switching layer having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a second metal oxide having a second bandgap greater the first bandgap, the coupling layer having a second thickness that is less than 25 percent of the first thickness.

Abstract: A variable resistance memory device that includes a first electrode, a second electrode, a variable resistance layer interposed between the first electrode and a second electrode. A metal oxide electrode is interposed between the first electrode and the variable resistance layer, and the metal oxide electrode does not include a nitrogen constituent.

Abstract: A two terminal device which can be used for the rectification of the current. Internally it has a regenerative coupling between MOS gates of opposite type and probe regions. This regenerative coupling allows to achieve performance better than that of ideal diode.

Abstract: Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed.

Abstract: Some embodiments include memory cells. A memory cell may contain a switching region and an ion source region between a pair of electrodes. The switching region may be configured to reversibly retain a conductive bridge, with the memory cell being in a low resistive state when the conductive bridge is retained within the switching region and being in a high resistive state when the conductive bridge is not within the switching region. The memory cell may contain an ordered framework extending across the switching region to orient the conductive bridge within the switching region, with the framework remaining within the switching region in both the high resistive and low resistive states of the memory cell.

Abstract: A method for fabricating an image sensor is described. A substrate is provided. Multiple photoresist patterns are formed over the substrate, and then a thermal reflow step is performed to convert the photoresist patterns into multiple microlenses arranged in an array. The focal length of the microlens increases from the center of the array toward the edge of the array.

Abstract: An apparatus and method for storing information are provided, including using a transistor having a channel, a gate oxide layer, a gate electrode, and a modifiable gate stack layer. The on-resistance of the transistor is changed by causing a non-charge-storage based physical change in the modifiable gate stack layer, to store information.

Abstract: The power semiconductor element has an emitter region and a stop zone in front of the emitter region. The conductivities of the emitter region and of the stop zone are opposed to one another. In order to reduce not only the static but also the dynamic loss of the power semiconductor foreign atoms are used in the stop-zone. The foreign atoms have at least one energy level within the band gap of the semiconductor and at least 200 meV away from the conduction band and valence band of the semiconductor.

Abstract: A thyristor-based memory device may comprise two base regions of opposite type conductivity formed between a cathode-emitter region and an anode-emitter region. A junction defined between the p-base region and the cathode-emitter region of the thyristor may be “treated” with a high ionization energy acceptor such as indium in combination with carbon as an activation assist species. These two implants may form complexes that may extend across the junction region.

Abstract: A silicon controlled rectifier structure with the symmetrical layout is provided. The N-type doped regions and the P-type doped regions are disposed with the N-well and symmetrically arranged relative to the isolation structure in-between, while the P-type buried layer is located under the N-type doped regions and the P-type doped regions and fully isolates the N-type doped regions from the N-well.

Abstract: A vertical-type semiconductor device for controlling a current flowing between electrodes opposed against each other across a semiconductor substrate, including: a semiconductor substrate having first and second surfaces opposed against each other; a first electrode formed in the first surface; a second electrode formed in the second surface through a high-resistance electrode whose resistance is Rs; and a third electrode formed along at least a part of the outer periphery of the second surface, wherein a potential difference Vs between the second and third electrodes is measured with a current I flowing between the first and second electrodes, and the current I is detected from the resistance Rs and the potential difference Vs.

Abstract: Disclosed are a variable mask device for crystallizing a silicon layer capable of controlling a width and a length of an opening, and a method for crystallizing a silicon using the variable mask device. The variable mask device has a frame with an opening whose width is controlled by an X direction actuator and whose length is controlled by a Y direction actuator. A substrate on which a plurality of unit liquid crystal display panels are formed is provided. A laser beam is aligned through the opening and the silicon layer formed on the substrate is irradiated with the laser beam, thereby crystallizing the silicon layer. The substrate is moved in an X direction by scanning distance and the silicon layer is irradiated until the silicon layer is entirely crystallized.

Abstract: A silicon oxide film as an insulating film is accumulated so as to cover a whole surface of a silicon substrate including a surface of a resistance element by, for example, a thermal CVD method, just after a resist pattern is removed. This silicon oxide film is processed to form a silicide block on the resistance element, and side wall spacers at both side surfaces of gate electrodes, and so on, of respective transistors, at the same time.

Abstract: A SiC gate turn-off (GTO) thyristor that exhibits improved greatly performance includes a p-type anode region, a n-type gated base region positioned beneath the anode region, a n-type drift region positioned beneath the gated base region and doped to a lower concentration of donors than that of the gated base region, a p-type buffer region positioned beneath the n-type drift region and doped with acceptors to a concentration whose magnitude lies between the doping concentration of the anode region and the drift region, and an n-type substrate positioned beneath the buffer region. In another aspect of the invention of this application, a silicon or silicon carbide gate-turn-off thyristor includes a GTO thyristor structure with a thick buffer layer having a high, free-carrier recombination rate.

Abstract: An IGBT has a punch-through structure including an n+ buffer layer. It includes a p− low concentration layer formed between the n+ buffer layer and a p+ drain layer. Owing to the low concentration layer, the drain current decreases to zero gradually, not rapidly, when the IGBT is turned off.

Abstract: A high frequency high voltage semiconductor device having a shifted doping profile and method for forming the same are provided. Specifically, the present invention provides a semiconductor device (<250V) in which the doping profile is shifted towards the source or body region of the device. The shift in doping profile under the present invention allows both transconductance and capacitance to be optimized so that a SOI device can operate at high frequencies.

Abstract: A vehicle system is disclosed that includes a vehicle lamp assembly including a plurality of LEDs that emit white light so as to function as an illuminator light. The lamp assembly also may include a plurality of LEDs that emit colored light, such as red or red-orange, so as to function as a signal light. Alternatively or additionally, the lamp assembly may include a camera of a vehicle imaging system. The lamp assembly may serve as a center high mounted stop light or as a tail light. The system also includes a controller that rapidly pulses the LEDs on and off at a rate that is imperceivable by the human eye. The pulsing intervals of the LEDs may be related to the readout intervals of the camera sensor array. In this manner, the LEDs may be pulsed on during camera readout so as to increase their intensity while the camera is capturing an image, or may be pulsed off during camera readout to prevent feedback glare from interfering with image capture by a highly sensitive image sensor array of the camera.

Abstract: The semiconductor switching element blocks in both directions between a first and a second load terminal. The switching element has a field effect transistor and a bipolar transistor. The field effect transistor has a controlled gate, a source connected to the first load terminal, a drain connected to the second load terminal and a body connection. The bipolar transistor has a base, an emitter, and a collector. The emitter is connected to the body connection of the field effect transistor.

Abstract: An active matrix substrate includes a substrate composed of resin, and a polysilicon thin film diode formed on the substrate. The polysilicon thin film diode may be a lateral diode centrally having a region into which impurity is doped. As an alternative, the polysilicon thin film diode may be comprised of two lateral diodes electrically connected in parallel to each other and arranged in opposite directions.

Abstract: An insulated gate bipolar transistor having a high breakdown voltage in a reverse blocking mode and a method for fabricating the same are provided. The insulated gate bipolar transistor includes a relatively low-concentration lower buffer layer and a relatively high-concentration upper buffer layer. The low-concentration lower buffer layer contacts a semiconductor substrate having a high concentration of first conductivity type impurities used as a collector region, and the high-concentration upper buffer layer contacts a drift region of a second conductivity type. The conductivity type of the upper buffer layer is second conductivity type impurities, and the conductivity type of the lower buffer layer is substantially intrinsic, or first conductivity type impurities, or second conductivity type impurities. According to the present invention, due to the high-concentration upper buffer layer, the thickness of the drift region can be reduced, and during a forward continuity, a switching speed can be improved.

Abstract: The power semiconductor element has an emitter region and a stop zone in front of the emitter region. The conductivities of the emitter region and of the stop zone are opposed to one another. In order to reduce not only the static but also the dynamic loss of the power semiconductor foreign atoms are used in the stop-zone. The foreign atoms have at least one energy level within the band gap of the semiconductor and at least 200 meV away from the conduction band and valence band of the semiconductor.

Abstract: A semiconductor component has a semiconductor body with at least one integrated lateral resistor. The lateral resistor is formed with a dopant concentration in the resistor region. The resistor region is located in a region which is accessible from the surface of the semi-conductor component and it has a defined dopant concentration. Scattering centers are provided in the region of the lateral resistor which reduce a temperature dependency of the lateral resistor.

Abstract: A solar cell with a heightened open-circuit voltage and improved junction quality of the interface between an interfacial layer (or buffer layer) and a thin-film light absorbing layer is disclosed. A thin-film solar cell is fabricated on a glass substrate and includes a metallic back electrode, a light absorbing layer, an interfacial layer, a window layer, and an upper electrode. The solar cell is characterized by the light absorbing layer. The light absorbing layer is a thin film of p-type Cu(InGa)Se.sub.2 (CIGS) of the Cu-III-VI.sub.2 chalcopyrite structure and has such a gallium concentration gradient that the gallium concentration gradually (gradationally) increases from the surface thereof to the inside, thereby attaining a heightened open-circuit voltage. The light absorbing layer has on its surface an ultrathin-film surface layer of Cu(InGa)(SeS).sub.2 (CIGSS), which has such a sulfur concentration gradient that the sulfur concentration abruptly decreases from the surface thereof (i.e.

Abstract: A method and apparatus for the localized reduction of the lifetime of charge carriers in integrated electronic devices. The method comprises the step of implanting ions, at a high dosage and at a high energy level, of a noble gas, preferably helium, in the active regions of the integrated device so that the ions form bubbles in the active regions. A further thermal treatment is performed after the formation of bubbles of the noble gas in order to improve the structure of the bubbles and to make the noble gas evaporate, leaving cavities in the active regions.

Abstract: The power thyristor of this invention has a cellular emitter structure. Each cell also has a FET assisted turn-on gate integrated into the cell. A turn-on gate voltage of one polarity is applied to a FET gate element that overlies the surface of the cell and to the turn-on gate integrated into the cell. When this voltage is so applied, a channel underlying the FET gate element becomes conductive, which allows the integrated turn-on gate to provide drive to the upper base-upper emitter junction of the thyristor cell thereby turning the thyristor cell on.

Abstract: The present invention provides a reverse conducting (RC) thyristor of a planar-gate structure for low-and-medium power use which is relatively simple in construction because of employing a planar structure for each of thyristor and diode regions, permits simultaneous formation of the both region and have high-speed performance and a RC thyristor of a buried-gate or recessed-gate structure which has a high breakdown voltage by the use of a buried-gate or recessed-gate structure, permits simultaneous formation of thyristor and diode regions and high-speed, high current switching performance, and the RC thyristor of the planar-gate structure has a construction which comprises an SI thyristor or miniaturized GTO of a planar-gate structure in the thyristor region and an SI diode of a planar structure in the diode region, the diode region having at its cathode side a Schottky contact between n emitters or diode cathode shorted region and the thyristor region having at its anode side an SI anode shorted structure fo

Abstract: In turn-off semiconductor components such as GTO thyristors, the semiconductor body can be locally overheated and destroyed as a consequence of inhomogeneities. The anode-side emitter is therefore doped with additional substances that locally compensate the emitter doping above the operating temperature and locally reduce the current amplification factor of the anode-side transistor structure. An increased turn-off current is thus achieved.

Abstract: A field-effect semiconductor device for reducing on-state source-drain voltage and increasing breakdown voltage, has a one conductivity type semiconductor region, a source region of one conductivity type, a drain region, and gate regions of other conductivity type. The source region, the drain region and the gate regions are formed in the semiconductor region and contiguous to a surface of the semiconductor region. The gate regions are located so as to sandwich a portion of the semiconductor region coupling the source region and the drain region.

Abstract: For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.3 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay.

Abstract: Controllable power semiconductor components such as, for example, IGBTs and thyristors are provided, which, compared to known components, have a relatively lightly doped n-buffer zone, a relatively flat p-emitter, and an n-base having a comparatively long charge carrier life expectancy. An advantage is achieved that the controllable power semiconductor component has a temperature-independent tail current, despite a low on-state dc resistance and a high blocking voltage.

Abstract: There is disclosed a semiconductor device wherein a p layer (7) is formed in an isolating portion (Z) and portions (1a, 1b) of an n-type base layer (1) lie on opposite sides of the p layer (7), the upper surfaces of the p layer (7) and the portions (1a, 1b) lying in the same plane as the upper surface of a p layer (3). The presence of the p layer (7) provides for high resistance to breakdown and high formation accuracy of the p layers (2, 3, 7) as compared with a structure in which the isolating portion (Z) lies in the bottom of a the recess, whereby the semiconductor device is less susceptible to short-circuit between the p-type base layer (2) and the p layer (3).

Abstract: Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.

Abstract: The present invention is directed to power semiconductor devices and, more particularly, to a semiconductor device with a static induction buffer structure which reduces the resistance of a buffer layer, enhances the injection efficiency of holes from the anode and permits the application of a high-intensity electric field across the cathode and anode, and a semiconductor device with a drift buffer structure in which an impurity density (concentration) gradient is set in a buffer layer to generate an internal electric field for holes to enhance the injection efficiency of holes from the anode and increase the electron storage efficiency or and impurity density (concentration) gradient is set in an anode region to generate an internal electric field for electrons and a high-intensity electric field can be applied across the cathode and anode.