Abstract: A semiconductor device includes an N-type silicon carbide layer, a P-type region, an N-type source region, a P-type contact region, a gate insulating film, a gate electrode, and a source electrode on the front surface side of an N-type silicon carbide substrate. A drain electrode is located on the back surface of the N-type silicon carbide substrate. A life time killer introduction region is located along an entire interface of the N-type silicon carbide layer and the bottom face of the P-type region. The life time killer is introduced by implanting helium or protons from the back surface side of the N-type silicon carbide substrate after forming a surface structure of an element on the front surface side of the N-type silicon carbide substrate and before forming the drain electrode.

Abstract: A small semiconductor device having a diode forward voltage less likely to change due to a gate potential is provided. An anode and an upper IGBT structure (emitter and body) are provided in a range in the substrate exposed at the upper surface. A trench, a gate insulating film, and a gate electrode extend along a border of the anode and the upper IGBT structure. Cathode and collector are provided in a range in the substrate exposed at the lower surface. A drift is provided between an upper structure and a lower structure. A crystal defect region extends across the drift above the cathode and the drift above the collector. When a thickness of the substrate is defined as x [?m] and a width of a portion of the crystal defect region that protrudes above the cathode is defined as y [?m], y?0.007x2?1.09x+126 is satisfied.

Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, including: a substrate; two field oxide regions formed in the substrate; two pseudo buried layers, each being formed under a corresponding one of the field oxide regions; a collector region formed between the field oxide regions, the collector region laterally extending under a corresponding one of the field oxide regions and each side of the collector region being connected with a corresponding one of the pseudo buried layers; a matching layer formed under both the pseudo buried layers and the collector region; and two deep hole electrodes, each being formed in a corresponding one of the field oxide regions, the deep hole electrodes being connected to the corresponding ones of the pseudo buried layers for picking up the collector region. A manufacturing method of the SiGe HBT is also disclosed.

Abstract: A semiconductor device includes an IGBT forming region and a diode forming region. The IGBT forming region includes an IGBT operating section that operates as an IGBT and a thinned-out section that does not operate as an IGBT. The IGBT operating section includes a channel region, and the thinned-out section includes a first anode region. The diode forming region includes a second anode region. When an area density is defined as a value calculated by integrating a concentration profile of second conductivity type impurities in each of the channel region, the first anode region, and the second anode region in a depth direction, an area density of the channel region is higher than an area density of the first anode region and an area density of the second anode region.

Abstract: A bidirectional switch controllable by a voltage between its gate and rear electrode and including an N-type semiconductor substrate surrounded with a P-type well; on the front surface side, a P-type well in which is formed a first N-type region; on the rear surface side, a P-type layer in which is formed a second N-type region. The well is doped to less than 1016 at./cm3, the exposed surfaces of this well being heavily P-type doped. At least a third P-type region, of same doping level as the well, is formed on the front surface side in the substrate, and contains at least a fourth N-type region of a doping level lower than 1017 at./cm3, on which is formed a Schottky contact.

Abstract: A semiconductor device includes a first device and a second device, which are implemented laterally next to each other in a substrate. A recombination zone is implemented in the substrate between the first device and the second device, so that diffusing charge carriers recombine between the first device and the second device.

Abstract: An example embodiment is a memory cell including a SOI substrate. A first and second set of lateral bipolar transistors are fabricated on the SOI substrate. The first and second set of lateral bipolar transistors are electrically coupled to form two inverters. The inverters are cross coupled to form a memory element.

Abstract: A method and structures are provided for implementing vertical transistors utilizing wire vias as gate nodes. The vertical transistors are high performance transistors fabricated up in the stack between the planes of the global signal routing wire, for example, used as vertical signal repeater transistors. An existing via or a supplemental vertical via between wire planes provides both an electrical connection and the gate node of the novel vertical transistor.

Abstract: Provided is a semiconductor device including a substrate, and a first wiring layer, a second wiring layer, and a switch via formed on the substrate. The first wiring layer has first wiring formed therein and the second wiring layer has second wiring formed therein. The switch via connects the first wiring and the second wiring. The switch via includes at least at its bottom a switch element including a resistance change layer. A resistance value of the resistance change layer changes according to a history of an electric field applied thereto.

Abstract: A nitride semiconductor LED device including an N-type doped layer, an active layer and a P-type doped layer is provided. The active layer is disposed on the N-type doped layer and includes at least one quantum well structure. The quantum well structure includes two quantum barrier layers and a quantum well sandwiched between the quantum barrier layers. The quantum barrier layer is a super-lattice structure including a quaternary nitride semiconductor. The P-type doped layer is disposed on the active layer.

Abstract: A semiconductor component is disclosed. One embodiment provides a semiconductor body having a cell region with at least one zone of a first conduction type and at least one zone of a second conduction type in a rear side. A drift zone of the first conduction type in the cell region is provided. The drift zone contains at least one region through which charge carriers flow in an operating mode of the semiconductor component in one polarity and charge carriers do not flow in an operating mode of the semiconductor component in an opposite polarity.

Abstract: The present invention provides a multi-finger structure of a SiGe heterojunction bipolar transistor (HBT). It is consisted of plural SiGe HBT single cells. The multi-finger structure is in a form of C/BEBC/BEBC/.../C, wherein, C, B, E respectively stands for collector, base and emitter; CBEBC stands for a SiGe HBT single cell. The collector region is consisted of an n type ion implanted layer inside the active region. The bottom of the implanted layer is connected to two n type pseudo buried layers. The two pseudo buried layers are formed through implantation to the bottom of the shallow trenches that surround the collector active region. Two collectors are picked up by deep trench contact through the field oxide above the two pseudo buried layers. The present invention can reduce junction capacitance, decrease collector electrode output resistance, and improve device frequency characteristics.

Abstract: A vertical pillar semiconductor device may include a substrate, a group of channel patterns, a gate insulation layer pattern and a gate electrode. The substrate may be divided into an active region and an isolation layer. A first impurity region may be formed in the substrate corresponding to the active region. The group of channel patterns may protrude from a surface of the active region and may be arranged parallel to each other. A second impurity region may be formed on an upper portion of the group of channel patterns. The gate insulation layer pattern may be formed on the substrate and a sidewall of the group of channel patterns. The gate insulation layer pattern may be spaced apart from an upper face of the group of channel patterns. The gate electrode may contact the gate insulation layer and may enclose a sidewall of the group of channel patterns.

Abstract: A fast injection optical switch is disclosed. The optical switch includes a thyristor having a plurality of layers including an outer doped layer and a switching layer. An area of the thyristor is configured to receive a light beam to be directed through at least one of the plurality of layers and exit the thyristor at a predetermined angle. At least two electrodes are coupled to the thyristor and configured to enable a voltage to be applied to facilitate carriers from the outer doped layer to be directed to the switching layer. Sufficient carriers can be directed to the switching layer to provide a change in refractive index of the switching layer to redirect at least a portion of the light beam to exit the thyristor at a deflection angle different from the predetermined angle.

Abstract: The present invention provides a multi-finger structure of a SiGe heterojunction bipolar transistor (HBT). It is consisted of plural SiGe HBT single cells. The multi-finger structure is in a form of C/BEBC/BEBC/.../C, wherein, C, B, E respectively stands for collector, base and emitter; CBEBC stands for a SiGe HBT single cell. The collector region is consisted of an n type ion implanted layer inside the active region. The bottom of the implanted layer is connected to two n type pseudo buried layers. The two pseudo buried layers are formed through implantation to the bottom of the shallow trenches that surround the collector active region. Two collectors are picked up by deep trench contact through the field oxide above the two pseudo buried layers. The present invention can reduce junction capacitance, decrease collector electrode output resistance, and improve device frequency characteristics.

Abstract: In a bipolar device, such as transistor or a thyristor, the emitter layer or the anode layer is formed of two high-doped and low-doped layers, a semiconductor region for suppressing recombination comprising an identical semiconductor having an impurity density identical with that of the low-doped layer is present being in contact with a base layer or a gate layer and a surface passivation layer, and the width of the semiconductor region for suppressing recombination is defined equal with or longer than the diffusion length of the carrier. This provides, among other things, an effect of attaining reduction in the size of the bipolar transistor or improvement of the switching frequency of the thyristor without deteriorating the performance.

Abstract: An integrated switching device has a switching IGFET connected between a pair of main terminals, a protector IGFET connected between the drain and gate electrodes of the switching IGFET, and a gate resistor connected between a main control terminal and the gate electrode of the switching IGFET. The protector IGFET has its gate electrode connected to the source electrode of the switching IGFET. The protector IGFET turns on in response to an application of a verse voltage to the switching IGFET thereby protecting the same from a reverse current flow.

Abstract: A high-efficiency power semiconductor rectifier device (10) comprising a ?P++ layer (12), a P-body (14), an N-drift region (16), an N+ substrate (18), an anode (20), and a cathode (22). The method of fabricating the device (10) comprises the steps of depositing the N-drift region (16) on the N+ substrate (18), implanting boron into the N-drift region (16) to create a P-body region (14), forming a layer of titanium silicide (56) on the P-body region (14), and concentrating a portion of the implanted boron at the interface region between the layer of titanium silicide (56) and the P-body region (14) to create the ?P++ layer (12) of supersaturated P-doped silicon.

Abstract: An object of the present invention is to provide a semiconductor device capable of radiating electron-beams only to a desired region without forming a layer for restricting the radiating rays. A source electrode 22 made of aluminum prevents the generation of bremsstrahlung even when the electron-beams are radiated to the source electrode in a exposed condition. Also, the source electrode having an opening 25 at above of a crystal defect region 11 is used as a mask when the electron-beams are radiated thereto. That is the source electrode made of aluminum can be used both as a wiring and a mask for the radiating rays.

Abstract: The invention relates to a high-voltage diode having a specifically optimized switch-off behavior. A soft recovery behavior of the component can be obtained without increasing the forward losses by adjusting in a specific manner the service life of the charge carriers by irradiating only the n+-conducting cathode emitter (6) side or both sides, i.e. the n+-conducting cathode emitter (6) side and the p+-conducting anode emitter (4) side.

Abstract: The power semiconductor element has an emitter region and a stop zone in front of the emitter region. The conductivities of the emitter region and of the stop zone are opposed to one another. In order to reduce not only the static but also the dynamic loss of the power semiconductor foreign atoms are used in the stop-zone. The foreign atoms have at least one energy level within the band gap of the semiconductor and at least 200 meV away from the conduction band and valence band of the semiconductor.

Abstract: A thyristor-based memory device may comprise two base regions of opposite type conductivity formed between a cathode-emitter region and an anode-emitter region. A junction defined between the p-base region and the cathode-emitter region of the thyristor may be “treated” with a high ionization energy acceptor such as indium in combination with carbon as an activation assist species. These two implants may form complexes that may extend across the junction region.

Abstract: A silicon controlled rectifier structure with the symmetrical layout is provided. The N-type doped regions and the P-type doped regions are disposed with the N-well and symmetrically arranged relative to the isolation structure in-between, while the P-type buried layer is located under the N-type doped regions and the P-type doped regions and fully isolates the N-type doped regions from the N-well.

Abstract: A vertical-type semiconductor device for controlling a current flowing between electrodes opposed against each other across a semiconductor substrate, including: a semiconductor substrate having first and second surfaces opposed against each other; a first electrode formed in the first surface; a second electrode formed in the second surface through a high-resistance electrode whose resistance is Rs; and a third electrode formed along at least a part of the outer periphery of the second surface, wherein a potential difference Vs between the second and third electrodes is measured with a current I flowing between the first and second electrodes, and the current I is detected from the resistance Rs and the potential difference Vs.

Abstract: Semiconductor devices having recombination centers comprised of well-positioned heavy metals. At least one lattice defect region within the semiconductor device is first created using particle beam implantation. Use of particle beam implantation positions the lattice defect region(s) with high accuracy in the semiconductor device. A heavy metal implantation treatment of the device is applied. The lattice defects created by the particle beam implantation act as gettering sites for the heavy metal implantation. Thus, after the creation of lattice defects and heavy metal diffusion, the heavy metal atoms are concentrated in the well-positioned lattice defect region(s).

Abstract: A method for producing a semiconductor component has the following step: the front side (101) of the semiconductor body (100) is irradiated with high-energy particles using the terminal electrode (40) as a mask, in order to produce recombination centres (80A, 80B) in the semiconductor body (100) for the recombination of the first and second conduction type of charge carriers.

Abstract: An object of the present invention is to provide a semiconductor device capable of radiating electron-beams only to a desired region without forming a layer for restricting the radiating rays. A source electrode 22 made of aluminum prevents the generation of bremsstrahlung even when the electron-beams are radiated to the source electrode in a exposed condition. Also, the source electrode having an opening 25 at above of a crystal defect region 11 is used as a mask when the electron-beams are radiated thereto. That is the source electrode made of aluminum can be used both as a wiring and a mask for the radiating rays.

Abstract: A CSTBT includes a carrier stored layer (113) formed between a P base region (104) and a semiconductor substrate (103) and the carrier stored layer has an impurity concentration higher than that of the semiconductor substrate (103). The P base region (104) in a periphery of a gate electrode (110) functions as a channel. When it is assumed that an impurity concentration of a first carrier stored layer region (113a) just under the channel is ND1 and an impurity concentration of a second carrier stored layer region (113b) other than just under the channel is ND2 in the carrier stored layer (113), the relationship of the impurity concentrations is defined by ND1<ND2. Thus, a gate capacity and a short-circuit current can be controlled and variation in threshold voltage can be prevented.

Abstract: In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.

Abstract: A thyristor-based semiconductor device is formed having a thyristor, a pass device and an emitter region buried in a substrate and below at least one other vertically-arranged contiguous region of the thyristor that is at least partially below an upper surface of the substrate. According to an example embodiment of the present invention, a conductor, such as a polysilicon pillar formed in a trench, extends through the substrate and to the buried emitter region of the thyristor. In one implementation, a portion of the conductor includes a reduced-resistance material, such as a salicide, that is adapted to reduce the resistance of an electrical connection made to the buried emitter region via the conductor. This is particularly useful, for example, in connecting the buried emitter region to a power supply at a reduced resistance (e.g., as compared to the resistance that would be exhibited, were the reduced-resistance material not present).

Abstract: A semiconductor device that helps to prevent the occurrence of current localization in the vicinity of an electrode edge and improves the reverse-recovery withstanding capability. The semiconductor device according to the invention includes a first carrier lifetime region, in which the carrier lifetime is short, formed in such a configuration that the first carrier lifetime region extends across the edge area of an anode electrode projection, which projects the anode electrode vertically into a semiconductor substrate. The first carrier lifetime region also includes a vertical boundary area spreading nearly vertically between a heavily doped p-type anode layer and a lightly doped semiconductor layer. The first carrier lifetime region of the invention is formed by irradiating with a particle beam, such as a He2+ ion beam or a proton beam.

Abstract: Various circuit devices incorporating junction-traversing dislocation regions and methods of making the same are provided. In one aspect, a method of processing is provided that includes forming an impurity region in a device region of a semiconductor-on-insulator substrate. The impurity region defines a junction. A dislocation region is formed in the device region that traverses the junction. The dislocation region provides a pathway to neutralize charge lingering in a floating body of a device.

Abstract: The present invention provides a semiconductor device wherein the turning-off time thereof can be reduced substantially and, at the same time, the turned-on resistance thereof can also be prevented effectively from increasing as well. Lattice defects are distributed at a high concentration in a defect region an area in close proximity to the boundary surface between an n drift region and a p+ substrate. The half-value width of the distribution is set at a value which is large enough for the defect region to include a non-depletion region in the n drift region. However, the defect region is not spread to cover a diffusion layer. In this way, the turning-off time of the semiconductor device can be reduced considerably without being accompanied by an increase in turned-on resistance thereof. In addition, by employing an absorber with an uneven surface, the distribution of lattice defects can be obtained by carrying out radiation of ions at only one time.

Abstract: Switching times of a thyristor-based semiconductor device are improved by enhancing carrier drainage from a buried thyristor-emitter region. According to an example embodiment of the present invention, a conductive contact extends to a doped well region buried in a substrate and is adapted to drain carriers therefrom. The device includes a thyristor body having at least one doped emitter region buried in the doped well region. A conductive thyristor control port is adapted to capacitively couple to the thyristor body and to control current flow therein. With this approach, the thyristor can be rapidly switched between resistance states, which has been found to be particularly useful in high-speed data latching implementations including but not limited to memory cell applications.

Abstract: A power semiconductor device including first and second assembly units. The first assembly of units includes a first semiconductor region of a second conductivity type selectively formed in a first main surface of the first semiconductor layer, a second semiconductor region of the first conductivity type selectively formed in a surface of the first semiconductor region, a first gate insulation film formed in contact with at least the surface of the first semiconductor region between the second semiconductor region and the first semiconductor layer, and a first trench-type gate electrode formed on the first gate insulation film and arranged in parallel and extending through the first semiconductor region in a direction of depth thereof.

Abstract: The present invention provides, in a TFT, a channel region facing a gate electrode through a gate insulating film, a source electrode connected to the channel region and a drain region connected to the channel region on the side opposite the source region that are formed in a polycrystal semiconductor film that was patterned in island forms. In the channel region, a recombination center is formed for capturing a small number of carriers (holes) by impurities, such as inert-gas, metals, Group III elements, Group IV elements and Group V elements, introduced to a predetermined region in this channel region, or by defects generated due to the introduction of these impurities. The present invention thus provides an arrangement restraining bipolar transistor type behavior to stabilize saturation current and to provide a TFT that can improve reliability.

Abstract: The semiconductor switching element blocks in both directions between a first and a second load terminal. The switching element has a field effect transistor and a bipolar transistor. The field effect transistor has a controlled gate, a source connected to the first load terminal, a drain connected to the second load terminal and a body connection. The bipolar transistor has a base, an emitter, and a collector. The emitter is connected to the body connection of the field effect transistor.

Abstract: A semiconductor layer, through which a main current flows, is so structured that a carrier life time in the semiconductor layer is ununiform in accordance with a predetermined distribution of the carrier life time. Thus, turn OFF characteristics of a semiconductor switching device can be improved without causing any unacceptable disadvantages for other characteristics.

Abstract: An insulated gate bipolar transistor having a high breakdown voltage in a reverse blocking mode and a method for fabricating the same are provided. The insulated gate bipolar transistor includes a relatively low-concentration lower buffer layer and a relatively high-concentration upper buffer layer. The low-concentration lower buffer layer contacts a semiconductor substrate having a high concentration of first conductivity type impurities used as a collector region, and the high-concentration upper buffer layer contacts a drift region of a second conductivity type. The conductivity type of the upper buffer layer is second conductivity type impurities, and the conductivity type of the lower buffer layer is substantially intrinsic, or first conductivity type impurities, or second conductivity type impurities. According to the present invention, due to the high-concentration upper buffer layer, the thickness of the drift region can be reduced, and during a forward continuity, a switching speed can be improved.

Abstract: A low junction capacitance semiconductor structure and an I/O buffer are disclosed. The semiconductor structure includes a MOS transistor and a lightly doped region. The MOS transistor is formed in a semiconductor substrate and has a gate and source and drain region formed aside the gate. The lightly doped region has a conductivity the same as the source and drain regions, and is formed in the drain region and has a depth larger than the source and drain regions. Further, the lightly doped region can be achieved by CMOS-compatible processes, and the formed devices in the well can be isolated from the semiconductor substrate using deeply doped regions which are usually adopted in advanced technologies.

Abstract: The thyristor is based on a semiconductor body with an anode-side base zone of the first conductivity type and one or more cathode-side base zones of the opposite, second conductivity type. Anode-side and cathode-side emitter zones are provided, and at least one region in the cathode-side base zone whose geometry gives it a reduced breakdown voltage as compared with the remaining regions in the cathode-side base zone and the edge of the semiconductor body. At the anode, below the region of reduced breakdown voltage, the thyristor has at least one recombination zone in which the free charge carriers have a reduced lifetime.

Abstract: A gate terminal plate (1) of a GCT thyristor (90), a connecting substrate (70) of a driving device and a cathode electrode plate (10) are interposed between a set of metal rings (7A) and (7C) fastened to each other with a screw (8). The cathode electrode plate (10) is connected to a cathode post electrode (31) of the GCT thyristor (90). The screw (8) is electrically insulated from the metal ring (7A) and the gate terminal plate (1) through an insulator (9). By this structure, the gate terminal plate (1) and the cathode electrode plate (10) are directly connected to a first metallized layer (5) and a second metallized layer (6) which are provided on two main surfaces of the connecting substrate (70) of the driving device, respectively. Thus, resistance and inductance components in a path for a gate current are reduced and an assembly is simplified.

Abstract: A gate-controlled thyristor in which an IGBT in a first cell and a thyristor in a main cell are connected together in ouch a way that the first cell and the main cell form a lateral FET with a channel of a first conducting type. In an emitter zone of the thyristor, there is a layer embedded that increases the charge carrier recombination in order to reduce the start-up resistance of the gate-controlled thyristor. Trenches, filled with insulated gate electrodes, can be introduced into the lateral FET, so that the FET is a side wall FET.

Abstract: One embodiment of a semiconductor device includes a laterally extending semiconductor base, a buffer adjacent the base and having a first conductivity type dopant, and a laterally extending emitter adjacent the buffer and opposite the base and having a second conductivity type dopant. The buffer is relatively thin and has a first conductivity type dopant concentration greater than a second conductivity type dopant concentration in adjacent emitter portions to provide a negative temperature coefficient for current gain and a positive temperature coefficient for forward voltage for the device. The buffer may be silicon or germanium. A low temperature bonded interface may be between the emitter and the buffer or the buffer and the base. Another embodiment of a device may include a laterally extending localized lifetime killing portion between oppositely doped first and second laterally extending portions.

Abstract: An IGBT is optimized for ZVS operation, thereby significantly reducing switching losses during ZVS operation. In effect, the IGBT is optimized to operate as a MOSFET with a very small bipolar transistor component. Switching losses are reduced by reducing the number of minority carriers injected into the device during conduction. Additionally, this ZVS IGBT structure allows for a small increase in stored charge as the operating temperature is increased, allowing the device to operate at higher temperatures with relatively low switching losses.

Abstract: The present invention relates to a diode, and has an object to simultaneously implement a high di/dt capability, a low reverse recovery loss and a low forward voltage and to suppress generation of voltage oscillation. In order to achieve the above-mentioned object, life time killers are selectively introduced into a semiconductor substrate (20) comprising a P layer (1), an N− layer (21) and an N+ layer (3). A density of the introduced life time killers is the highest in a first region (6) adjacent to the P layer (1), and is the second highest in a second region (7) in the N− layer (21). The life time killers are not introduced into a third region (2). Accordingly, a life time in the N− layer (21) is expressed by the first region (6)<the second region (7)<the third region (2). The second region (7) and the third region (2) are adjacent to the P layer (1). In addition, the second region (7) annularly surrounds the third region (2).

Abstract: A thin film transistor for an antistatic circuit includes: wells formed on a silicon substrate; insulating layers for electrical isolation between electrodes formed within the wells; low density impurity diffused regions respectively interposed between the insulating layers; a first high-density impurity diffused region formed within one low-density impurity diffused region; a second high-density impurity diffused region formed within the other low-density impurity diffused region; interlevel insulating layers formed on the insulating layers and the low-density impurity diffused layers; and metal gate electrodes formed on the low-density impurity diffused layers and the interlevel insulating layers; at least one of the first high-density impurity diffused region and the second high-density impurity diffused region being arranged to overlap on active region, inward from outside edges of the active region.

Abstract: A Schottky diode of SiC has a substrate layer, a drift layer and emitter layer regions formed in the drift layer. A metal layer makes an ohmic contact to the emitter layer regions and Schottky contact to the drift layer. A depletion of the drift layer region between two adjacent emitter layer regions is allowed in the blocking state of the diode making the two adjacent p-type emitter layer regions form a continuous depleted region therebetween in this state.

Abstract: A semiconductor device includes a plurality of defect layers separated from one another in the semiconductor layer. A distance separating any adjacent ones of the defect layers is kept such that they are prevented from contacting each other and those regions having effect of shortening a carrier lifetime overlap each other.

Abstract: An insulated gate thyristor includes a first-conductivity-type base layer having a high resistivity, first and second second-conductivity-type base regions formed in a surface layer of the first-conductivity-type base layer, a first-conductivity-type source region formed in a surface layer of the first second-conductivity-type base region, and a first-conductivity-type emitter region formed in a surface layer of the second second-conductivity-type base region.