Abstract: A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.

Abstract: The present disclosure relates to a display device. An exemplary embodiment of the present invention provides a display device including a substrate and an active pattern positioned above the substrate. To the active pattern includes a channel region and a conductive region having a higher carrier concentration than the channel region. A first insulating layer is disposed on the active pattern. A first conductive layer is disposed on the first insulating layer and includes a first conductor. The channel region of the active pattern includes a first channel region overlapping the first conductor along a direction orthogonal to an upper surface of the substrate. The conductive region of the active pattern includes a first conductive region overlapping the first conductor along the direction orthogonal to the upper surface of the substrate.

Abstract: Provided are an improved memory device and a method of manufacturing the same. In one embodiment, the memory device may include a vertical stack of alternating oxide layer and nitride layer, the vertical stack having a channel region formed therethrough, a plurality of nanostructures selectively formed on nitride layer of the vertical stack, and a gate oxide layer disposed on exposed surfaces of the channel region, the gate oxide layer encapsulating the plurality of nanostructures formed on the nitride layer. The nanostructures may be a group IV semiconductor compound such as silicon germanium (SiGe).

Abstract: A semiconductor device according to example embodiments of inventive concepts may include a substrate, source/drain regions extending perpendicular to an upper surface of the substrate, a plurality of nanosheets on the substrate and separated from each other, and a gate electrode and a gate insulating layer on the substrate. The nanosheets define channel regions that extend in a first direction between the source/drain regions. The gate electrode surrounds the nanosheets and extends in a second direction intersecting the first direction. The gate insulating layer is between the nanosheets and the gate electrode. A length of the gate electrode in the first direction may be greater than a space between adjacent nanosheets among the nanosheets.

Abstract: The present disclosure relates to a display device. An exemplary embodiment of the present invention provides a display device including a substrate and an active pattern positioned above the substrate. to the active pattern includes a channel region and a conductive region having a higher carrier concentration than the channel region. A first insulating layer is disposed on the active pattern. A first conductive layer is disposed on the first insulating layer and includes a first conductor. The channel region of the active pattern includes a first channel region overlapping the first conductor along a direction orthogonal to an upper surface of the substrate. The conductive region of the active pattern includes a first conductive region overlapping the first conductor along the direction orthogonal to the upper surface of the substrate.

Abstract: The present disclosure relates to a solid-state image sensing device capable of restricting an occurrence of a dark current and a method for manufacturing the same, and an electronic device. A solid-state image sensing device includes a FD part formed on a P-type semiconductor substrate by implanting an N-type impurity, a high-dielectric insulative film laminated on at least the FD part, and a contact electrode connected to the FD part in a connection structure via the high-dielectric insulative film. For example, the high-dielectric insulative film is formed by use of a material which reduces the schottky barrier height in a connection part between the FD part and the electrode in a single layer or in a plurality of layers. The present technology is applicable to CMOS image sensors, for example.

Abstract: A nitride semiconductor light-emitting device includes a substrate which includes polycrystal silicon dioxide or amorphous silicon dioxide as a main component, an underlying layer that is provided on the substrate, and a multilayer structure that is provided on the underlying layer and includes at least one layer made of a nitride semiconductor single crystal. The underlying layer includes crystals oriented to a c-axis and is formed by sputtering.

Abstract: A device is provided that comprises a first pillar disposed in a first region and overlying a base structure, and a second pillar disposed in a second region and overlying the base structure and being spaced apart from the first pillar by a device region. A bridge is disposed in the device region with a first end connected to the first pillar and a second end connected to the second pillar. The bridge includes a top, sides, and a bottom. The bridge is formed from one or more heterostructures with an undercut opening extending from the bottom to an underlying structure. A four-sided conductive contact wraps around and substantially surrounds the bridge around its top, its sides, and its bottom along at least a portion of its length between the first and second end.

Abstract: A device is provided that comprises a first pillar disposed in a first region and overlying a base structure, and a second pillar disposed in a second region and overlying the base structure and being spaced apart from the first pillar by a device region. A bridge is disposed in the device region with a first end connected to the first pillar and a second end connected to the second pillar. The bridge includes a top, sides, and a bottom. The bridge is formed from one or more heterostructures with an undercut opening extending from the bottom to an underlying structure. A four-sided conductive contact wraps around and substantially surrounds the bridge around its top, its sides, and its bottom along at least a portion of its length between the first and second end.

Abstract: Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. An interfacial intrinsic non-crystalline semiconductor material layer is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. The presence of the interfacial intrinsic non-crystalline semiconductor material layer improves the surface passivation of the crystalline semiconductor material by reducing the interface defect density at the heterojunction.

Abstract: A method of producing a photovoltaic device includes providing a stretchable substrate for the photovoltaic device; and stretching the substrate to produce a stretched substrate. The method further includes depositing a structure comprising hydrogenated amorphous silicon onto the stretched substrate; and subjecting the deposited hydrogenated amorphous silicon structure and the stretched substrate to a compressive force to form a compressively strained photovoltaic device.

Abstract: Embodiments disclose a method including forming at least one compound semiconductor layer on a top r-face of a substrate, forming a line for cleavage on a bottom r-face of the substrate along a length of a guide line, wherein the guide line extends in a (11-20)-plane direction of the substrate, wherein the guide line extends from one portion of an edge to another portion of the edge, and wherein the edge is disposed between the top r-face and the bottom r-face of the substrate, and applying a force to the bottom r-face of the substrate to cleave the substrate along the line for cleavage in the (11-20)-plane direction and to form a cleaved facet along a m-plane of the at least one compound semiconductor.

Abstract: A magnetic memory device and method of manufacturing the same are provided. The magnetic memory device can include a first vertical magnetic pattern on a substrate, a second vertical magnetic pattern on the first vertical magnetic pattern, and a tunnel barrier pattern disposed between the first vertical magnetic pattern and the second vertical magnetic pattern. The first vertical magnetic pattern can include a first pattern on the substrate, a second pattern on the first pattern, and an exchange coupling pattern between the first pattern and the second pattern. The first pattern can comprise an amorphous magnetic substance and a component comprising at least one of platinum, palladium, and nickel.

Abstract: A miniaturized semiconductor device including a transistor in which a channel formation region is formed using an oxide semiconductor film and variation in electric characteristics due to a short-channel effect is suppressed is provided. In addition, a semiconductor device whose on-state current is improved is provided. A semiconductor device is provided with an oxide semiconductor film including a pair of second oxide semiconductor regions which are amorphous regions and a first oxide semiconductor region located between the pair of second oxide semiconductor regions, a gate insulating film, and a gate electrode provided over the first oxide semiconductor region with the gate insulating film interposed therebetween. Hydrogen or a rare gas is added to the second oxide semiconductor regions.

Abstract: The present disclosure focuses on Ge nanostructured materials for optoelectronic devices: including high-efficiency quantum dot (QD) photodetectors and Si and Ge heteronanowire solar cells. The common thread among these materials is the use of Ge/Si or Ge/oxide barriers to confine carriers and enhance photoconductive gain in detectors and optical absorption and spectral coverage in solar cells.

Abstract: The present invention relates to a heat dissipator that includes a conductive substrate and a plurality of nanostructures supported by the conductive substrate. The nanostructures are at least partly embedded in an insulator. Each of the nanostructures includes a plurality of intermediate layers on the conductive substrate. At least two of the plurality of intermediate layers are interdiffused, and material of the at least two of the plurality of intermediate layers that are interdiffused is present in the nanostructure.

Abstract: Provided is a magnetic memory device and a method of forming the same. A first magnetic conductive layer is disposed on a substrate. A first tunnel barrier layer including a first metallic element and a first non-metallic element is disposed on the first magnetic conductive layer. A second magnetic conductive layer is disposed on the first tunnel barrier layer. A content of an isotope of the first metallic element having a non-zero nuclear spin quantum number is lower than a natural state.

Abstract: According to one embodiment, a memory device with magnetroresistive effect element is disclosed. The element includes first metal magnetic film (MMF) with nonmagnetic element and axis of easy magnetization perpendicular (EMP), first insulating film, first intermediate magnetic film between the first MMF and the first insulating film, second MMF on the first insulating film and including nonmagnetic elements, the second MMF having axis of EMP, second intermediate magnetic film between the first insulating film and the second MMF, and diffusion preventing film including metal nitride having barrier property against diffusion of the nonmagnetic elements between the first MMF and the first intermediate magnetic film.

Abstract: A method of producing a semiconductor device includes the steps of preparing an SOQ (Silicon On Quartz) substrate in which a semiconductor layer is formed on a quartz substrate; forming a plurality of semiconductor device forming regions in the SOQ substrate; forming a crack inspection pattern in the SOQ substrate; inspecting the crack inspection pattern to detect a crack in the crack inspection pattern in a first inspection step; and inspecting the semiconductor device forming regions to detect a crack in the semiconductor device forming regions in a second inspection step when the crack is detected in the crack inspection pattern in the first inspection step.

Abstract: The present invention provides for nanostructures grown on a conducting or insulating substrate, and a method of making the same. The nanostructures grown according to the claimed method are suitable for interconnects and/or as heat dissipators in electronic devices.

Abstract: A semiconductor light emitting device and a method of manufacturing the semiconductor light emitting device are provided. The semiconductor light emitting device comprises a substrate having a top surface that is curved to protrude, and a light emitting structure that is curved to protrude on the substrate and comprises an active layer.

Abstract: A light emitting device of the invention includes an electron transporting layer, a hole transporting layer provided mutually facing the electron transporting layer with a distance between the hole transporting layer and the electron transporting layer, a phosphor layer having a layer of a plurality of semiconductor fine particles sandwiched between the electron transporting layer and the hole transporting layer, a first electrode provided facing the electron transporting layer and connected electrically, and a second electrode provided facing the hole transporting layer and connected electrically: in which the semiconductor fine particles composing the phosphor layer have a p-type part and an n-type part inside of the particles and have a pn-junction in the interface of the p-type part and the n-type part and are arranged in a manner that the p type part is partially brought into contact with the hole transporting layer and at the same time, the n type part is partially brought into contact with the electron

Abstract: The present invention is disclosed that a device capable of normal incident detection of infrared light to efficiently convert infrared light into electric signals. The device includes a substrate, a first contact layer formed on the substrate, an active layer formed on the first contact layer, a barrier layer formed on the active layer and a second contact layer formed on the barrier layer, wherein the active layer includes multiple quantum dot layers.

Abstract: Provided is an optical device having a strained buried channel area. The optical device includes: a semiconductor substrate of a first conductive type; a gate insulating layer formed on the semiconductor substrate; a gate of a second conductive type opposite to the first conductive type, formed on the gate insulating layer; a high density dopant diffusion area formed in the semiconductor substrate under the gate and doped with a first conductive type dopant having a higher density than the semiconductor substrate; a strained buried channel area formed of a semiconductor material having a different lattice parameter from a material of which the semiconductor substrate is formed and extending between the gate insulating layer and the semiconductor substrate to contact the high density dopant diffusion area; and a semiconductor cap layer formed between the gate insulating layer and the strained buried channel area.

Abstract: In a photoelectric conversion device, in a contact between a p-type semiconductor 3a and an electrode 2, an n-type semiconductor 6 of a conductivity type opposite to that of the p-type semiconductor is provided between the p-type semiconductor 3a and the electrode 2. The existence of the n-type semiconductor 6 allows a recombination rate of photo-generated carriers excited by incident light to be effectively reduced, and allows a dark current component to be effectively prevented from being produced. Therefore, it is possible to improve photoelectric conversion efficiency as well as to stabilize characteristics. Further, a tunnel junction is realized by increasing the concentration of a doping element in at least one or preferably both of the p-type semiconductor 3a and the n-type semiconductor 6 in a region where they are in contact with each other, thereby keeping ohmic characteristics between the semiconductor and the electrode good.

Abstract: Disclosed are embodiments of a wafer that incorporates fill structures with varying configurations to provide uniform reflectance. Uniform reflectance is achieved by distributing across the wafer fill structures having different semiconductor materials such that approximately the same ratio and density between the different semiconductor materials is achieved within each region and, optimally, each sub-region. Alternatively, it is achieved by distributing across the wafer fill structures, including one or more hybrid fill structure containing varying proportions of different semiconductor materials, such that approximately the same ratio between the different semiconductor materials is achieved within each region and, optimally, each sub-region.

Abstract: A solid-state memory device includes: a superlattice laminate having plural crystal layers laminated therein, the crystal layers including first and second crystal layers having mutually opposite compositions; a lower electrode provided on a first surface in a laminating direction of the superlattice laminate; and an upper electrode provided on a second surface of the superlattice laminate in the laminating direction. The first crystal layer included in the superlattice laminate is made of a phase change compound. According to the present invention, the superlattice laminate laminated in opposite directions of the upper and lower electrodes is sandwiched between these electrodes. Therefore, when an electric energy is applied to the superlattice laminate via these electrodes, a uniform electric energy can be applied to a laminated surface of the superlattice laminate. Accordingly, fluctuation of a resistance is small even when information is repeatedly rewritten, and data can be read stably as a result.

Abstract: An optical semiconductor includes a first semiconductor layer and at least one reflective element that is formed on the semiconductor layer. The at least one reflective element comprises alternating layers of high and low index layers. A crystalline semiconductor layer is formed on the at least one reflective element.

Abstract: Gallium nitride material-based semiconductor structures are provided. In some embodiments, the structures include a composite substrate over which a gallium nitride material region is formed. The gallium nitride material structures may include additional features, such as strain-absorbing layers and/or transition layers, which also promote favorable stress conditions. The reduction in stresses may reduce defect formation and cracking in the gallium nitride material region, as well as reducing warpage of the overall structure. The gallium nitride material-based semiconductor structures may be used in a variety of applications such as transistors (e.g. FETs) Schottky diodes, light emitting diodes, laser diodes, SAW devices, and sensors, amongst others devices.

Abstract: The present invention provides for nanostructures grown on a conducting or insulating substrate, and a method of making the same. The nanostructures grown according to the claimed method are suitable for interconnects and/or as heat dissipators in electronic devices.

Abstract: The semiconductor device according to an aspect of the invention includes: an internal circuit area having an internal circuit; an I/O circuit area positioned outside the internal circuit area; and an electrode pad placed across an outer edge of the I/O circuit area. In the electrode pad, an area outside the outer edge of the I/O circuit area is a bonding area, and an area inside the outer edge is a probe area.

Abstract: A field effect transistor (FET) includes a semiconductor region of a first conductivity type and a well region of a second conductivity type extending over the semiconductor region. A gate electrode is adjacent to but insulated from the well region, and a source region of the first conductivity type is in the well region. A heavy body region is in electrical contact with the well region, and includes a material having a lower energy gap than the well region.

Abstract: In a photoelectric conversion device, in a contact between a p-type semiconductor 3a and an electrode 2, an n-type semiconductor 6 of a conductivity type opposite to that of the p-type semiconductor is provided between the p-type semiconductor 3a and the electrode 2. The existence of the n-type semiconductor 6 allows a recombination rate of photo-generated carriers excited by incident light to be effectively reduced, and allows a dark current component to be effectively prevented from being produced. Therefore, it is possible to improve photoelectric conversion efficiency as well as to stabilize characteristics. Further, a tunnel junction is realized by increasing the concentration of a doping element in at least one or preferably both of the p-type semiconductor 3a and the n-type semiconductor 6 in a region where they are in contact with each other, thereby keeping ohmic characteristics between the semiconductor and the electrode good.

Abstract: A light source is provided including an LED component having an emitting surface, which may include: i) an LED capable of emitting light at a first wavelength; and ii) a re-emitting semiconductor construction which includes a second potential well not located within a pn junction having an emitting surface; or which may alternately include a first potential well located within a pn junction and a second potential well not located within a pn junction; and which additionally includes a converging optical element.

Abstract: A spin coherent, single photon detector has a body of semiconductor material with a quantum well region formed in barrier material in the body. The body has a first electrode forming an isolation electrode for defining, when negatively energized, an extent of the quantum well in the body and a second electrode positioned above a location where an electrostatic quantum dot is defined in said quantum well when positively energized. The quantum well occurs in three layers of material: a central quantum well layer and two outer quantum well layers, the two outer quantum well layers having a relatively low conduction band minimum and the barrier having a relatively high conduction band minimum while the central quantum well layer having a conduction band minimum between the relatively high and relatively low conduction band minimums.

Abstract: A semiconductor device comprises a glass substrate serving as a substrate having an insulated surface and a silicon layer located on a position overlapping with this glass substrate. The silicon layer includes an amorphous gettering region. Preferably, the silicon layer includes a main region serving as an active element region, and the gettering region is preferably included in the remaining portion of the silicon layer excluding the main region. Preferably, the silicon layer may include a portion serving as an active region of a thin-film transistor.

Abstract: A general, closed, anisotropic kinetic turbulence theory for gases and liquids is based on new solutions of the Maxwell moment equations of the Boltzmann equations. These solutions provide a closed initial equation set for the four time average fluid mechanic variables, the sixteen time average thermal motion correlation and the sixteen time average turbulent motion correlations listed in Table I.

Abstract: Semiconductor quantum well devices and methods of making the same are described. In one aspect, a device includes a quantum well structure that includes semiconductor layers defining interleaved heavy-hole and light-hole valance band quantum wells. Each of the quantum wells includes a quantum well layer interposed between barrier layers. One of the semiconductor layers that functions as a barrier layer of one of the light-hole quantum wells also functions as the quantum well layer of one of the heavy-hole quantum wells. Another of the semiconductor layers that functions as a barrier layer of one of the heavy-hole quantum wells also functions as the quantum well layer of one of the light-hole quantum wells.

Abstract: A polycrystalline silicon plate has grain boundary lines on a surface thereof, and at least one of the grain boundary lines is a quasi-linear grain boundary line. The silicon plate is used to produce a solar cell. The silicon plate is formed using a base substrate having an irregular surface provided with dotted or linear protrusions, which makes it possible to control the grain boundary lines. As such, an inexpensive and high-quality silicon plate can be provided. Further, by employing this silicon plate to produce a solar cell, an inexpensive and high-quality solar cell can be provided as well.

Abstract: Disclosed is a natural-superlattice homologous single-crystal thin film, which includes a complex oxide which is epitaxially grown on either one of a ZnO epitaxial thin film formed on a single-crystal substrate, the single-crystal substrate after disappearance of the ZnO epitaxial thin film and a ZnO single crystal. The complex oxide is expressed by the formula: M1M2O3 (ZnO)m, wherein M1 is at least one selected from the group consisting of Ga, Fe, Sc, In, Lu, Yb, Tm, Er, Ho and Y, M2 is at least one selected from the group consisting of Mn, Fe, Ga, In and Al, and m is a natural number of 1 or more. A natural-superlattice homologous single-crystal thin film formed by depositing the complex oxide and subjecting the obtained layered film to a thermal anneal treatment can be used in optimal devices, electronic devices and X-ray optical devices.

Abstract: A super-lattice thermoelectric device. The device includes p-legs and n-legs, each leg having a large number of alternating layers of two materials with differing electron band gaps. The n-legs in the device are comprised of alternating layers of silicon and silicon germanium. The p-legs includes alternating layers of B4C and B9C. In preferred embodiments the layers are about 100 angstroms thick. Applicants have fabricated and tested a first Si/SiGe (n-leg) and B4C/B9C (p-leg) quantum well thermocouple. Each leg was only 11 microns thick on a 5 micron Si substrate. Nevertheless, in actual tests the thermocouple operated with an amazing efficiency of 14 percent with a Th of 250 degrees C. Thermoelectric modules made according to the present invention are useful for both cooling applications as well as electric power generation. This preferred embodiment is a thermoelectric 10×10 egg crate type module about 6 cm×6 cm×0.

Abstract: An InGaAlAs-based buried type laser is expected to improve properties of the device, but generates defects at a re-growth interface and is difficult to realize a long-term reliability necessary for optical communication, due to inclusion of Al in an active layer. A semiconductor optical device and an optical module including a package substrate and a semiconductor optical device mounted on the package substrate are provided, whereby there are realized the improvement of device properties and the long-term reliability through the use of an Al composition ratio-reduced tensile strained quantum well layer.

Abstract: A Group-III nitride semiconductor device including a crystal substrate, an electrically conducting Group-III nitride semiconductor (AlXGaYIn1?(X+Y)N: 0?X<1, 0<Y?1 and 0<X+Y?1) crystal layer vapor-phase grown on the crystal substrate, an ohmic electrode and an electrically conducting boron phosphide crystal layer provided between the ohmic electrode and the Group-III nitride semiconductor crystal layer, the ohmic electrode being disposed in contact with the boron phosphide crystal layer. Also disclosed is a method for producing the Group-III nitride semiconductor device, and a light-emitting diode including the Group-III nitride semiconductor device.

Abstract: A board for an electronic device is provide comprising a substrate having an amorphous layer, a buffer layer formed on the amorphous layer, the buffer layer having an orientation at least in the direction of its thickness, and a conductive oxide layer formed on the buffer layer by means of epitaxial growth, the conductive oxide layer having a metal oxide of a perovskite structure. The buffer layer contains at least one of the group consisting of a metal oxide of a NaCl structure and a metal oxide of a fluorite structure. Furthermore, the buffer layer 12 is formed by epitaxial growth in the cubic crystal (100) orientation.

Abstract: Alloy memory structures and methods are disclosed wherein a layer or volume of alloy material changes conductivity subsequent to introduction of a electron beam current-induced change in phase of the alloy, the conductivity change being detected using current detection means such as photon-emitting P-N junctions, and being associated with a change in data bit memory state.

Abstract: An array of multi-state, multi-layer magnetic memory devices (10) wherein each memory device comprises a nonmagnetic spacer region (22) and a free magnetic region (24) positioned adjacent to a surface of the nonmagnetic spacer region, the free magnetic region including a plurality of magnetic layers (36,34,38), wherein the magnetic layer (36) in the plurality of magnetic layers positioned adjacent to the surface of the nonmagnetic spacer region has a thickness substantially greater than a thickness of each of the magnetic layers (34,38) subsequently grown thereon wherein the thickness is chosen to improve the magnetic switching variation so that the magnetic switching field for each memory device in the array of memory devices is more uniform.

Abstract: A pre-metal dielectric structure of a SONOS memory structure includes a UV light-absorbing film, which prevents the ONO structure from being electronically charged in response to UV irradiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer located over the SONOS memory structure, a light-absorbing structure located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the light-absorbing structure. The light-absorbing structure can be a continuous polysilicon or amorphous silicon layer. Alternately, the light-absorbing structure can include one or more patterned polysilicon layers. In another embodiment, the SONOS transistors include UV light absorbing polysilicon spacers.

Abstract: A semiconductor component for generating a polychromatic electromagnetic radiation has a semiconductor chip with a first semiconductor layer and a second semiconductor layer, which is provided adjacent to the first semiconductor layer and has an electroluminescent region. The electroluminescent region emits electromagnetic radiation of a first wavelength. The first semiconductor layer includes a material which, when excited with the electromagnetic radiation of the first wavelength, re-emits radiation with a second wavelength which is longer than the first wavelength.

Abstract: A method for fabricating a p-n heterojunction device is provided, the device being preferably comprised of an n-type GaN layer co-doped with silicon and zinc and a p-type AlGaN layer. The device may also include a p-type GaN capping layer. The device can be grown on any of a variety of different base substrates, the base substrate comprised of either a single substrate or a single substrate and an intermediary layer. The device can be grown directly onto the surface of the substrate without the inclusion of a low temperature buffer layer.

Abstract: A practically realizable semiconductor magnetic body having a flat-band structure is disclosed. The semiconductor magnetic body is formed by semiconductor quantum dots arranged on lattice points such that electrons can transfer between neighboring quantum dots and the electron energy band contains a flat-band structure, where each quantum dot is a structure in which electrons are confined inside a region which is surrounded by high energy potential regions, and the flat-band structure is a band structure in which energy dispersion of electrons has hardly any wave number dependency.