Of Amorphous Semiconductor Material Patents (Class 257/16)
  • Patent number: 6858863
    Abstract: A semiconductor laser device includes a resonant cavity formed on a GaAs substrate, the resonant cavity including a quantum well (QW) active layer structure having a GaInNAs(Sb) well layer and a pair of barrier layers. The QW structure has a conduction band offset energy (?Ec) equal to or higher than 350 milli-electron-volts (meV) between the well layer and the barrier layers, and each of the barrier layers a tensile strain equal to or lower than 2.5%.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: February 22, 2005
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Hitoshi Shimizu, Kouji Kumada, Norihiro Iwai
  • Patent number: 6855992
    Abstract: A semiconductor structure includes a monocrystalline silicon substrate, an amorphous oxide material overlying the monocrystalline silicon substrate, a monocrystalline perovskite oxide material overlying the amorphous oxide material, and a monocrystalline compound semiconductor material overlying the monocrystalline perovskite oxide material. A composite transistor includes a first transistor having first active regions formed in the monocrystalline silicon substrate, a second transistor having second active regions formed in the monocrystalline compound semiconductor material, and a mode control terminal for controlling the first transistor and the second transistor.
    Type: Grant
    Filed: July 24, 2001
    Date of Patent: February 15, 2005
    Assignee: Motorola Inc.
    Inventors: Rudy M. Emrick, Bruce Allen Bosco, John E. Holmes, Steven James Franson, Stephen Kent Rockwell
  • Patent number: 6828579
    Abstract: A superlattice thermoelectric device. The device includes p-legs and n-legs, each leg includes a large number of at least two different very thin alternating layers of elements. The n-legs in the device includes alternating layers of silicon and silicon carbide. In preferred embodiments p-legs include a superlatice of B-C layers, with alternating layers of different stoichiometric forms of B-C. This preferred embodiment is designed to produce 20 Watts with a temperature difference of 300 degrees C. with a module efficiency of about 30 percent. The module is about 1 cm thick with a cross section area of about 7 cm2 and has about 10,000 sets of n and p legs each set of legs being about 55 microns thick and having about 5,000 very thin layers (each layer about 10 nm thick).
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: December 7, 2004
    Assignee: Hi-Z Technology, Inc.
    Inventors: Saied Ghamaty, Norbert B. Elsner
  • Patent number: 6818966
    Abstract: A method and structure for controlling the surface properties in the dielectric layers in a thin film component can be provided for improving the trimming process of thin film element. A metal fill is configured with a uniform fill pattern beneath an array of thin film resistors, and can comprise a plurality of smaller features or peaks providing a finer fill pattern that improves the control of the topology of the dielectric layers. The fill pattern can be configured in various manners, such as fill patterns parallel to the thin film resistor, fill patterns perpendicular to the thin film resistor, or fill patterns comprising a checkerboard-like configuration.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: November 16, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Eric W. Beach, Walter B. Meinel, Eric L. Hoyt
  • Patent number: 6756649
    Abstract: A modulator includes a voltage source, a first arrangement including first and second non-insulating layers configured such that a modulation voltage from the voltage source can be applied there across, and a second arrangement between the first and second non-insulating layers. The second arrangement includes a first amorphous layer configured such that a transport of electrons between the first and second non-insulating layers includes tunneling. The first arrangement further includes an antenna structure for absorbing part of an input radiation, while a remainder of the input radiation is reflected. The second arrangement cooperates with the first arrangement such that the antenna exhibits a first absorptivity, when a first modulation voltage is applied to the first arrangement, and exhibits a distinct, second absorptivity, when a second modulation voltage is applied, thereby causing the antenna to reflect a different amount of input radiation to an output as modulated radiation.
    Type: Grant
    Filed: January 20, 2003
    Date of Patent: June 29, 2004
    Assignee: The Regents of the University of Colorado
    Inventors: Garret Moddel, Blake J. Eliasson
  • Patent number: 6713819
    Abstract: An integrated circuit formed in semiconductor-on-insulator format. The integrated circuit includes a layer of semiconductor material disposed on an insulating layer, where the insulating layer disposed on a substrate. A first and a second MOSFET are provided such that one of a source and a drain of the first MOSFET is disposed adjacent one of a source and a drain of the second MOSFET. An amorphous region is formed in the layer of semiconductor material and extending from an upper surface of the layer of semiconductor material to the isolation layer. The amorphous region is formed between a crystalline portion of the one of the source and the drain of the first MOSFET and a crystalline portion of the one of the source and the drain of the second MOSFET.
    Type: Grant
    Filed: April 8, 2002
    Date of Patent: March 30, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: William G. En, Dong-Hyuk Ju, Srinath Krishnan
  • Patent number: 6710382
    Abstract: A silicon germanium layer is deposited over a semiconductor substrate with a gate insulating film interposed between the substrate and the silicon germanium layer. Then, an upper silicon layer in an amorphous state is deposited on the silicon germanium layer. Thereafter, a gate electrode is formed by patterning the silicon germanium layer and the upper silicon layer.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: March 23, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroko Kubo, Kenji Yoneda
  • Patent number: 6630691
    Abstract: The present invention provides an LED device comprising a phosphor-converting substrate that converts primary light emitted by the LED, which is blue light, into one or more other wavelengths of light, which then combine with unconverted primary light to produce white light. The substrate is a single crystal phosphor having desired luminescent properties. The single crystal phosphor has the necessary lattice structure to promote single crystalline growth of the light-emitting structure of the LED device. Moreover, the thermo-mechanical properties of the substrate are such that the introduction of excessive strain or cracks in the epitaxial films of the LED device is prevented. The characteristics of the substrate, i.e., the dopant concentration and thickness, are capable of being precisely controlled and tested before the LED device is fabricated so that the fraction of primary light that passes through the substrate without being converted is predictable and controllable.
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: October 7, 2003
    Assignee: Lumileds Lighting U.S., LLC
    Inventors: Regina B. Mueller-Mach, Gerd O. Mueller, David A. Vanderwater
  • Patent number: 6621096
    Abstract: A device isolation process flow for an atomic resolution storage (ARS) system inserts device isolation into a process flow of the ARS system so that diodes may be electrically insulated from one another to improve signal to noise ratio. In addition, since most harsh processing is done prior to depositing a phase change layer, which stores data bits, process damage to the phase change layer may be minimized.
    Type: Grant
    Filed: May 21, 2001
    Date of Patent: September 16, 2003
    Assignee: Hewlett-Packard Develpoment Company, L.P.
    Inventors: Heon Lee, Chung-Ching Yang, Peter Hartwell
  • Patent number: 6573528
    Abstract: This patent is generally directed towards a method and device for providing a diode structure that has a barrier height that may be readily engineered with a series resistance that may be independently varied while simultaneously providing for the complete characterization and discernment of the barrier height in a microwave and millimeter-wave rectifying diode without the need for device fabrication and electrical measurement. The present invention generally relates to microwave and millimeterwave diodes, and more particularly to low barrier structures within these diodes that are capable of rectification of microwave and millimeterwave radiation.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: June 3, 2003
    Inventor: Walter David Braddock
  • Patent number: 6559469
    Abstract: An integrated circuit includes a layered superlattice material having the formula A1w1+a1A2w2+a2 . . . Ajwj+ajS1x1+s1S2x2+s2 . . . Skxk+skB1y1+b1B2y2+b2 . . . Blyl+blQz−q, where A1, A2 . . . Aj represent A-site elements in a perovskite-like structure, S1, S2 . . . Sk represent superlattice generator elements, B1, B2 . . . B1 represent B-site elements in a perovskite-like structure, Q represents an anion, the superscripts indicate the valences of the respective elements, the subscripts indicate the number of atoms of the element in the unit cell, and at least w1 and y1 are non-zero. Some of these materials are extremely low fatigue ferroelectrics and are applied in ferroelectric FETs in non-volatile memories. Others are high dielectric constant materials that do not degrade or break down over long periods of use and are applied as the gate insulator in volatile memories.
    Type: Grant
    Filed: October 11, 2000
    Date of Patent: May 6, 2003
    Assignee: Symetrix Corporation
    Inventors: Carlos A. Paz de Araujo, Larry D. McMillan, Vikram Joshi, Narayan Solayappan, Joseph D. Cuchiaro
  • Patent number: 6559467
    Abstract: A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis. The quantum dot layer is preferably comprised of AlxByInzGa1-x-y-zN, InGaN1-a-bPaAsb, or AlxByInzGa1-x-y-zN1-a-bPaAsb.
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: May 6, 2003
    Assignee: Technologies and Devices International, Inc.
    Inventors: Audrey E. Nikolaev, Yuri V. Melnik, Konstantin V. Vassilevski, Vladimir A. Dmitriev
  • Patent number: 6489041
    Abstract: A practically realizable semiconductor magnetic body having a flat-band structure is disclosed. The semiconductor magnetic body is formed by semiconductor quantum dots arranged on lattice points such that electrons can transfer between neighboring quantum dots and the electron energy band contains a flat-band structure, where each quantum dot is a structure in which electrons are confined inside a region which is surrounded by high energy potential regions, and the flat-band structure is a band structure in which energy dispersion of electrons has hardly any wave number dependency.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: December 3, 2002
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Hiroyuki Tamura, Kenji Shiraishi, Hideaki Takayanagi
  • Publication number: 20020153522
    Abstract: The present invention relates to a light-emitting device utilizing amorphous silicon quantum dot nanostructures, wherein the light-emitting device can be fabricated using the existing silicon semiconductor fabrication technology, is excellent in light-emitting efficiency, and can emit light in the visible region including short wavelength region such as green and blue.
    Type: Application
    Filed: April 18, 2001
    Publication date: October 24, 2002
    Applicant: Kwangju Institute of Science and Technology
    Inventors: Nae Man Park, Tae Soo Kim, Seong Ju Park
  • Patent number: 6369405
    Abstract: A method of making semiconductor quantum wires employs a semiconductor wafer (14) as starting material. The wafer (14) is weakly doped p type with a shallow heavily doped p layer therein for current flow uniformity purposes. The wafer (14) is anodised in 20% aqueous hydrofluoric acid to produce a layer (5) microns thick with 70% porosity and good crystallinity. The layer is subsequently etched in concentrated hydrofluoric acid, which provides a slow etch rate. The etch increases porosity to a level in the region of 80% or above. At such a level, pores overlap and isolated quantum wires are expected to form with diameters less than or equal to 3 nm. The etched layer exhibits photoluminescence emission at photon energies well above the silicon bandgap (1.1 eV) and extending into the red region (1.6-2.0 eV) of the visible spectrum.
    Type: Grant
    Filed: April 26, 1994
    Date of Patent: April 9, 2002
    Assignee: The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Northern Ireland
    Inventors: Leigh-Trevor Canham, John Michael Keen, Weng Yee Leong
  • Publication number: 20010050363
    Abstract: In the case where a Ta2O5 thin film having double bond Ta═O is employed for a capacitative insulating film, Rapid Thermal Anneal in oxygen and UV/O3 treatment are executed at suitable temperature and in suitable time. Whether or not absorption peak which appears in 2340 cm−1 exists and whether it is large or small are monitored by measuring a transmission infrared absorption spectrum of a Ta2O5 thin film with Fourier Transform Infrared Spectroscopy. In the case where a Ta2O5 thin film, in which an abundance ratio of oxygen in a three coordinate bonding state is large, is employed for a capacitative insulating film, an intensity ratio of each double peak which appears in 510 cm−1 and 570 cm−1 is measured as well, so that the film whose ratio (510/570) is larger than another one is used as an character to improve quality of a film.
    Type: Application
    Filed: June 6, 2001
    Publication date: December 13, 2001
    Applicant: NEC Corporation
    Inventor: Haruhiko Ono
  • Patent number: 6259116
    Abstract: A semiconductor memory device using silicon-rich amorphous silicon alloy material memory elements that are electrically programmable by means of current induced conductivity comprises a layer (10) of the alloy material on opposing sides of which sets of input and output contacts (16, 18) are provided, and discrete conductive elements (20) within the layer which serve as nodes and define programmable conductive paths between input and output contacts to create a three dimensional memory network. The conductive elements can be arranged at one or more levels within the thickness of the alloy layer and preferably are of defined shape forming a predetermined 2D array at each level.
    Type: Grant
    Filed: October 22, 1998
    Date of Patent: July 10, 2001
    Assignee: U.S. Philips Corporation
    Inventor: John M. Shannon
  • Patent number: 5847418
    Abstract: Described is a semiconductor photo detector comprising, between a lower electrode and an upper electrode, an optical absorption layer which generates photo carriers, receiving light and an amplification layer which amplifies the photo carriers so generated. In the semiconductor photo detector, the amplification layer is formed of a well layer which causes an avalanche phenomenon and a barrier layer which has a band gap larger than that of the optical absorption layer. The well layer is formed of a crystal substance, by which at the interface with the barrier layer, the energy value of the conduction band of the photo carriers in the well layer is lower than that in the barrier layer and at the same time, the difference in the energy value of the conduction band between the well layer and the barrier layer is larger than the band gap between the valence band and the conduction band of the well layer.
    Type: Grant
    Filed: October 30, 1996
    Date of Patent: December 8, 1998
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Takeshi Nakamura, Shinya Kyozuka, Takayuki Yamada, Yasuaki Miyamoto
  • Patent number: 5783838
    Abstract: Described is a semiconductor photo detector comprising, between two electrodes, at least one of said electrodes being a transparent electrode, an optical absorption layer which is composed of a non-single crystalline material, absorbs light and generates photo carriers and a carrier multiplication layer which is composed of a non-single crystalline material and multiplies the photo carriers generated by the optical absorption layer. The carrier multiplication layer is formed of a multilayer film obtained by stacking films each having plural layers which are composed of non-single crystalline Zn.sub.x Cd.sub.1-x M (0.ltoreq.x.ltoreq.1, M represents one selected from the group consisting of S, Se and Te) and are different in a composition ratio in accordance with a change in the value of x in said Zn.sub.x Cd.sub.1-x M, whereby a band discontinuity .DELTA.Ec of the conduction band can be made larger, an ionization rate of electrons can be heightened and the place where ionization occurs can be specified.
    Type: Grant
    Filed: October 30, 1996
    Date of Patent: July 21, 1998
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Shinya Kyozuka, Takeshi Nakamura, Takayuki Yamada, Yasuaki Miyamoto
  • Patent number: 5686734
    Abstract: A high performance thin film semiconductor device having a heterojunction such as a photoelectric conversion device is disclosed. In accordance with the present invention, the thin film semiconductor device comprises a thin semiconductor layer which forms a heterojunction with a non-single crystal silicon layer or non-single crystal silicon-germanium layer, wherein the valence band discontinuity at the heterointerface arising from the difference in optical energy bandgap is as small as 0.3 eV or less and wherein the thin semiconductor layer has an optical energy bandgap greater than 2.8 eV, so that hole transport performance may not be degraded. Such a thin semiconductor layer may be formed by using silane gas and methane gas with a flow rate ratio greater than 30 at a deposition rate less than 0.5 .ANG./sec.
    Type: Grant
    Filed: July 14, 1995
    Date of Patent: November 11, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshihiro Hamakawa, Shigetoshi Sugawa, Tadashi Atoji, Hiroaki Okamoto
  • Patent number: 5646418
    Abstract: A quantum effect switching device comprising a substrate 12, first and second tunnel barriers 14 and 18, and a quantum well 16. The current between a drain region 20 and the substrate 12 can be switched by placing a potential on a gate layer 24. The potential on the gate layer 24 selectively modulates the effective dimensions of the quantum well 16 to alter the allowed energy levels within the conduction band of the quantum well 16.
    Type: Grant
    Filed: August 24, 1992
    Date of Patent: July 8, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Gary A. Frazier, James H. Luscombe
  • Patent number: 5534111
    Abstract: A thermal isolation microstructure fabricated by a process which allows the ultra thinning of support legs for the microdetector.
    Type: Grant
    Filed: February 29, 1988
    Date of Patent: July 9, 1996
    Assignee: Honeywell Inc.
    Inventors: G. Benjamin Hocker, James O. Holmen, Robert G. Johnson
  • Patent number: 5496415
    Abstract: A solar cell formed from a semiconductor having a relative wide band-gap E.sub.b- characterized by a multi-quantum well system incorporated in the depletion region of the cell in which the quantum wells comprise regions of semiconductor with a smaller band gap separated by small amounts of the wider band-gap semiconductor (E.sub.b) so that the effective band-gap for absorption (E.sub.a) is less than E.sub.b.
    Type: Grant
    Filed: August 24, 1994
    Date of Patent: March 5, 1996
    Assignee: Imperial College of Science, Technology and Medicine
    Inventor: Keith Barnham
  • Patent number: 5481124
    Abstract: Compatibility of high sensitivity with low remaining images, and low crosstalk can be achieved by a laminated solid-state image pickup device, which includes accumulating portions for accumulating electric signals, reading units for reading the electric signals, connecting members formed in contact with the accumulating portions, and a photoconductive film, and by a method for manufacturing the device. The photoconductive film is made of a non-crystalline semiconductor, and is configured by laminating a carrier multiplication layer, a light absorbing layer, a charge injection inhibiting layer of a second conduction type. Each of the connecting members is made of a semiconductor layer of a first conduction type, intrinsic or having a low impurity density, surrounded by a semiconductor layer of the second conduction type or a conductive material.
    Type: Grant
    Filed: August 10, 1994
    Date of Patent: January 2, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiraku Kozuka, Shigetoshi Sugawa, Hisae Shimizu
  • Patent number: 5453629
    Abstract: A photoelectric conversion device includes a plurality of photoelectric conversion units and a signal output unit. The signal output unit has at least one storage device for storing electrical signals generated by the photoelectric conversion device. A scanning device scans the electrical signals generated by the electric conversion units, and a reading device reads out electrical signals generated by the photoelectric conversion units. Each of the photoelectric conversion units includes a light absorption layer and a multiplication layer. The multiplication layer includes at least one step-back structure which multiplies carriers produced by absorption of light, and in which a forbidden band width changes continuously from a minimum to a maximum width.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: September 26, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventors: Ihachiro Gofuku, Masato Yamanobe, Izumi Tabata, Hiraku Kozuka
  • Patent number: 5452383
    Abstract: An optical switch includes a semiconductor substrate having a surface, a ridge waveguide disposed on the surface of the semiconductor substrate and including an optical waveguide layer having an MQW structure, first and second cladding layers sandwiching the optical waveguide layer, and a switch disposed in a part of the ridge waveguide. A part of the MQW optical waveguide layer included in the switch is thicker than the other part of the optical waveguide layer, whereby the energy band gap of the optical waveguide layer of the switch is smaller than the energy band gap of the other part of the optical waveguide layer and larger than the energy of the signal light. Therefore, the absorption loss of the signal light traveling through the optical waveguide layer is reduced. Furthermore, since the variation in the refractive index of the switch when current is applied to the switch is increased, the ON/OFF ratio of the switch is increased.
    Type: Grant
    Filed: January 28, 1994
    Date of Patent: September 19, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tohru Takiguchi
  • Patent number: 5396082
    Abstract: The semiconductor device has a semiconductor substrate composed essentially of a III-V compound semiconductor containing Ga and As, and a surface layer structure provided on the semiconductor substrate and this layer has a composition different from that of the semiconductor substrate. The surface layer structure includes a strained layer epitaxially grown on the surface of the semiconductor substrate and composed essentially of at least one-element selected from the group consisting of indium, gallium, aluminum and boron, and at least one element selected from the group consisting of arsenic and phosphorus. The strained layer has a composition different from that of the semiconductor substrate The strained layer has a valence band maximum lower in energy than that of the valence band maximum of the semiconductor substrate.
    Type: Grant
    Filed: March 4, 1994
    Date of Patent: March 7, 1995
    Assignee: Nippon Telegraph & Telephone Corporation
    Inventors: Yoshinori Wada, Kazumi Wada, Takahisa Ohno
  • Patent number: 5315128
    Abstract: Described is a resonant-cavity p-i-n photodetector based on the reflection or transmission through a Fabry-Perot cavity incorporating non-epitaxial, amorphous layers with alternating refractive index difference which layers are electron-beam deposited on a light-gathering side of a commercially available photodetector. The materials of the Fabry-Perot cavity are selectable from materials, refractive indices of which fall within a large range (from n=1.26 for CaF.sub.2 to n=3.5 for Si) preferably from materials which are depositable in an amorphous state. The material combinations are selected so that only wavelengths resonant with the cavity mode will be detected. The microcavity of the RC-PIN design can also be deposited on any existing detector structure, without modification of semiconductor growth. Such a photodetector would be useful for wavelength de-multiplexing applications.
    Type: Grant
    Filed: April 30, 1993
    Date of Patent: May 24, 1994
    Assignee: AT&T Bell Laboratories
    Inventors: Neil E. J. Hunt, Erdmann F. Schubert, George J. Zydzik
  • Patent number: 5294820
    Abstract: A field-effect transistor comprising a semiconductor substrate having source and drain regions and a gate electrode, wherein a thin organic film including donor and acceptor molecules is provided between the semiconductor substrate and the gate electrode. When a predetermined voltage is applied to the gate electrode, charge transfer occurs between the donor and acceptor molecules included in the thin organic film, thereby controlling the surface potential of the semiconductor substrate.
    Type: Grant
    Filed: February 7, 1992
    Date of Patent: March 15, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuhiro Gemma, Koichi Mizushima, Akira Miura, Makoto Azuma, Toshio Nakayama
  • Patent number: 5206523
    Abstract: A process is disclosed for producing microporous crystalline silicon which has a band-gap substantially increased relative to that of normal crystalline silicon. This process involves the preparation of quantum wires of silicon by means of a chemical attack method carried out on silicon that has been doped such that it conducts electricity substantially via the effective transport of electric charge by means of so-called holes. The microporous crystalline silicon thus produced is in the form of a discrete mass having a bulk-like, interconnected crystalline silicon structure of quantum wires whose band-gap is greater than normal crystalline silicon. Because of this increased band-gap this microporous crystalline silicon may be used as an active element in applications such as tandem solar cells.
    Type: Grant
    Filed: August 29, 1991
    Date of Patent: April 27, 1993
    Inventors: Ulrich M. Goesele, Volker E. Lehmann
  • Patent number: 5164809
    Abstract: Hydrogenated amorphous silicon radiation detector devices having enhanced signal are disclosed. Specifically provided are transversely oriented electrode layers and layered detector configurations of amorphous silicon, the structure of which allow high electric fields upon application of a bias thereby beneficially resulting in a reduction in noise from contact injection and an increase in signal including avalanche multiplication and gain of the signal produced by incoming high energy radiation. These enhanced radiation sensitive devices can be used as measuring and detection means for visible light, low energy photons and high energy ionizing particles such as electrons, x-rays, alpha particles, beta particles and gamma radiation. Particular utility of the device is disclosed for precision powder crystallography and biological identification.
    Type: Grant
    Filed: April 21, 1989
    Date of Patent: November 17, 1992
    Assignee: The Regents of the University of Calif.
    Inventors: Robert A. Street, Victor Perez-Mendez, Selig N. Kaplan
  • Patent number: 4984768
    Abstract: A laterally retractable and longitudinally foldable chair having a plurality of transverse struts connected with a plurality of longitudinal support members to form hingedly connected sub assemblies of a chair frame for supporting an individual. Each strut is provided with adjusting means. Each adjusting means has a locking means associated therewith which allows for selective adjustment of the width of said chair between a retracted, or compact, configuration and an expanded, or in use, configuration. The adjusting means is comprised of a projection and cooperating aperture in each said transverse strut which allows one to releasably lock the chair in the expanded or retracted position as desired. The novel chair further comprises a plurality of hinge members which hingedly connect the longitudinal support members and which allow the individual sub assemblies to be folded upon themselves to futher reduce the collapsed dimensions of the chair.
    Type: Grant
    Filed: October 27, 1989
    Date of Patent: January 15, 1991
    Inventors: Michael A. Kolber, Terri L. Meinking
  • Patent number: 4958885
    Abstract: A high chair has a backrest member and a seat member which constitute a seat section, and a support member which is disposed to overlap the backrest member and which supports the backrest member for vertical slide movement. The support member is fixed in its raised position by a raised position fixing device. In the region where the backrest member and the support member overlap each other, the support member has a through-hole. On the other hand, a plurality of vertically aligned engaging holes are provided in the backrest member at positions where they can be opposed to the through-hole. A lock pin is inserted into the through-hole and one of the engaging holes, thereby fixing the height of the backrest member.
    Type: Grant
    Filed: June 30, 1986
    Date of Patent: September 25, 1990
    Assignee: Aprica Kassai Kabushikikaisha
    Inventor: Kenzou Kassai