Lateral Structure Patents (Class 257/162)
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Patent number: 11876088Abstract: An integrated circuit (IC) structure includes a continuous well including first through third well portions. The continuous well is one of an n-well or a p-well, the first well portion extends in a first direction, the second well portion extends from the first well portion in a second direction perpendicular to the first direction, and the third well portion extends from the first well portion in the second direction parallel to the second well portion.Type: GrantFiled: November 16, 2021Date of Patent: January 16, 2024Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITED, TSMC CHINA COMPANY, LIMITEDInventors: Yang Zhou, Liu Han, Qingchao Meng, XinYong Wang, ZeJian Cai
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Patent number: 10879782Abstract: The semiconductor device is provided with a plurality of switching elements connected in parallel to each other, and a plurality of recirculation element connected in parallel to the aforementioned plurality of switching elements. An emitter electrode serves as a reference potential of the aforementioned plurality of switching elements and an anode electrode serves as a reference potential of the aforementioned plurality of recirculation elements are electrically connected by the same plate-like member consisting of a conductive material. The aforementioned switching elements and the aforementioned recirculation elements which are connected in parallel on the lowest potential side are constituted so that the distance from the emitter terminal connected to the aforementioned emitter electrode to the aforementioned recirculation element becomes no greater than the distance from the aforementioned emitter terminal.Type: GrantFiled: August 2, 2017Date of Patent: December 29, 2020Assignee: DENSO CORPORATIONInventors: Yuu Yamahira, Tetsuya Matsuoka
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Patent number: 10026833Abstract: To provide a semiconductor device with a high degree of flatness, provided is a semiconductor device including a semiconductor substrate; an element insulating film that is formed on a front surface side of the semiconductor substrate and includes a groove; and a semiconductor element provided in the groove of the element insulating film. The semiconductor device further comprises a withstand voltage structure farther to the outside than the active region, the withstand voltage structure includes a field insulating film formed on the front surface of the semiconductor substrate, and film thickness of a region of the element insulating film where the groove is not provided is the same as film thickness of the field insulating film.Type: GrantFiled: December 26, 2016Date of Patent: July 17, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventor: Hiroyuki Tanaka
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Patent number: 9647100Abstract: A semiconductor device includes transistor cells formed along a first surface at a front side of a semiconductor body in a transistor cell area. A drift zone structure forms first pn junctions with body zones of the transistor cells. An auxiliary structure between the drift zone structure and a second surface at a rear side of the semiconductor body includes a first portion that contains deep level dopants requiring at least 150 meV to ionize. A collector structure directly adjoins the auxiliary structure. An injection efficiency of minority carriers from the collector structure into the drift zone structure varies along a direction parallel to the first surface at least in the transistor cell area.Type: GrantFiled: October 20, 2015Date of Patent: May 9, 2017Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Christian Jaeger, Franz Josef Niedernostheide, Roman Baburske, Andre Rainer Stegner, Antonio Vellei
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Patent number: 9590578Abstract: An amplifier device with at least one microwave tube, intended to be mounted on a satellite, includes a high voltage section directly connected to said microwave tube or tubes, a low voltage section, and a low voltage cabling assembly provided with low voltage connectors at the ends thereof connecting said low and high voltage sections.Type: GrantFiled: July 2, 2015Date of Patent: March 7, 2017Assignee: ThalesInventors: Christophe Balayer, Bruno Trancart
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Patent number: 9525077Abstract: A vertically oriented BARITT diode is formed in an integrated circuit. The BARITT diode has a source proximate to the top surface of the substrate of the integrated circuit, a drift region immediately below the source in the semiconductor material of the substrate, and a collector in the semiconductor material of the substrate immediately below the drift region. A dielectric isolation structure laterally surrounds the drift region, extending from the source to the collector. The source may optionally include a silicon germanium layer or may optionally include a schottky barrier contact.Type: GrantFiled: November 4, 2015Date of Patent: December 20, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiaochuan Bi, Tracey L Krakowski, Suman Banerjee
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Patent number: 9330961Abstract: Protection device structures and related fabrication methods and devices are provided. An exemplary device includes a first interface, a second interface, a first protection circuitry arrangement coupled to the first interface, and a second protection circuitry arrangement coupled between the first protection circuitry arrangement and the second interface. The second protection circuitry arrangement includes a first transistor and a diode coupled to the first transistor, wherein the first transistor and the diode are configured electrically in series between the first protection circuitry arrangement and the second interface.Type: GrantFiled: September 23, 2013Date of Patent: May 3, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Weize Chen, Patrice M. Parris
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Patent number: 9178025Abstract: A solution for designing a semiconductor device, in which two or more attributes of a pair of electrodes are determined to, for example, minimize resistance between the electrodes, is provided. Each electrode can include a current feeding contact from which multiple fingers extend, which are interdigitated with the fingers of the other electrode in an alternating pattern. The attributes can include a target depth of each finger, a target effective width of each pair of adjacent fingers, and/or one or more target attributes of the current feeding contacts. Subsequently, the device and/or a circuit including the device can be fabricated.Type: GrantFiled: September 29, 2014Date of Patent: November 3, 2015Assignee: Sensor Electronic Technology, Inc.Inventors: Grigory Simin, Michael Shur, Remigijus Gaska
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Patent number: 9035352Abstract: A LSCR includes a substrate having a semiconductor surface which is p-doped. A first nwell and a second nwell spaced apart from one another are in the semiconductor surface by a lateral spacing distance. A first n+ diffusion region and a first p+ diffusion region are in the first nwell. A second n+ diffusion region is in the second nwell. A second p+ diffusion is between the first nwell and second nwell which provides a contact to the semiconductor surface. Dielectric isolation is between the first n+ diffusion region and first p+ diffusion region, along a periphery between the first nwell and the semiconductor surface, and along a periphery between the second nwell and the semiconductor surface. A resistor provides coupling between the second n+ diffusion region and second p+ diffusion.Type: GrantFiled: April 30, 2012Date of Patent: May 19, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Gianluca Boselli, Rajkumar Sankaralingam
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Publication number: 20150115317Abstract: Apparatus and methods for precision mixed-signal electronic circuit protection are provided. In one embodiment, an apparatus includes a p-well, an n-well, a poly-active diode structure, a p-type active region, and an n-type active region. The poly-active diode structure is formed over the n-well, the p-type active region is formed in the n-well on a first side of the poly-active diode structure, and the n-type active region is formed along a boundary of the p-well and the n-well on a second side of the poly-active diode structure. During a transient electrical event the apparatus is configured to provide conduction paths through and underneath the poly-active diode structure to facilitate injection of carriers in the n-type active region. The protection device can further include another poly-active diode structure formed over the p-well to further enhance carrier injection into the n-type active region.Type: ApplicationFiled: January 9, 2015Publication date: April 30, 2015Inventors: Javier Alejandro Salcedo, Srivatsan Parthasarathy
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Patent number: 9006863Abstract: A diode string voltage adapter includes diodes formed in a substrate of a first conductive type. Each diode includes a deep well region of a second conductive type formed in the substrate. A first well region of the first conductive type formed on the deep well region. A first heavily doped region of the first conductive type formed on the first well region. A second heavily doped region of the second conductive type formed on the first well region. The diodes are serially coupled to each other. A first heavily doped region of a beginning diode is coupled to a first voltage. A second heavily doped region of each diode is coupled to a first heavily doped region of a next diode. A second heavily doped region of an ending diode provides a second voltage. The deep well region is configured to be electrically floated.Type: GrantFiled: December 23, 2011Date of Patent: April 14, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Peng Hsieh, Jaw-Juinn Horng
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Patent number: 8952418Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.Type: GrantFiled: March 1, 2011Date of Patent: February 10, 2015Assignee: Micron Technology, Inc.Inventors: Rajesh N. Gupta, Farid Nemati, Scott T. Robins
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Patent number: 8933531Abstract: A semiconductor device including a base substrate; a semiconductor layer which is disposed on the base substrate and has a 2-Dimensional Electron Gas (2DEG) generated within the semiconductor layer; a plurality of first ohmic electrodes which are disposed on the central region of the semiconductor layer and have island-shaped cross sections; a second ohmic electrode which is disposed on edge regions of the semiconductor layer; and a Schottky electrode part has first bonding portions bonded to the first ohmic electrodes, and a second bonding portion bonded to the semiconductor layer. A depletion region is provided to be spaced apart from the 2DEG when the semiconductor device is driven at an on-voltage and is provided to be expanded to the 2DEG when the semiconductor device is driven at an off-voltage, the depletion region being generated within the semiconductor layer by bonding the semiconductor layer and the second bonding portion.Type: GrantFiled: November 1, 2012Date of Patent: January 13, 2015Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Woo Cul Jeon, Jung Hee Lee, Young Hwan Park, Ki Yeol Park
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Patent number: 8853738Abstract: A power LDMOS device including a substrate, source and drain regions, gates and trench insulating structures is provided. The substrate has a finger tip area, a finger body area and a palm area. The source regions are in the substrate in the finger body area and further extend to the finger tip area. The neighboring source regions in the finger tip area are connected. The outmost two source regions further extend to the palm area and are connected. The drain regions are in the substrate in the finger body area and further extend to the palm area. The neighboring drain regions in the palm area are connected. The source and drain regions are disposed alternately. A gate is disposed between the neighboring source and drain regions. The trench insulating structures are in the substrate in the palm area and respectively surround ends of the drain regions.Type: GrantFiled: June 27, 2011Date of Patent: October 7, 2014Assignee: Episil Technologies Inc.Inventors: Chung-Yeh Lee, Pei-Hsun Wu, Shiang-Wen Huang
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Patent number: 8772836Abstract: To provide a semiconductor device in which a rectifying element capable of reducing a leak current in reverse bias when a high voltage is applied and reducing a forward voltage drop Vf and a transistor element are integrally formed on a single substrate. A semiconductor device has a transistor element and a rectifying element on a single substrate. The transistor element has an active layer formed on the substrate and three electrodes (source electrode, drain electrode, and gate electrode) disposed on the active layer. The rectifying element has an anode electrode disposed on the active layer, a cathode electrode which is the drain electrode, and a first auxiliary electrode between the anode electrode and cathode electrode.Type: GrantFiled: March 8, 2011Date of Patent: July 8, 2014Assignee: Sanken Electric Co., Ltd.Inventor: Osamu Machida
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Patent number: 8742450Abstract: A III-nitride power semiconductor device that includes a plurality of III-nitride heterojunctions.Type: GrantFiled: May 9, 2013Date of Patent: June 3, 2014Assignee: International Rectifier CorporationInventor: Robert Beach
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Patent number: 8710617Abstract: In a region located between a collector electrode and a semiconductor substrate, there are a portion where a hollow region is located and a portion where no hollow region is located. Between the collector electrode and the portion where no hollow region is located in the semiconductor substrate, a floating silicon layer electrically isolated by insulating films is formed.Type: GrantFiled: March 13, 2013Date of Patent: April 29, 2014Assignee: Mitsubishi Electric CorporationInventors: Junichi Yamashita, Tomohide Terashima
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Patent number: 8686505Abstract: A method produces a semiconductor device including a semiconductor body, an electrode thereon, and an insulating structure insulating the electrode from the semiconductor body. The semiconductor body includes a first contact region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, and a second contact region having a higher maximum doping concentration than the drift region. The insulating structure includes a gate dielectric portion forming a first horizontal interface. with the drift region and has a first maximum vertical extension A field dielectric portion forms with the drift region second and third horizontal interfaces arranged below the main surface. A second maximum vertical extension of the field dielectric portion is larger than the first maximum vertical extension. A third maximum vertical extension of the field dielectric portion is larger than the second maximum vertical extension.Type: GrantFiled: July 27, 2012Date of Patent: April 1, 2014Assignee: Infineon Technologies Dresden GmbHInventors: Marc Strasser, Karl-Heinz Gebhardt, Ralf Rudolf, Lincoln O'Riain
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Patent number: 8680573Abstract: Device structures, design structures, and fabrication methods for a silicon controlled rectifier. A well of a first conductivity type is formed in a device region, which may be defined from a device layer of a semiconductor-on-insulator substrate. A doped region of a second conductivity type is formed in the well. A cathode of a silicon controlled rectifier and a cathode of a diode are formed in the device region. The silicon controlled rectifier comprises a first portion of the well and an anode comprised of a first portion of the doped region. The diode comprises a second portion of the well and an anode comprised of a second portion of the doped region.Type: GrantFiled: April 25, 2012Date of Patent: March 25, 2014Assignee: International Business Machines CorporationInventors: James P. Di Sarro, Robert J. Gauthier, Jr., Junjun Li
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Patent number: 8610168Abstract: In a semiconductor device in which an IGBT, a control circuit for the IGBT and so on are formed on an SOI substrate divided by trenches, the invention is directed to providing the IGBT with a higher breakdown voltage, an enhanced turn-off characteristic and so on. An N type epitaxial layer is formed on a dummy semiconductor substrate, a trench is formed in the N type epitaxial layer, an N type buffer layer and then a P type embedded collector layer are formed on the sidewall of the trench and the front surface of the N type epitaxial layer, and the bottom of the trench and the P+ type embedded collector layer are covered by an embedded insulation film. The embedded insulation film is covered by a polysilicon film, and a P type semiconductor substrate is attached to the polysilicon film with an insulation film being interposed therebetween.Type: GrantFiled: May 27, 2011Date of Patent: December 17, 2013Assignee: ON Semiconductor Trading, Ltd.Inventor: Mitsuru Soma
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Publication number: 20130292740Abstract: In a region located between a collector electrode and a semiconductor substrate, there are a portion where a hollow region is located and a portion where no hollow region is located. Between the collector electrode and the portion where no hollow region is located in the semiconductor substrate, a floating silicon layer electrically isolated by insulating films is formed.Type: ApplicationFiled: March 13, 2013Publication date: November 7, 2013Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Junichi YAMASHITA, Tomohide TERASHIMA
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Publication number: 20130285114Abstract: A LSCR includes a substrate having a semiconductor surface which is p-doped. A first nwell and a second nwell spaced apart from one another are in the semiconductor surface by a lateral spacing distance. A first n+ diffusion region and a first p+ diffusion region are in the first nwell. A second n+ diffusion region is in the second nwell. A second p+ diffusion is between the first nwell and second nwell which provides a contact to the semiconductor surface. Dielectric isolation is between the first n+ diffusion region and first p+ diffusion region, along a periphery between the first nwell and the semiconductor surface, and along a periphery between the second nwell and the semiconductor surface. A resistor provides coupling between the second n+ diffusion region and second p+ diffusion.Type: ApplicationFiled: April 30, 2012Publication date: October 31, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: GIANLUCA BOSELLI, RAJKUMAR SANKARALINGAM
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Patent number: 8569843Abstract: A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.Type: GrantFiled: November 29, 2012Date of Patent: October 29, 2013Assignee: Panasonic CorporationInventors: Manabu Yanagihara, Kazushi Nakazawa, Tatsuo Morita, Yasuhiro Uemoto
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Patent number: 8552469Abstract: There is a problem that a reverse off-leak current becomes too large in a Schottky barrier diode. A semiconductor device of the present invention includes P-type first and second anode diffusion layers formed in an N-type epitaxial layer, N-type cathode diffusion layers formed in the epitaxial layer, a P-type third anode diffusion layer formed in the epitaxial layer so as to surround the first and second anode diffusion layers and to extend toward the cathode diffusion layers, and a Schottky barrier metal layer formed on the first and second anode diffusion layers.Type: GrantFiled: September 27, 2007Date of Patent: October 8, 2013Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventors: Shuichi Kikuchi, Shigeaki Okawa, Kiyofumi Nakaya, Shuji Tanaka
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Patent number: 8541812Abstract: A semiconductor device (10) comprising a bipolar transistor and a field effect transistor within a semiconductor body (1) comprising a projecting mesa (5) within which are at least a portion of a collector region (22d and 22e) and a base region (33d) of the bipolar transistor. The bipolar transistor is provided with a first insulating cavity (92) provided in the collector region (22d and 22e). The base region (33d) is narrower in the plane of the substrate than the collector region (22d and 22e) due to a second insulating cavity (94) provided around the base region (33d) and between the collector region (22d and 22e) and the emitter region (4). By blocking diffusion from the base region the first insulating cavity (92) provides a reduction in the base collector capacitance and can be described as defining the base contact.Type: GrantFiled: February 26, 2009Date of Patent: September 24, 2013Assignee: NXP B.V.Inventors: Philippe Meunier-Beillard, Mark C. J. C. M. Kramer, Johannes J. T. M. Donkers, Guillaume Boccardi
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Patent number: 8530979Abstract: Provided is a semiconductor package which includes: a semiconductor substrate; a functional element that is disposed on one surface of the semiconductor substrate; a protection substrate that is disposed in an opposite side of that surface of the semiconductor substrate with a predetermined gap from a surface of the semiconductor substrate; and a junction member that is disposed to surround the functional element and bonds the semiconductor substrate and the protection substrate together, wherein the functional element has a shape different from a shape of a plane surrounded by the junction member in that surface of the semiconductor substrate, or is disposed in a region deviated from a central region of the plane surrounded by the junction member in that surface of the semiconductor substrate.Type: GrantFiled: October 1, 2010Date of Patent: September 10, 2013Assignee: Fujikura Ltd.Inventors: Shingo Ogura, Yuki Suto
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Patent number: 8502268Abstract: A LDMOS structure includes a gate, a source, a drain and a bulk. The gate includes a polycrystalline silicon layer, the source includes a P-implanted layer, the drain includes the P-implanted layer, a P-well layer, and a deep P-well layer. A bulk terminal is connected through the P-implanted layer, the P-well layer, the deep P-well layer, and a P-type buried layer to the bulk. The LDMOS structure is able to be produced without any extra masking step, and it has compact structure, low on-resistance, and is able to withstand high current and high voltage.Type: GrantFiled: August 11, 2011Date of Patent: August 6, 2013Assignee: IPGoal Microelectronics (SiChuan) Co., Ltd.Inventor: Rongwei Yu
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Patent number: 8476675Abstract: A semiconductor device (10) comprising a bipolar transistor and a field 5 effect transistor within a semiconductor body (1) comprising a projecting mesa (5) within which are at least a portion of a collector region (22c and 22d) and a base region (33c) of the bipolar transistor. The bipolar transistor is provided with an insulating cavity (92b) provided in the collector region (22c and 22d). The insulating cavity (92b) may be provided by providing a layer (33a) in the collector region (22c), creating an access path, for example by selectively etching polysilicon towards monocrystalline, and removing a portion of the layer (33a) to provide the cavity using the access path. The layer (33a) provided in the collector region may be of SiGe:C. By blocking diffusion from the base region the insulating cavity (92b) provides a reduction in the base collector capacitance and can be described as defining the base contact.Type: GrantFiled: February 26, 2009Date of Patent: July 2, 2013Assignee: NXP B.V.Inventors: Philippe Meunier-Beillard, Johannes J. T. M. Donkers, Erwin Hijzen
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Patent number: 8441030Abstract: A III-nitride power semiconductor device that includes a plurality of III-nitride heterojunctions.Type: GrantFiled: September 29, 2005Date of Patent: May 14, 2013Assignee: International Rectifier CorporationInventor: Robert Beach
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Patent number: 8426939Abstract: The present invention provides a semiconductor device including: a base substrate; a first semiconductor layer which is disposed on the base substrate and has a front surface and a rear surface opposite to the front surface; first ohmic electrodes disposed on the front surface of the first semiconductor layer; a second ohmic electrode disposed on the rear surface of the first semiconductor layer; a second semiconductor layer interposed between the first semiconductor layer and the first ohmic electrodes; and a Schottky electrode part which covers the first ohmic electrodes on the front surface of the first semiconductor layer.Type: GrantFiled: January 8, 2010Date of Patent: April 23, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Woo Chul Jeon, Jung Hee Lee, Young Hwan Park, Ki Yeol Park
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Patent number: 8390070Abstract: The ESD protection device includes a substrate, a well, a first doped region and a second doped region. The substrate has a first conductive type, and the substrate is electrically connected to a first power node. The well has a second conductive type, and is disposed in the substrate. The first doped region has the first conductive type, and is disposed in the well. The first doped region and the well are electrically connected to a second power node. The second doped region has the second conductive type, and is disposed in the substrate. The second doped region is in a floating state.Type: GrantFiled: April 6, 2011Date of Patent: March 5, 2013Assignee: Nanya Technology Corp.Inventor: Wei-Fan Chen
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Patent number: 8373245Abstract: Disclosed is a semiconductor device including: a base substrate; a semiconductor layer disposed on the base substrate; an ohmic electrode part which has ohmic electrode lines disposed in a first direction, on the semiconductor layer; and a Schottky electrode part which is disposed to be spaced apart from the ohmic electrode lines on the semiconductor layer and includes Schottky electrode lines disposed in the first direction, wherein the Schottky electrode lines and the ohmic electrode lines are alternately disposed in parallel, and the ohmic electrode part further includes first ohmic electrodes covered by the Schottky electrode lines on the semiconductor layer.Type: GrantFiled: January 8, 2010Date of Patent: February 12, 2013Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Woo Chul Jeon, Jung Hee Lee, Young Hwan Park, Ki Yeol Park
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Patent number: 8344463Abstract: A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.Type: GrantFiled: July 10, 2009Date of Patent: January 1, 2013Assignee: Panasonic CorporationInventors: Manabu Yanagihara, Kazushi Nakazawa, Tatsuo Morita, Yasuhiro Uemoto
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Patent number: 8319309Abstract: The present invention provides a semiconductor device including: a base substrate; a semiconductor layer which is disposed on the base substrate and has a 2-Dimensional Electron Gas (2DEG) formed therewithin; a first ohmic electrode disposed on a central region of the semiconductor layer; a second ohmic electrode which is formed on the edge regions of the semiconductor layer in such a manner to be disposed to be spaced apart from the first ohmic electrodes, and have a ring shape surrounding the first ohmic electrode; and a Schottky electrode part which is formed on the central region to cover the first ohmic electrode and is formed to be spaced apart from the second ohmic electrode.Type: GrantFiled: January 8, 2010Date of Patent: November 27, 2012Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Woo Chul Jeon, Jung Hee Lee, Young Hwan Park, Ki Yeol Park
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Patent number: 8212320Abstract: In an ESD clamp formed in a SOI process, voltage tolerance is increased by introducing multiple blocking junctions between the anode and cathode of the device.Type: GrantFiled: March 15, 2006Date of Patent: July 3, 2012Assignee: National Semiconductor CorporationInventors: Vladislav Vashchenko, Peter J. Hopper
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Publication number: 20110147794Abstract: A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a P+-N body diode and an N+-P body diode. The P+-N body diode and the N+-P body diode are laterally integrated.Type: ApplicationFiled: February 25, 2011Publication date: June 23, 2011Applicant: INTERNATIONAL BUSINESS MACHINESInventors: Robert J. GAUTHIER, JR., Junjun LI, Souvick MITRA
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Patent number: 7943957Abstract: A diode 10 comprises an SOI substrate in which are stacked a semiconductor substrate 20, an insulator film 30, and a semiconductor layer 40. A bottom semiconductor region 60, an intermediate semiconductor region 53, and a surface semiconductor region 54 are formed in the semiconductor layer 40. The bottom semiconductor region 60 includes a high concentration of n-type impurity. The intermediate semiconductor region 53 includes a low concentration of n-type impurity. The surface semiconductor region 54 includes p-type impurity.Type: GrantFiled: November 17, 2006Date of Patent: May 17, 2011Assignee: Toyota Jidosha Kabushiki KaishaInventors: Masato Taki, Masahiro Kawakami, Kiyoharu Hayakawa, Masayasu Ishiko
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Patent number: 7910410Abstract: An integrated low leakage Schottky diode has a Schottky barrier junction proximate one side of an MOS gate with one end of a drift region on an opposite side of the gate. Below the Schottky metal and the gate oxide is a RESURF structure of an N? layer over a P? layer which also forms the drift region that ends at the diode's cathode in one embodiment of the present invention. The N? and P? layers have an upward concave shape under the gate. The gate electrode and the Schottky metal are connected to the diode's anode. A P? layer lies between the RESURF structure and an NISO region which has an electrical connection to the anode. A P+ layer under the Schottky metal is in contact with the P? layer through a P well.Type: GrantFiled: May 27, 2010Date of Patent: March 22, 2011Assignee: Fairchild Semiconductor CorporationInventor: Jun Cai
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Patent number: 7902601Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.Type: GrantFiled: December 16, 2008Date of Patent: March 8, 2011Assignee: Semiconductor Components Industries, LLCInventors: Gary H. Loechelt, John M. Parsey, Jr., Peter J. Zdebel, Gordon M. Grivna
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Patent number: 7893456Abstract: A thyristor-based memory may comprise a thyristor accessible via an access transistor. A temperature dependent bias may be applied to at least one of a supporting substrate and an electrode capacitively-coupled to a base region of the thyristor. The voltage level of the adaptive bias may change with respect to temperature and may influence and/or compensate an inherent bipolar gain of the thyristor in accordance with the change in bias and may enhance its performance and/or reliability over a range of operating temperature. In a particular embodiment, the thyristor may be formed in a layer of silicon of an SOI substrate and the adaptive bias coupled to a supporting substrate of the SOI structure.Type: GrantFiled: February 9, 2009Date of Patent: February 22, 2011Assignee: T-RAM Semiconductor, Inc.Inventors: Farid Nemati, Kevin J. Yang
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Patent number: 7883941Abstract: A method for fabricating a memory device is provided. A semiconductor layer is provided that includes first, second, third and fourth well regions of a first conductivity type in the semiconductor layer. A first gate structure overlies the first well region, a second gate structure overlies the second well region, a third gate structure overlies the third well region and is integral with the second gate structure, and a fourth gate structure overlies the fourth well region. Sidewall spacers are formed adjacent a first sidewall of the first gate structure and sidewalls of the second through fourth gate structures. In addition, an insulating spacer block is formed overlying a portion of the first well region and a portion of the first gate structure. The insulating spacer block is adjacent a second sidewall of the first gate structure.Type: GrantFiled: May 29, 2008Date of Patent: February 8, 2011Assignee: GlobalFoundries Inc.Inventor: Hyun-Jin Cho
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Publication number: 20100163924Abstract: A lateral silicon controlled rectifier structure includes a P-type substrate; an N-well region in the P-type substrate; a first P+ doped region in the N-well region and being connected to an anode; a P-well region in the P-type substrate and bordering upon the N-well region; a first N+ doped region formed in the P-well region and separated from the first P+ doped region by a spacing distance, the first N+ doped region being connected to a cathode; and a gate structure overlying a portion of the P-type substrate between the first P+ doped region and the first N+ doped region.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Inventors: Ta-Cheng Lin, Te-Chang Wu
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Patent number: 7745845Abstract: An integrated low leakage Schottky diode has a Schottky barrier junction proximate one side of an MOS gate with one end of a drift region on an opposite side of the gate. Below the Schottky metal and the gate oxide is a RESURF structure of an N? layer over a P? layer which also forms the drift region that ends at the diode's cathode in one embodiment of the present invention. The N? and P? layers have an upward concave shape under the gate. The gate electrode and the Schottky metal are connected to the diode's anode. A P? layer lies between the RESURF structure and an NISO region which has an electrical connection to the anode. A P+ layer under the Schottky metal is in contact with the P? layer through a P well.Type: GrantFiled: April 23, 2008Date of Patent: June 29, 2010Assignee: Fairchild Semiconductor CorporationInventor: Jun Cai
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Patent number: 7667241Abstract: An electrostatic discharge protection device for protecting a node includes a transistor, a silicon controlled rectifier, a second contact region laterally displaced from the first contact region, and a collection region adjacent the source region. The transistor includes a semiconductor substrate, a source region, a channel region adjacent the source region, a gate over the channel region, and a drain region laterally displaced from the channel. The silicon controlled rectifier includes the source region, a portion of the substrate, a doped well, and a first contact region in the well, laterally displaced from the drain region. The collection region, the source region and the gate, are metallically connected. The node, the first contact region, and the second contact region, are metallically connected, and the drain region is not metallically connected to the node.Type: GrantFiled: September 25, 2007Date of Patent: February 23, 2010Assignee: Cypress Semiconductor CorporationInventors: Andrew Walker, Helmut Puchner
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Patent number: 7602025Abstract: A drift diffusion layer of a low concentration is formed so as to surround a collector buffer layer having a relatively high concentration including a high-concentration collector diffusion layer in a plane structure. Thereby, current crowding in corner portions of the high-concentration collector diffusion layer is suppressed while maintaining a short turnoff time, and the improvement of breakdown voltage at on-time is realized.Type: GrantFiled: October 18, 2007Date of Patent: October 13, 2009Assignee: Panasonic CorporationInventors: Hisaji Nishimura, Hiroyoshi Ogura, Akira Ohdaira
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Publication number: 20090140290Abstract: A semiconductor component including a short-circuit structure. One embodiment provides a semiconductor component having a semiconductor body composed of doped semiconductor material. The semiconductor body includes a first zone of a first conduction type and a second zone of a second conduction type, complementary to the first conduction type, the second zone adjoining the first zone. The first zone and the second zone are coupled to an electrically highly conductive layer. A connection zone of the second conduction type is arranged between the second zone and the electrically highly conductive layer.Type: ApplicationFiled: November 26, 2008Publication date: June 4, 2009Applicant: INFINEON TECHNOLOGIES AGInventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Uwe Kellner-Werdehausen, Reiner Barthelmess
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Patent number: 7525155Abstract: A high voltage MOS transistor has a thermally-driven-in first doped region and a second doped region that form a double diffused drain structure. Boundaries of the first doped region are graded. A gate-side boundary of the first doped region extends laterally below part of the gate electrode. The second doped region is formed within the first doped region. A gate-side boundary of the second doped region is separated from a closest edge of the gate electrode by a first spaced distance. The gate-side boundary of the second doped region is separated from a closest edge of the spacer by a second spaced distance. The first spaced distance is greater than the second spaced distance. An isolation-side boundary of the second doped region may be separated from an adjacent isolation structure by a third spaced distance.Type: GrantFiled: March 23, 2006Date of Patent: April 28, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fu-Hsin Chen, Ruey-Hsin Liu
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Publication number: 20080237632Abstract: A III-nitride power semiconductor device that includes a first III-nitride power semiconductor device and a second III-nitride power semiconductor device formed in a common semiconductor die and operatively integrated to form a half-bridge.Type: ApplicationFiled: March 29, 2007Publication date: October 2, 2008Inventor: Daniel M. Kinzer
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Patent number: RE44547Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.Type: GrantFiled: October 24, 2012Date of Patent: October 22, 2013Assignee: Semiconductor Components Industries, LLCInventors: Gary H. Loechelt, John M. Parsey, Peter J. Zdebel, Gordon M. Grivna
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Patent number: RE45365Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.Type: GrantFiled: September 5, 2013Date of Patent: February 10, 2015Assignee: Semiconductor Components IndustriesInventors: Gary H. Loechelt, John M. Parsey, Jr., Peter J. Zdebel, Gordon M. Grivna