Abstract: A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.

Abstract: In accordance with an embodiment, a method include switching on a transistor device by generating a first conducting channel in a body region by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel in the body region by driving a second gate electrode. The first gate electrode is dielectrically insulated from a body region by a first gate dielectric, and the second gate electrode is dielectrically insulated from the body region by a second gate dielectric, arranged adjacent the first gate electrode, and separated from the first gate electrode by a separation layer. The body region is arranged between a source region and a drift region, and wherein the drift region is arranged between body region and a drain region.

Abstract: In accordance with an embodiment, a method includes switching on a transistor device by generating a first conducting channel by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel by driving a second gate electrode, wherein the second gate electrode is adjacent the first gate electrode in a current flow direction of the transistor device.

Abstract: In accordance with an embodiment, a method include switching on a transistor device by generating a first conducting channel in a body region by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel in the body region by driving a second gate electrode. The first gate electrode is dielectrically insulated from a body region by a first gate dielectric, and the second gate electrode is dielectrically insulated from the body region by a second gate dielectric, arranged adjacent the first gate electrode, and separated from the first gate electrode by a separation layer. The body region is arranged between a source region and a drift region, and wherein the drift region is arranged between body region and a drain region.

Abstract: One embodiment of the present invention relates to a silicon-controlled-rectifier (SCR). The SCR includes a longitudinal silicon fin extending between an anode and a cathode and including a junction region there between. One or more first transverse fins traverses the longitudinal fin at one or more respective tapping points positioned between the anode and the junction region. Other devices and methods are also disclosed.

Abstract: One embodiment of the present invention relates to a silicon-controlled-rectifier (SCR). The SCR includes a longitudinal silicon fin extending between an anode and a cathode and including a junction region there between. One or more first transverse fins traverses the longitudinal fin at one or more respective tapping points positioned between the anode and the junction region. Other devices and methods are also disclosed.

Abstract: An organic light emitting element includes an organic light emitting diode formed on a substrate, coupled to a transistor including a gate, a source and a drain and including a first electrode, an organic thin film layer and a second electrode; a photo diode formed on the substrate and having a semiconductor layer including a high-concentration P doping region, a low-concentration P doping region, an intrinsic region and a high-concentration N doping region; and a controller that controls luminance of light emitted from the organic light emitting diode, to a constant level by controlling a voltage applied to the first electrode and the second electrode according to the voltage outputted from the photo diode.

Abstract: A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.

Abstract: An apparatus including a first electrode portion configured to inject charge carriers; a second electrode portion configured to collect charge carriers and provide an output signal; a third electrode portion configured to collect charge carriers and provide an output signal; a monolithic semiconductor, providing a first channel for the transport of injected charge carriers between the first electrode portion and the second electrode portion and providing a second channel for the transport of injected charge carriers between the first electrode portion and the third electrode portion, wherein the first channel is configured such that a charge carrier injected at the first electrode portion will reach the second electrode portion via the first channel after a first transport time and the second channel is configured such that a charge carrier injected at the first electrode portion will reach the third electrode portion via the second channel after a second transport time greater than the first transport time;

Abstract: Atomic layer deposition is enhanced using plasma. Plasma begins prior to flowing a second precursor into a chamber. The second precursor reacts with a first precursor to deposit a layer on a substrate. The layer may include at least one element from each of the first and second precursors. The layer may be TaN, and the precursors may be TaF5 and NH3. The plasma may begin during purge gas flow between a pulse of the first precursor and a pulse of the second precursor. Thermal energy assists the reaction of the precursors to deposit the layer on the substrate. The thermal energy may be greater than generally accepted for ALD (e.g., more than 300 degrees Celsius).

Abstract: A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.

Abstract: A heterojunction bipolar transistor with InGaP as the emitter layer and capable of both reliable electrical conduction and thermal stability wherein a GaAs layer is inserted between the InGaP emitter layer and AlGaAs ballast resistance layer, to prevent holes reverse-injected from the base layer from diffusing and reaching the AlGaAs ballast resistance layer.

Abstract: A semiconductor device made of a group-III nitride semiconductor having excellent properties is provided. The semiconductor device has a horizontal diode structure of Schottky type or P-N junction type, or combined type thereof having a main conduction pathway in the horizontal direction in a conductive layer with unit anode portions and unit cathode electrodes being integrated adjacently to each other in the horizontal direction. The conductive layer is preferably formed by depositing a group-III nitride layer and generating a two-dimensional electron gas layer on the interface. Forming the conductive layer of the group-III nitride having high breakdown field allows the breakdown voltage to be kept high while the gap between electrodes is narrow, which achieves a semiconductor device having high output current per chip area.

Abstract: A heterojunction bipolar transistor with InGaP as the emitter layer and capable of both reliable electrical conduction and thermal stability wherein a GaAs layer is inserted between the InGaP emitter layer and AlGaAs ballast resistance layer, to prevent holes reverse-injected from the base layer from diffusing and reaching the AlGaAs ballast resistance layer.

Abstract: A method of forming a memory cell comprises forming a stack comprising a first electrode, an insulating layer over the first electrode, and a second electrode over the insulating layer, with a side wall on the stack. A side wall spacer comprising a programmable resistive material in electrical communication with the first and second electrodes is formed. The side wall spacer is formed by depositing a layer of programmable resistive material over the side wall of the stack, anisotropically etching the layer of programmable resistive material to remove it in areas away from the side wall, and selectively etching the programmable resistive material according to a pattern to define the width of the side wall spacer. In embodiments described herein, the width is about 40 nanometers or less.

Abstract: A thyristor-based memory device may comprise two base regions of opposite type conductivity formed between a cathode-emitter region and an anode-emitter region. A junction defined between the p-base region and the cathode-emitter region of the thyristor may be “treated” with a high ionization energy acceptor such as indium in combination with carbon as an activation assist species. These two implants may form complexes that may extend across the junction region.

Abstract: Provided is a nitride-based semiconductor device in which a SAW filter and a HFET are integrated on a single substrate, as well as a method for manufacturing the same. The nitride-based semiconductor device comprises a semi-insulating GaN layer formed on a substrate, a plurality of electrodes for a SAW filter formed on one side of the semi-insulating GaN layer, an Al-doped GaN layer formed on the other side of the semi-insulating GaN layer, an AlGaN layer formed on the Al-doped GaN layer, and a plurality of electrodes for an HFET formed on the AlGaN layer. Both sides of the semi-insulating GaN layer have the same surface level.

Abstract: There is provided an electrostatic discharge protection device comprising a P conductive type first P well region 101 formed in a P type epitaxial layer 31 being deposited on a surface of a P+ substrate 30 having a prescribed thickness, an N conductive type first N well 101 a periphery thereof being brought into direct contact with and surrounded by a first P well region 101, P conductive type first P diffusion regions 121a and 121b, a P conductive type third P diffusion region 125, and an N conductive type second N diffusion region 223 arranged within a first P well region 101, and a P conductive type second P diffusion region 123 and an N conductive type first N diffusion region 221 arranged within a first N well 201.

Abstract: A semiconductor integrated circuit device has a semiconductor integrated circuit chip, a package enclosing the chip, and a plurality of conductors connecting the bonding pads of the chip to the leads of the package. The chip has an internal circuit, a plurality of bonding pads having signal paths formed between themselves and the internal circuit, and a switching circuit provided in a predetermined signal path so as to perform a switching operation to allow the internal circuit to be connected selectively to one of different bonding pads. The switching circuit is fed with an external signal to perform its switching operation in such a way as to prevent the signals passing through mutually adjacent conductors from affecting each other.

Abstract: An insulated gate semiconductor device includes a control electrode having a trench type structure formed on the surface of a first semiconductor layer of a first conductivity type via a gate insulation film and disposed in a lattice shape, the control electrode having a plurality of first control electrode sections and a plurality of second control electrode sections which intersect with the plurality of first control electrode sections, respectively, and a plurality of fifth semiconductor layers of a second conductivity type which are provided on an interface of the first semiconductor layer in contact with the plurality of second control electrode sections, and connected to at least one of a plurality of second semiconductor layers of the second conductivity type, the fifth semiconductor layers having impurity concentration lower than that of the plurality of second semiconductor layers.

Abstract: The present invention provides a PMSCR (bridging modified lateral modified silicon controlled rectifier having first conductivity type) with a guard ring controlled circuit. The present invention utilizes controlled circuit such as switch to control functionally of guard ring of PMSCR. In normal operation, the switch is of low impedance such that the guard ring is short to anode and collects electrons to enhance the power-zapping immunity. Furthermore, during the ESD (electrostatic discharge) event, the switch is of high impedance such that the guard ring is non-functional. Thus, the PMSCR with guard ring control circuit can enhance both the ESD performance and the power-zapping immunity in the application of the HV (high voltage) pad.

Abstract: An ESD protection circuit having a high triggering threshold. The ESD protection circuit comprises a semiconductor-controlled rectifier (SCR) and a bipolar-junction-transistor (BJT). The SCR comprises an anode, an anode gate, a cathode gate and a cathode. The anode is coupled to a first pad. The cathode gate and the cathode are coupled to a second pad. The BJT transistor is parasitic under a metal-on-semiconductor (MOS) transistor and has a collector and an emitter. Either the collector or the emitter is coupled to the anode gate, and the other is coupled only to the second pad. Current generated at the anode is shared by the BJT transistor. A larger current is required to trigger the SCR in the ESD protection circuit of the present invention and result in a latch-up. Thus, latch-up caused by accidental noise is prevented during normal power operations.

Abstract: An audio amplifier output stage layout technique achieves minimum cross coupling between audio amplifier channels. Regarding TDAA output stages, the typical TDAA includes two demodulation inductors per audio channel. The two pair of demodulation inductors associated with the TDAA are arranged to form an X-pattern to simultaneously minimize cross coupling between audio amplifier channels and reduce PCB layout size.

Abstract: A semiconductor thyristor device incorporates buried regions to achieve low breakover voltage devices, and the buried regions are offset laterally with respect to the emitter regions. The low voltage thyristor devices can be incorporated into five-pin protection modules for protecting customer circuits.

Abstract: A lower electrode of a semiconductor is directly connected to a heat sink, while a first electrode and a second electrode are connected to a plate-shaped second conductor by means of a first conductor. Radiated heat of the semiconductor is directly conducted to the heat sink and absorbed. The heat is radiated by being further conducted to the plate-shaped second conductor via the first conductor, thereby allowing the semiconductor to have a reduced temperature.

Abstract: An embedded SCR in conjunction with a Gated-NMOS is created for protecting a chip input or output pad from ESD, by inserting a p+ diffusion and the n-well in the drain side and a part of the drain to forms a low-trigger, high efficiency SCR. The device layout is such that the drain connection is tightly tied together at the p+ diffusion and the n+ drain making that connection very short and, thereby, preventing latch-up. The parasitic SCR is contained entirely within the n+ diffusion (the source of the grounded gate NMOS transistor) at either side of the structure and, therefore, called an embedded SCR. For a 12 volt I/O device each of two n+ drains is placed in its own n-type doped drain (ndd) area straddling halfway the n-well. The structure is repeated as required and a p+ diffusion is implanted at both perimeters and connected to the nearest n+ source and a reference voltage.

Abstract: The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly, an object of the present invention is to reduce an ON voltage while ensuring a wide operating area and sustaining a high breakdown voltage. To achieve this object, a semiconductor base body is divided into a first MOS region and a second MOS region. In the first MOS region, a p base layer, an n+ emitter layer and a p+ layer are provided in an upper main surface of the semiconductor base body. In the second MOS region, a p base layer, an n layer and a p+ layer are provided. When a positive gate voltage is applied to a gate electrode in order to turn on the device, since the p base layer and the emitter electrode are cut off, a main current does not flow in the p base layer. Therefore, a hole accumulation effect is enhanced and the ON voltage is reduced.

Abstract: A power MOSFET includes a pair of electrically isolated gates having different gate widths. The MOSFET is connected in a switching mode DC-DC converter, with the gates being driven by a pulse width modulation (PWM) control to vary the duty cycle of the gate drive signal and thereby regulate the output voltage of the DC-DC converter. In light load conditions, the larger gate is disconnected from the PWM control to reduce the gate capacitance which must be driven by the PWM control. In normal load conditions, the larger gate is connected to the PWM control to reduce the on-resistance of the MOSFET. Both of these operations increase the efficiency of the DC-DC converter.

Abstract: A bipolar transistor includes an emitter, a base, a collector, an additional base semiconductor region having the same conductivity type as the base, arranged at the emitter and constituting a connection with the emitter. A first electrical connection connects the additional base semiconductor region with the base, thereby short-circuiting the additional base semiconductor region relative to the base, such that the additional base semiconductor region and base together constitute a combined base of the transistor. A further semiconducting collector region has the same conductivity type as the collector. A second electrical connection connects the further semiconductor connecting region and the collector, thereby short-circuiting the further semiconducting collector region and the collector, such that the additional semiconducting collector region and the collector together constitute a combined collector of the transistor.

Abstract: The invention provides an optical functioning device which emits and receives light, and a driver circuit for controlling the device with light. In the device, elements, in which semiconductor multilayer-film reflecting mirrors are provided at both the upper and lower ends of a pnpn structure of semiconductors and which have light-emitting and light-receiving functions to act as optical resonators, are integrated two-dimensionally each with electrodes which are provided for the and the transistors act as phototransistors into which light is introduced.

Abstract: A novel semiconductor device with a pair of main surfaces is disclosed, in which at least three semiconductor layers are formed adjacently to each other. The device comprises a main thyristor portion for supplying a main current, an auxiliary thyristor portion, a pilot thyristor portion and a breakover portion. The breakover portion, in turn, includes a semiconductor layer having a high impurities concentration formed on one of the main surfaces, and a plurality of semiconductor layers having a high impurities concentration of opposite conduction type formed adjacently to the semiconductor layer and in spaced relationship from each other.

Abstract: A voltage-controlled power monolithic bidirectional switch has two main terminals and includes a control electrode whose voltage is referenced to one of the main terminals. The switch includes a lateral P-channel MOS transistor; a vertical N-channel MOS transistor, the source well of the vertical N-channel MOS transistor also constituting the source of the lateral transistor; a lateral thyristor whose first three regions correspond to the source, drain and channel of the lateral MOS transistor; a first vertical thyristor disposed in parallel with the lateral thyristor; and a second vertical thyristor having a polarity opposite to the first polarity and disposed in parallel with the vertical MOS transistor.

Abstract: High withstand voltage, low on-voltage, low turn-off loss, and high switching speed are realized in semiconductor bidirectional switches in which the potential of the substrate is floating. A switch has a p-type substrate without an electrode, and an n-layer on the substrate. At least one pair of p-well regions and at least one p-region are formed in a surface layer of the n-layer. An n.sup.+ region is formed in the p-well region, and a gate electrode is fixed via an insulation film to the p-well region. A main electrode is fixed to a part of the surface of the n.sup.+ region and the surface of a p.sup.+ contact region in the p-well region.

Abstract: An a.c. switch includes across first and second main terminals a first thyristor disposed in parallel with, but in an opposite direction of, a first diode and in series with a second thyristor disposed in parallel with but in an opposite direction of, a second diode. The first thyristor has a gate terminal connected to its gate area. The second thyristor and second diode are vertically realized in the same substrate, their conduction areas being closely interlaced, whereby a polarity inversion following a conduction period of the second diode causes the second thyristor to become conductive.

Abstract: A control device for controlling a double gate semiconductor device having a second gate electrode for controlling transition from a thyristor operation to a transistor operation, and a first gate electrode for controlling transition from transistor operation to an ON/OFF operation, and for controlling a current passing from a collector electrode to an emitter electrode, includes a first gate control circuit for delaying a turn-off signal to the double gate semiconductor device and applying the turn-off signal to the first gate electrode.

Abstract: An a.c. switch includes across first and second main terminals a first thyristor disposed in parallel with, but in an opposite direction of, a first diode and in series with a second thyristor disposed in parallel with, but in an opposite direction of, a second diode. The first thyristor has a gate terminal connected to its gate area. The second thyristor and second diode are vertically realized in the same substrate, their conduction areas being closely interlaced, whereby a polarity inversion following a conduction period of the second diode causes the second thyristor to become conductive.

Abstract: A semiconductor device thyristor structure includes a first conductive type collector region, second conductive type and first conductive type base regions, and a second conductive type emitter region. First conductive type regions and second conductive type regions have respective first and second type majority carriers. A first MOSFET injects the second type majority carriers into the second conductive type base region. A second MOSFET is opened and closed independent of the first MOSFET and extracts the first type majority carriers from the first conductive type base region. A third MOSFET has a first gate electrode which is also a gate electrode of the first MOSFET, for extracting the first type majority carriers from the first conductive type base region. First conductive type and second conductive type emitter regions are formed within the first conductive type base region and an emitter voltage can be simultaneously applied to these emitter regions.

Abstract: A semiconductor switching device having gate-controlled regenerative and non-regenerative conduction modes includes a P-N-P-N thyristor and a diverter region in a semiconductor substrate. Regenerative conduction can be initiated by electrically connecting the thyristor's cathode region and first base region in response to a first bias signal. Non-regenerative conduction can also be initiated by electrically connecting the thyristor's second base region to the diverter region in response to a second bias signal, after regenerative conduction has been initiated. Alternative, non-regenerative conduction can be initiated by electrically connecting the thyristor's second base region to the diverter region and then electrically connecting the thyristor's first base region to the cathode region.

Abstract: The semiconductor device is formed of an EST part and an IGBT part, wherein the EST part has a first MOSFET and a second MOSFET synchronously switching, and the IGBT part has a third MOSFET controllable independently from them. At a turn-off of the semiconductor device, when turning off the first and second MOSFETs while keeping the third MOSFET at an on-state, IGBT operation remains. Thus, the current path which tends to flow to an emitter region changes toward an emitter electrode side even if the recovery of the potential barrier is late due to the junction in the emitter region, and the charge accumulation to the emitter region is restrained. After the potential barrier is recovered, the third MOSFET is turned off. Controllable turn-off current can be enlarged and turn-off time can be shortened.

Abstract: A vertical type surge protection device for absorbing surges of either polarity has a second region forming a first pn junction with a first region, a third region forming a first minority carrier injection junction with respect to the second region, a fourth region forming a second pn junction with the first region and a fifth region forming a second minority carrier injection junction with the fourth region. When the absolute value of a surge voltage applied across the device exceeds the breakdown voltage, either the one of the first and second pn junctions that is reverse biased owing to the surge polarity breaks down or punch-through occurs between the first and third regions or between the first and fifth regions, whereafter breakover ensues as a result of positive feedback.

Abstract: A thyristor comprised of a vertical thyristor including, on its front surface, a localized anode region, and on its rear surface, a cathode metallization substantially coating the whole rear surface region, and, on its front surface region, a lateral thyristor. The thyristor gate corresponds to the cathode region or to the cathode-gate region of the lateral thyristor. The cathode-gate region or cathode region, respectively, of the lateral thyristor is connected to the cathode of the vertical thyristor.

Abstract: A channel in which electron current is supplied from n.sup.+ type source layer to an n.sup.- type base layer is formed in a thyristor portion by using a first gate electrode to have an electrical connection in a thyristor state. Injection of hole current to a p type base layer, which is necessary to maintain the thyristor state is extracted to a source terminal by a control MOSFET portion including a second gate electrode a turn-off time and the state of this device is changed to the transistor state similar to that in the IGBT so that a short switching time turn-off is realized.

Abstract: A gate electrode includes a first region formed in an OFF gate region and a second region formed in an ON gate region. A P-channel region is formed in the OFF gate region and an N-channel region is formed in the ON gate region to separate these gate regions. Since a P.sup.- -type channel region of low impurity concentration is formed at an end of a P-type base region in which the N-channel region is formed, the impurity concentration of the P-type base region can be increased and thus turn-off characteristic is improved.

Abstract: A bi-directional switch includes a well region of a first conductivity type placed within a substrate. A first region of second conductivity type is placed within the well. A second contact region of second conductivity type is placed within the well. A drift region of second conductivity is placed between the first contact and the second contact. The drift region is separated from the first contact by a first channel region and is separated from the second contact by a second channel region. A first gate region is placed over the first channel region and a second gate region over the second channel region.

Abstract: A GTO thyristor includes a p-type emitter layer, an n-type base layer, a p-type base layer and an n-type emitter layer. An additional n-type layer is formed on the p-type base layer next to the n-type emitter layer An additional p.sup.+ -type layer is formed on the additional n-type layer and stretches to the n-type emitter layer. An anode electrode and a cathode electrode are disposed respectively on the n-type emitter layer and the p-type base layer. The n-type emitter layer and the additional p.sup.+ -type layer are connected with each other by a floating electrode. A first gate electrode is disposed on the additional p.sup.+ -type layer, additional n-type layer and p-type base layer with an insulating film interposed therebetween so as to form a first FET. A second gate electrode is disposed on the n-type base layer, p-type base layer and n-type emitter layer with an insulating film interposed therebetween so as to form a second FET.

Abstract: A switching device includes a thyristor and a MOSFET, and a voltage clamp circuit. The voltage clamp circuit includes an N.sup.+ type contact region formed in a surface layer of a N type substrate and electrically connected to a gate electrode of a MOSFET, and a P type guard ring surrounding the contact region.

Abstract: A conductivity modulation type MISFET, and a control circuit thereof are provided. A semiconductor device 1 comprises a conductivity modulation type MOSFET 1a and a built-in MOSFET 1b which is designed to control a source electrode 12a and a control electrode 13 of a parasitic transistor to be in a short state or an open state, said conductivity modulation type MOSFET 1a having a polysilicon gate 6 on an obverse surface of n.sup.- -type conductivity modulation layer 4, a p-type channel diffusion area 7, n.sup.+ -type source diffusion area 8 and a parasitic transistor control electrode 13 conductively connected to the p-type channel diffusion area 7 through a p.sup.+ -type contact area 9.

Abstract: A gate valve structure has an expanding valve assembly mounted with the valve chamber comprising a gate (32) and segment (34) which may be laterally expanded. The gate and segment have a plurality of coacting interfitting saw-type teeth (46,48) which define cam surfaces (50,56) to effect expansion of the gate valve assembly. A flexible sleeve (64) is secured about the ports (42,44) in the gate and segment to bridge the gap (58) between the gate (32) and segment (34) upon expansion. A torsion spring (72) urges the gate and segment to a contracted position.