Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of the second conductivity type, and an insulating portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The insulating portion is located in a vicinity of, and contacts, the second semiconductor region and the third semiconductor region, and the insulating portion includes a plurality of voids therein, the plurality of voids extending around the second semiconductor region.

Abstract: Provided is an electrostatic protection circuit that has little leakage current under normal operation and allows a trigger voltage to be set comparatively freely, without requiring a special process step. This electrostatic protection circuit is provided with a series circuit including a transistor, a predetermined number of diodes and an impedance element that are connected in series between the first node and the second node, and a discharge circuit configured to send current from the first node to the second node following an increase in a potential difference that occurs between both ends of the impedance element, when the first node reaches a higher potential than the second node and current flows through the series circuit. The predetermined number of diodes are connected between the source and the back gate of the transistor.

Abstract: A silicon-based substrate on which a nitride compound semiconductor layer is formed on a front surface thereof, including a first portion provided on the front surface side which has a first impurity concentration and a second portion provided on an inner side of the first portion which has a second impurity concentration higher than the first impurity concentration, wherein the first impurity concentration being 1×1014 atoms/atomscm3 or more and less than 1×1019 atoms/cm3. Consequently, there is provided the silicon-based substrate in which the crystallinity of the nitride compound semiconductor layer formed on an upper side thereof can be maintained excellently while improving a warpage of the substrate.

Abstract: A power semiconductor device comprising a first metal electrode and a second metal electrode formed on a first substrate surface of a semiconductor substrate, a semi-insulating field plate interconnecting said first and second metal electrodes, and an insulating oxide layer extending between said first and second metal electrodes and between said field plate and said semiconductor substrate, wherein said semi-insulating field plate is a titanium nitride (TiN) field plate.

Abstract: A nanowire circuit architecture is presented. The technology comprises of nanowire transistors (8,9), and optionally nanowire capacitors (12) and nanowire resistors (11), that are integrated using two levels of interconnects only (1,2). Implementations of ring-oscillators, sample-and-hold circuits, and comparators may be realized in this nanowire circuit architecture. Circuit input and circuit output as well as the transistor connections within each circuit are provided in the two levels of interconnects (1,2).

Abstract: An insulating layer, an undoped first GaN layer and an AlGaN layer are laminated in this order on a surface of a semiconductor substrate. A surface barrier layer formed by a two-dimensional electron gas is provided in an interface between the first GaN layer and the AlGaN layer. A recess (first recess) which reaches the first GaN layer but does not pierce the first GaN layer is formed in a surface layer of the AlGaN layer. A first high withstand voltage transistor and a control circuit are formed integrally on the aforementioned semiconductor substrate. The first high withstand voltage transistor is formed in the first recess and on a surface of the AlGaN layer. The control circuit includes an n-channel MOSFET formed in part of the first recess, and a depression type n-channel MOSFET formed on a surface of the AlGaN layer.

Abstract: An electrostatic discharge (ESD) protection circuit structure includes several diffusion regions and a MOS transistor. The circuit structure includes a first diffusion region of a first type (e.g., P-type or N-type) formed in a first well of the first type, a second diffusion region of the first type formed in the first well of the first type, and a first diffusion region of a second type (e.g., N-type or P-type) formed in a first well of the second type. The first well of the second type is formed in the first well of the first type. The MOS transistor is of the second type and includes a drain formed by a second diffusion region of the second type formed in a second well of the second type bordering the first well of the first type.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.

Abstract: A bipolar semiconductor switch having a semiconductor body is provided. The semiconductor body includes a first p-type semiconductor region, a second p-type semiconductor region, and a first n-type semiconductor region forming a first pn-junction with the first p-type semiconductor region and a second pn-junction with the second p-type semiconductor region. On a shortest path through the first n-type semiconductor region between the first pn-junction and the second pn-junction a concentration of charge recombination centers and a concentration of n-dopants vary. The concentration of the charge recombination centers has a maximum at a point along the shortest path where the concentration of n-dopants is at least close to a maximum dopant concentration. Further, a manufacturing method for the bipolar semiconductor switch is provided.

Abstract: In an ultra high voltage lateral GaN structure having a 2DEG region extending between two terminals, an isolation region is provided between the two terminals to provide for reversible snapback.

Abstract: Apparatus and methods for electronic circuit protection under high stress operating conditions are provided. In one embodiment, an apparatus includes a substrate having a first p-well, a second p-well adjacent the first p-well, and an n-type region separating the first and second p-wells. An n-type active area is over the first p-well and a p-type active area is over the second p-well. The n-type and p-type active areas are electrically connected to a cathode and anode of a high reverse blocking voltage (HRBV) device, respectively. The n-type active area, the first p-well and the n-type region operate as an NPN bipolar transistor and the second p-well, the n-type region, and the first p-well operate as a PNP bipolar transistor. The NPN bipolar transistor defines a relatively low forward trigger voltage of the HRBV device and the PNP bipolar transistor defines a relatively high reverse breakdown voltage of the HRBV device.

Abstract: A trench MOS structure is provided. The trench MOS structure includes a substrate, an epitaxial layer, a trench, a gate isolation, a trench gate, a guard ring and a reinforcement structure within the guard ring. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The trench is disposed in the epitaxial layer. The gate isolation covers the inner wall of the trench. The trench gate is disposed in the trench and has the first conductivity type. The guard ring has a second conductivity type and is disposed within the epitaxial layer. The reinforcement structure has an electrically insulating material and is disposed within the guard ring.

Abstract: The invention provides a novel memory for which process technology is relatively simple and which can store multivalued information by a small number of elements. A part of a shape of the first electrode in the first storage element is made different from a shape of the first electrode in the second storage element, and thereby voltage values which change electric resistance between the first electrode and the second electrode are varied, so that one memory cell stores multivalued information over one bit. By partially processing the first electrode, storage capacity per unit area can be increased.

Abstract: Apparatus and methods for electronic circuit protection under high stress operating conditions are provided. In one embodiment, an apparatus includes a substrate having a first p-well, a second p-well adjacent the first p-well, and an n-type region separating the first and second p-wells. An n-type active area is over the first p-well and a p-type active area is over the second p-well. The n-type and p-type active areas are electrically connected to a cathode and anode of a high reverse blocking voltage (HRBV) device, respectively. The n-type active area, the first p-well and the n-type region operate as an NPN bipolar transistor and the second p-well, the n-type region, and the first p-well operate as a PNP bipolar transistor. The NPN bipolar transistor defines a relatively low forward trigger voltage of the HRBV device and the PNP bipolar transistor defines a relatively high reverse breakdown voltage of the HRBV device.

Abstract: An ESD protection circuit includes a MOS transistor of a first type, a MOS transistor of a second type, an I/O pad, and first, second, and third guard rings of the first, second, and first types, respectively. The MOS transistor of the first type has a source coupled to a first node having a first voltage, and a drain coupled to a second node. The MOS transistor of the second type has a drain coupled to the second node, and a source coupled to a third node having a second voltage lower than the first voltage. The I/O pad is coupled to the second node. The first, second, and third guard rings are positioned around the MOS transistor of the second type.

Abstract: Growth of thermoelectric materials in the form of quantum well superlattices on three-dimensionally structured substrates provide the means to achieve high conversion efficiency of the thermoelectric module combined with inexpensiveness of fabrication and compatibility with large scale production. Thermoelectric devices utilizing thermoelectric materials in the form of quantum well semiconductor superlattices grown on three-dimensionally structured substrates provide improved thermoelectric characteristics that can be used for power generation, cooling and other applications.

Abstract: A vertical transient voltage suppressor for protecting an electronic device is disclosed. The vertical transient voltage includes a conductivity type substrate having highly doping concentration; a first type lightly doped region is arranged on the conductivity type substrate, wherein the conductivity type substrate and the first type lightly doped region respectively belong to opposite types; a first type heavily doped region and a second type heavily doped region are arranged in the first type lightly doped region, wherein the first and second type heavily doped regions and the conductivity type substrate belong to same types; and a deep first type heavily doped region is arranged on the conductivity type substrate and neighbors the first type lightly doped region, wherein the deep first type heavily doped region and the first type lightly doped region respectively belong to opposite types, and wherein the deep first type heavily doped region is coupled to the first type heavily doped region.

Abstract: A protective structure is produced by providing a semiconductor substrate having doping of a first conductivity type. A semiconductor layer having doping of a second conductivity type is applied at a surface of the semiconductor substrate. A buried layer with doping of a second conductivity type is formed in a first region of the semiconductor layer, producing a layer at the junction between the semiconductor layer and semiconductor substrate. A first dopant zone having doping of a first conductivity type is formed in the first region of the semiconductor layer above the buried layer. A second dopant zone having doping of a second conductivity type is formed in a second region of the semiconductor layer. An electrical insulation is formed between the first and second regions of the semiconductor layer. A common connection device is formed for the first and second dopant zones.

Abstract: A semiconductor device has at least a cell between two opposite main surfaces. Each cell has a first device feature region contacted with the first main surface and a second device feature region contacted with the second main surface. There is a voltage-sustaining region between the first device feature region and the second device feature region, which includes at least a semiconductor region and an insulator region containing conductive particles. The semiconductor region and the insulator region contact directly with each other. The structure of such voltage-sustaining region can not only be used to implement high-voltage devices, but further be used as a junction edge technique of high-voltage devices.

Abstract: A phase change RAM device includes a semiconductor substrate having a phase change cell area and a voltage application area; a first oxide layer, a nitride layer and a second oxide layer sequentially formed on the semiconductor substrate; a first plug formed in the first oxide layer, the nitride layer and the second oxide layer of the phase change cell area; a second plug formed in the first oxide layer and the nitride layer of the voltage application area; a conductive line formed in the second oxide layer; a third oxide layer formed on the second oxide layer; a lower electrode shaped like a plug, the lower electrode being formed so as to directly make contact with the first plug; and a phase change layer and an upper electrode sequentially formed on the lower electrode in a pattern form.

Abstract: An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes a modified breakdown shallow trench isolation (STI) region to effectively reduce a drain to source resistance when compared to a conventional semiconductor device, thereby increasing the breakdown voltage of the semiconductor device when compared to the conventional semiconductor device. The modified breakdown STI region allows more current to pass from a source region to a drain region of the semiconductor device, thereby further increasing the break down voltage of the semiconductor device from that of the conventional semiconductor device. The semiconductor device may include a modified well region to further reduce the drain to source resistance of the semiconductor device.

Abstract: A power semiconductor device according to an embodiment of the present invention includes a first semiconductor layer of a first or second conductivity type, a second semiconductor layer of the first conductivity type formed on the first semiconductor layer, a third semiconductor layer of the second conductivity type selectively formed on a surface of the second semiconductor layer, at least one trench formed in a periphery of the third semiconductor layer on the surface of the second semiconductor layer, a depth of a bottom surface of the at least one trench being deeper than a bottom surface of the third semiconductor layer, and shallower than a top surface of the first semiconductor layer, and some or all of the at least one trench being in contact with a side surface of the third semiconductor layer, at least one insulator buried in the at least one trench, a first main electrode electrically connected to the first semiconductor layer, and a second main electrode electrically connected to the third semico

Abstract: A Dual-directional Silicon Controlled Rectifier (DSCR) includes a substrate of a first conductivity type, a buried layer formed on the substrate and of a second conductivity type, a first well and a second well formed on the buried layer and of the first conductivity type, a third well formed between the first well and the second well and of the second conductivity type, and a doped region formed between a first semiconductor region and a third semiconductor region and of the second conductivity type. The doped region includes a part of the third well. The DSCR may regulate a breakdown voltage of a junction thereof. Therefore, when an I/O voltage of an Integrated Circuit (IC) is much higher than a working voltage, a false action may not occur.

Abstract: A semiconductor component includes a semiconductor body having a first side, a second side, an edge delimiting the semiconductor body in a lateral direction, an inner region and an edge region. A first semiconductor zone of a first conduction type is arranged in the inner region and in the edge region. A second semiconductor zone of a second conduction type is arranged in the inner region and adjacent to the first semiconductor zone. A trench is arranged in the edge region and has first and second sidewalls and a bottom, and extends into the semiconductor body. A doped first sidewall zone of the second conduction type is adjacent to the first sidewall of the trench. A doped second sidewall zone of the second conduction type is adjacent to the second sidewall of the trench. A doped bottom zone of the second conduction type is adjacent to the bottom of the trench. Doping concentrations of the sidewall zones are lower than a doping concentration of the bottom zone.

Abstract: A semiconductor device includes: a first insulating layer; a semiconductor layer provided on the first insulating layer; a first semiconductor region selectively provided in the semiconductor layer; a second semiconductor region selectively provided in the semiconductor layer and spaced from the first semiconductor region; a first main electrode provided in contact with the first semiconductor region; a second main electrode provided in contact with the second semiconductor region; a second insulating layer provided on the semiconductor layer; a first conductive material provided in the second insulating layer above a portion of the semiconductor layer located between the first semiconductor region and the second semiconductor region; and a second conductive material provided in a trench provided in a portion of the semiconductor layer opposed to the first conductive material, being in contact with the first conductive material, and reaching the first insulating layer.

Abstract: The first base electrodes and the first emitter electrodes are all formed like strips, and are alternately arranged in parallel, and the area of the second emitter electrode is expanded to be larger than that of the second base electrode. With this, the number of current paths increases in each of which a current is pulled up almost straight from the emitter region to the second emitter electrode through the first emitter electrodes, thereby preventing the current densities of the entire chip from becoming uneven.

Abstract: An integrated circuit containing an SCRMOS transistor. The SCRMOS transistor has one drain structure with a centralized drain diffused region and distributed SCR terminals, and a second drain structure with distributed drain diffused regions and SCR terminals. An MOS gate between the centralized drain diffused region and a source diffused region is shorted to the source diffused region. A process of forming the integrated circuit having the SCRMOS transistor is also disclosed.

Abstract: A single-photon detector is disclosed that provides reduced afterpulsing without some of the disadvantages for doing so in the prior art. An embodiment of the present invention provides a stimulus pulse to the active area of an avalanche photodetector to stimulate charges that are trapped in energy trap states to detrap. In some embodiments of the present invention, the stimulus pulse is a thermal pulse.

Abstract: A power semiconductor device that includes common conduction regions, charge compensation regions, each adjacent a respective common conduction region, and a stand off region over the common conduction regions and charge compensation regions.

Abstract: A protective structure is produced by providing a semiconductor substrate with a doping of a first conductivity type. A semiconductor layer with a doping of a second conductivity type is applied at a surface of the semiconductor substrate. A buried layer with doping of a second conductivity type is formed in a first region of the semiconductor layer, wherein the buried layer is produced at the junction between the semiconductor layer and semiconductor substrate. A first dopant zone with a doping of a first conductivity type is formed in the first region of the semiconductor layer above the buried layer. A second dopant zone with a doping of a second conductivity type is formed in a second region of the semiconductor layer. An electrical insulation is formed between the first region and the second region of the semiconductor layer. A common connection device is formed for the first dopant zone and the second dopant zone.

Abstract: A double-gate semiconductor device provides a high breakdown voltage allowing for a large excursion of the output voltage that is useful for power applications. The double-gate semiconductor device may be considered a double-gate device including a MOS gate and a junction gate, in which the bias of the junction gate may be a function of the gate voltage of the MOS gate. The breakdown voltage of the double-gate semiconductor device is the sum of the breakdown voltages of the MOS gate and the junction gate. Because an individual junction gate has an intrinsically high breakdown voltage, the breakdown voltage of the double-gate semiconductor device is greater than the breakdown voltage of an individual MOS gate. The double-gate semiconductor device provides improved RF capability in addition to operability at higher power levels as compared to conventional transistor devices.

Abstract: In the upper surface of a p? substrate, an n-type impurity region is formed. In the upper surface of the n-type impurity region, a p-well is formed. Also in the upper surface of the n-type impurity region, a p+-type source region and a p+-type drain region are formed. In the upper surface of the p-well, an n+-type drain region and an n+-type source region are formed. In the p? substrate, an n+ buried layer having an impurity concentration higher than that of the n-type impurity region is formed. The n+ buried layer is formed in contact with the bottom surface of the n-type impurity region at a greater depth than the n-type impurity region.

Abstract: A semiconductor device includes a semiconductor region having a pn junction and a field shaping region located adjacent the pn junction to increase the reverse breakdown voltage of the device. The field shaping region is coupled via capacitive voltage coupling regions to substantially the same voltages as are applied to the pn junction. When a reverse voltage is applied across the pn junction and the device is non-conducting, a capacitive electric field is present in a part of the field shaping region which extends beyond a limit of the pn junction depletion region which would exist in the absence of the field shaping region. The electric field in the field shaping region inducing a stretched electric field limited to a correspondingly stretched pn junction depletion region in the semiconductor region.

Abstract: A multiple layer overvoltage protection device is provided. The method begins by providing a substrate having a first impurity concentration of a first conductivity type to define a mid-region layer. A dopant of a second conductivity type is introduced into the substrate with a second impurity concentration less than the first impurity concentration. An upper base region having a second type of conductivity is formed on the upper surface of the mid-region layer. A lower base region layer having a second type of conductivity is formed on a lower surface of the mid-region layer. A first emitter region having a first type of conductivity is formed on a surface of the upper base region layer. A first metal contact is coupled to the upper base region layer and a second metal contact is coupled to the lower base region layer.

Abstract: The first base electrodes and the first emitter electrodes are all formed like strips, and are alternately arranged in parallel, and the area of the second emitter electrode is expanded to be larger than that of the second base electrode. With this, the number of current paths increases in each of which a current is pulled up almost straight from the emitter region to the second emitter electrode through the first emitter electrodes, thereby preventing the current densities of the entire chip from becoming uneven.

Abstract: A semiconductor device includes a semiconductor region having a pn junction and a field shaping region located adjacent the pn junction to increase the reverse breakdown voltage of the device. The field shaping region is coupled via capacitive voltage coupling regions to substantially the same voltages as are applied to the pn junction. When a reverse voltage is applied across the pn junction and the device is non-conducting, a capacitive electric field is present in a part of the field shaping region which extends beyond a limit of the pn junction depletion region which would exist in the absence of the field shaping region. The electric field in the field shaping region inducing a stretched electric field limited to a correspondingly stretched pn junction depletion region in the semiconductor region.

Abstract: In a semiconductor device of the present invention, a MOS transistor is disposed in an elliptical shape. Linear regions in the elliptical shape are respectively used as the active regions, and round regions in the elliptical shape is used respectively as the inactive regions. In each of the inactive regions, a P type diffusion layer is formed to coincide with a round shape. Another P type diffusion layer is formed in a part of one of the inactive regions. These P type diffusion layers are formed as floating diffusion layers, are capacitively coupled to a metal layer on an insulating layer, and assume a state where predetermined potentials are respectively applied thereto. This structure makes it possible to maintain current performance of the active regions, while improving the withstand voltage characteristics in the inactive regions.

Abstract: A semiconductor integrated circuit includes a plurality of circuit cells each including a pad on a semiconductor chip. Each of the circuit cells includes a high-side transistor, a level shift circuit, a low-side transistor, a pre-driver, and a pad. The high-side transistor and the low-side transistor are arranged to face each other with the pad interposed therebetween.

Abstract: A single-photon detector is disclosed that provides reduced afterpulsing without some of the disadvantages for doing so in the prior art. An embodiment of the present invention provides a stimulus pulse to the active area of an avalanche photodetector to stimulate charges that are trapped in energy trap states to detrap. In some embodiments of the present invention, the stimulus pulse is a thermal pulse.

Abstract: Electrostatic discharge (ESD) protection is provided for an integrated circuit. In an aspect, a dynamic region having doped regions is formed on an epitaxy layer and substrate, and interconnects contact the dynamic region. In an aspect, the dynamic region operates as a back-to-back SCR that snaps back in both positive and negative voltage directions. In an aspect the dynamic region operates as an SCR that snaps back in a positive voltage direction and operates as a simple diode in a negative voltage direction. In another aspect, the dynamic region operates as an SCR that snaps back in a negative voltage direction and operates as a simple diode in a positive voltage direction. ESD protection over an adjustable and wide positive and negative voltage range is provided by varying widths and positioning of various doping regions. Breakdown voltages, critical voltages and critical currents are independently controlled.

Abstract: Electrostatic discharge (ESD) protection is provided for an integrated circuit. Snap back from a lower initial critical voltage and critical current is provided, as compared to contemporary designs. A dynamic region having doped regions is formed on a substrate, interconnects contacting the dynamic region. The dynamic region includes an Nwell region, a Pwell region and shallow diffusions, defining a PNP region, an NPN region and a voltage Breakdown region. In an aspect, the Nwell region includes a first N+ contact, a first P+ contact and an N+ doped enhancement, while the Pwell region includes a second N+ contact, a second P+ contact and a P+ doped enhancement. The N+ doped enhancement contacts the P+ doped enhancement forming the breakdown voltage region therebetween, in one case forming a buried breakdown voltage junction.

Abstract: A drift diffusion layer of a low concentration is formed so as to surround a collector buffer layer having a relatively high concentration including a high-concentration collector diffusion layer in a plane structure. Thereby, current crowding in corner portions of the high-concentration collector diffusion layer is suppressed while maintaining a short turnoff time, and the improvement of breakdown voltage at on-time is realized.

Abstract: A semiconductor device, for example a diode (200), having a pn junction (101) has an insulating material field shaping region (201) adjacent, and possibly bridging, the pn junction. The field shaping region (201) preferably has a high dielectric constant and is coupled via capacitive voltage coupling regions (204,205) to substantially the same voltages as are applied to the pn junction. When a reverse voltage is applied across the pn junction (101) and the device is non-conducting, a capacitive electric field, is present in a part of the field shaping region which extends beyond a limit of the pn junction depletion region which would exist in the absence of the field shaping region (201), the electric field in the field shaping region inducing a stretched electric field limited to a correspondingly stretched pn junction depletion region (208,209) and an increased reverse breakdown voltage of the device.

Abstract: The present invention disclosed herein is a Vertical Double-Diffused Metal Oxide Semiconductor (VDMOS) device incorporating a reverse diode. This device includes a plurality of source regions isolated from a drain region. A source region in close proximity to the drain region is a first diffusion structure in which a heavily doped diffusion layer of a second conductivity type is formed in a body region of a second conductivity type. Another source region is a second diffusion structure in which a heavily doped diffusion layer of a first conductivity type and a heavily doped diffusion layer of the second conductivity type are formed in the body region of the second conductivity type. An impurity diffusion structure of the source region in close proximity to the drain region is changed to be operated as a diode, thereby forming a strong current path to ESD (Electro-Static Discharge) or EOS (Electrical Over Stress). As a result, it is possible to prevent the device from being broken down.

Abstract: Electrostatic discharge (ESD) protection is provided for an integrated circuit. In an aspect, a dynamic region having doped regions is formed on an epitaxy layer and substrate, and interconnects contact the dynamic region. In an aspect, the dynamic region operates as a back-to-back SCR that snaps back in both positive and negative voltage directions. In an aspect the dynamic region operates as an SCR that snaps back in a positive voltage direction and operates as a simple diode in a negative voltage direction. In another aspect, the dynamic region operates as an SCR that snaps back in a negative voltage direction and operates as a simple diode in a positive voltage direction. ESD protection over an adjustable and wide positive and negative voltage range is provided by varying widths and positioning of various doping regions. Breakdown voltages, critical voltages and critical currents are independently controlled.

Abstract: An ESD protection circuit using a double-triggered silicon controller rectifier (SCR). The double-triggered silicon controller rectifier (SCR) includes N+ diffusion areas, P+ diffusion areas, a first N-well region, a second N-well region and a third N-well region formed in a P-substrate. The N+ diffusion areas and the P+ diffusion areas are isolated by shallow trench isolation (STI) structures. Two of the N+ diffusion areas are N-type trigger terminals. Two of the P+ diffusion areas are the P-type trigger terminal.

Abstract: A surface-emitting type device includes a substrate including a first face, a second face that is tilted with respect to the first face and has a plane index different from a plane index of the first face, and a third face that is tilted with respect to the second face and has a plane index equal to the plane index of the first face, an emission section formed above the first face, and a rectification section formed above each of the second face and the third face, wherein the emission section includes a first semiconductor layer of a first conductivity type, an active layer formed above the first semiconductor layer, and a second semiconductor layer of a second conductivity type formed above the active layer, the rectification section includes a first semiconductor layer of the second conductivity type formed above the second face, and a second semiconductor layer of the first conductivity type formed continuously with the first semiconductor layer above the third face, at least a portion of the first semico

Abstract: An ion-through region 100, 102 is provided as a first opening in a passivation film 90 on a source electrode 70 and a drain electrode 80. The passivation film 90 is coated with a sealing resin to package the semiconductor device. At this point, the ion-through region 100, 102 is filled with the sealing resin to put the sealing resin into direct contact with the source electrode 70 and the drain electrode 80. With this structure, movable ions accumulated at an interface of the sealing resin with the passivation film 90 in a high temperature and high humidity atmosphere are discharged to the source electrode 70 and the drain electrode 80 via the ion-through region 100, 102 and thus do not influence an N?-type extended drain region 30. Therefore, the drain breakdown voltage can be improved.

Abstract: An electric contact member which is excellent in voltage-proof performance and melt-resistant performance and excellent in mass productivity, and a method of manufacturing thereof, and a vacuum interrupter, a vacuum circuit breaker and a load-break switch for a road side transformer using thereof. The contact member is composed of a base member made of high conductive metal, and a contact layer made of refractory metal and high conductive metal, and the contact layer is formed of a plurality of thermal sprayed layers.

Abstract: A method of patterning and releasing chemically sensitive low k films without the complication of a permanent hardmask stack, yielding an unaltered free-standing structure is provided. The method includes providing a structure including a Si-containing substrate having in-laid etch stop layers located therein; forming a chemically sensitive low k film and a protective hardmask having a pattern atop the structure; transferring the pattern to the chemically sensitive low k film to provide an opening that exposes a portion of the Si-containing substrate; and etching the exposed portion of the Si-containing substrate through the opening to provide a cavity in the Si-containing substrate in which a free-standing low k film structure is formed, while removing the hardmask. In accordance with the present invention, the etching comprises a XeF2 etch gas.