Abstract: A semiconductor memory device includes: a memory cell including a first cell that stores data, and a second cell that stores complementary data that is complementary to the data; a redundant memory cell including a third cell that stores margined complementary data in which a margin is added to the complementary data, and a fourth cell that stores margined data in which a margin is added to the data; and a controller that causes the data and the margined complementary data to be compared and a test of the first cell to be executed, and the complementary data and the margined data to be compared and a test of the second cell to be executed.

Abstract: A power supply device includes a transformer, a primary semiconductor component, a secondary semiconductor component, a choke coil and a circuit board. Electronic components which include the transformer, the primary semiconductor component, the secondary semiconductor component, and the choke coil, are stacked in pairs, in a normal direction of a board. One pair forms a first stacked body and another pair to forms a second stacked body. A circuit board is interposed between the one pair of electronic components which forms the first stacked body, and also between the other pair of electronic components which forms the second stacked body.

Abstract: A semiconductor device includes a trench-gate IGBT enabling the fine adjustment of a gate capacitance independent from cell performance. In a gate wiring lead-out region, a plurality of trenches is arranged spaced apart from each other in an X direction perpendicular to a Y direction. Each trench has a shape enclosed by a rectangular outer outline and a rectangular inner outline in plan view. A trench gate electrode is provided in each of the trenches so as to be electrically coupled to an extraction electrode. To obtain an adequate breakdown voltage between a collector and an emitter, the trenches are formed in a p-type floating region. An n?-type drift region is formed in a region located inside an inner outline of the trench in plan view, whereby a capacitance formed between the trench gate electrode and the n?-type drift region is used as the reverse transfer capacitance.

Abstract: Embodiments of the present invention provide for the enhancement of transistors in a semiconductor structure using a strain layer. The structure comprises a patterned layer consisting of an excavated region and a pattern region, a strain layer located in the excavated region and on the pattern region, an active layer located above the strain layer, a field effect transistor formed in the active layer, and a handle layer located above the active layer. The field effect transistor comprises a source, a drain, and a channel. The channel lies completely within a lateral extent of the pattern region. The source and the drain each lie only partially within the lateral extent of the pattern region. The strain layer alters a carrier mobility of the channel. In some embodiments, the strain layer is introduced to the back side of a semiconductor-on-insulator structure.

Abstract: A flexible film includes a base film including an edge portion which extends in a first direction, a plurality of wirings disposed on the base film, and a plurality of pads which is disposed in the edge portion of the base film and connected to the plurality of wirings. The plurality of pads disposed in the edge portion include a plurality of horizontal pads horizontally arranged in the first direction to define a pad row extended in the first direction; and a vertical pad including a plurality of vertically arranged pads arranged in a second direction perpendicular to the first direction, within a same pad row in which the plurality of horizontal pads are horizontally arranged.

Abstract: The present disclosure discloses an organic light emitting diode substrate, comprising: a base substrate and a device layer formed in a middle part thereon, a region on the base substrate other than the device layer being divided into an inner ring region that surrounds the device layer and an outer ring region outside the inner ring region; a first adhesive layer adhered on the device layer and the inner ring region and covering the device layer and the inner ring region, the first adhesive layer being used to block moisture and oxygen for the device layer; a second adhesive frame adhered on the outer ring region and the first adhesive layer and covering a portion of the first adhesive layer over the inner ring region, the second adhesive frame having a higher adhesive strength than the first adhesive layer.

Abstract: A digital-drive display system, comprising an array of display pixels, each display pixel having a light emitter, a digital memory for storing a digital pixel value, and a drive circuit that drives the light emitter in response to the digital pixel value. The drive circuit can respond to a control signal provided to all of the display pixels in common by a display controller that loads digital pixel values in the digit memory of each display pixel.

Abstract: Some embodiments include a memory cell having first and second transistors and first and second capacitors. The first capacitor is vertically displaced relative to the first transistor. The first capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a common plate structure, and a first capacitor dielectric material between the first and second nodes. The second capacitor is vertically displaced relative to the second transistor. The second capacitor has a third node electrically coupled with a source/drain region of the second transistor, a fourth node electrically coupled with the common plate structure, and a second capacitor dielectric material between the first and second nodes. Some embodiments include memory arrays having 2T-2C memory cells.

Abstract: In a bipolar transistor, a collector layer includes three semiconductor layers: an n-type GaAs layer (Si concentration: about 5×1015 cm?3, thickness: about 350 nm), a p-type GaAs layer (C concentration: about 4.5×1015 cm?3, thickness: about 100 nm, sheet concentration: 4.5×1010 cm?2), and an n-type GaAs layer Si concentration: about 5×1015 cm?3, thickness: about 500 nm. The sheet concentration of the p-type GaAs layer is set to less than 1×1011 cm?2.

Abstract: The present invention relates to methods and systems for cell lysis in a microfluidic device. More specifically, embodiments of the present invention relate to methods and systems for rapid continuous flow mechanical cell lysis. In one embodiment, a microfluidic device includes one or more microfluidic channels, each channel comprising constricted regions and non-constricted regions separating the constricted regions, wherein the constricted regions are configured to disrupt the cellular membranes of cells in fluid flowing through the one or more microfluidic channels.

Abstract: A method for manufacturing semiconductor device includes depositing a contact metal layer over a III-V compound layer. An anti-reflective coating (ARC) layer is deposited over the contact metal layer, and an etch stop layer is deposited over the ARC layer. The etch stop layer, the ARC layer, and the contact metal layer are etched to form a contact stack over the III-V compound layer. A conductive layer is deposited over the III-V compound layer, and the conductive layer is etched to form a gate field plate. The etch stop layer has an etch selectivity different from that of the conductive layer.

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having a shared SRAM trench and a common contact having a low contact resistance. The method includes forming a first semiconductor fin opposite a surface of a substrate and forming a second semiconductor fin opposite the surface of the substrate and adjacent to the first semiconductor fin. A doped region is formed over portions of each of the first and second semiconductor fins and a dielectric layer is formed over the doped regions. A shared trench is formed in the dielectric layer exposing portions of the doped regions. The exposed doped regions are then amorphized and recrystallized.

Abstract: When an optical waveguide is formed, an area of an opening of a resist mask is equal to an area of a semiconductor layer for a dummy pattern exposed from the resist mask, and the semiconductor layer for the dummy pattern exposed from the resist mask has a uniform thickness in a region in which the dummy pattern is formed. As a result, an effective pattern density does not change in etching the semiconductor layer for the dummy pattern, and accordingly, it is possible to form a rib-shaped optical waveguide having desired dimensions and a desired shape.

Abstract: A hetero-integrated device includes a monocrystalline Si substrate and a trench formed in the substrate to expose a crystal surface at a bottom of the trench. Sidewall dielectric spacers are formed on sidewalls of the trench, and a III-V material layer is formed on the crystal surface at the bottom of the trench and is isolated from the sidewalls of the trench by the sidewall dielectric spacers.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor wafers with reduced bowing and warping and methods of manufacture. The structure includes a substrate including plurality of trenches which have progressively different depths as they extend radially inwardly from an edge of the substrate towards a center of the substrate.

Abstract: A display device includes: an organic electroluminescent element; a capacitor; a drive transistor; a data line; a test transistor which switches between conduction and non-conduction between the data line and an anode electrode of the organic electroluminescent element; a voltage generation unit which supplies the data line with a test voltage for measuring an anode voltage of the organic electroluminescent element; a current detection unit which detects a current through the test transistor when a test transistor is in a conducting state, while the voltage generation unit is applying the test voltage to the data line; a control unit which updates the voltage value of the test voltage, based on a direction of the current detected by the current detection unit, and causes the voltage generation unit to output the updated test voltage.

Abstract: Embodiments relate to use of a particle accelerator beam to form thin films of material from a bulk substrate. In particular embodiments, a bulk substrate (e.g. donor substrate) having a top surface is exposed to a beam of accelerated particles. In certain embodiments, this bulk substrate may comprise GaN; in other embodiments this bulk substrate may comprise Si, SiC, or other materials. Then, a thin film or wafer of material is separated from the bulk substrate by performing a controlled cleaving process along a cleave region formed by particles implanted from the beam. In certain embodiments this separated material is incorporated directly into an optoelectronic device, for example a GaN film cleaved from GaN bulk material. In some embodiments, this separated material may be employed as a template for further growth of semiconductor materials (e.g. GaN) that are useful for optoelectronic devices.

Abstract: Method including the steps of a) Providing a first stack including a first substrate on which is deposited a first metal layer including a first metal, and a first solubilization layer distinct from the first metal layer, the first solubilization layer including a first getter material configured to solubilize the oxygen, b) Providing a second stack including a second substrate on which is deposited a second metal layer including a second metal, c) Contacting the first metal layer and the second metal layer so as to obtain a direct metal bonding between the first metal layer and the second metal layer, and d) Applying a heat treatment for annealing the bonding.

Abstract: Provided is a semiconductor device including a MOS analog circuit which has a high reliability and a low manufacturing cost, and in which latent failure is easily detected. The MOS analog circuit is switched to a test state or an operating state based on a control signal that is externally supplied. In the test state, a voltage between a power supply terminal and a reference terminal is applied to a gate oxide film of a MOS transistor included in the MOS analog circuit.

Abstract: Sensor devices and methods are provided where a second magnetoresistive sensor stack is provided on top of a first magnetoresistive sensor stack.

Abstract: Disclosed herein are technologies for forming a plurality of known good die (KGD)-light emitting diode (LED) components into a larger size optically coherent LED chips or devices. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is coupled to a rectifying device to prevent parallel leak current from flowing through non-selected memory cells. In an array of resistive memory bit structures, resistive memory cells from different memory bit structures are stacked and share rectifying devices.

Abstract: The present disclosure relates to an image sensor integrated chip having a grid structure that reduces crosstalk between pixel regions of an image sensor chip. In some embodiments, the integrated chip has an image sensing element arranged within a substrate. An absorption enhancement structure is disposed along the back-side of the substrate. A grid structure is arranged over the absorption enhancement structure. The grid structure defines an opening arranged over the image sensing element and extends from over the absorption enhancement structure to a location within the absorption enhancement structure. By having the grid structure extend into the absorption enhancement structure, the grid structure is able to reduce crosstalk between adjacent image sensing elements by blocking radiation reflected off of non-planar surfaces of the absorption enhancement structure from traveling to an adjacent pixel region.

Abstract: A FET device includes a substrate having top and bottom surfaces, a channel layer on the top surface of the substrate; the channel layer having top and bottom surfaces, at least two recesses extending into the channel layer from the top surface of the channel layer and forming a channel region between the at least two recesses, a gate electrode disposed in each of the at least two recesses, and a drain region and a source region formed in the channel layer on opposite sides of said channel region.

Abstract: A method for forming fins on a semiconductor device includes etching trenches into a monocrystalline substrate to form first fins and forming a first dielectric layer at bottoms of the trenches. Second fins of a material having a different composition than the substrate are grown on sidewalls of the trenches. A second dielectric layer is formed over the second fins. The first fins are removed by etching. The second fins are processed to form fin field effect transistor devices.

Abstract: After forming a trench extending through a (100) silicon layer and a buried insulator layer and into a (111) silicon layer of a semiconductor-on-insulator (SOI) substrate, and prior to epitaxial growth of a Group III nitride material from a sub-surface of the (111) silicon layer that is exposed by the trench, a first sidewall spacer including a first dielectric material that can effectively prevent Group III elements from diffusing into silicon of the SOI substrate during the high temperature epitaxial growth of the Group III nitride materials is formed on sidewalls of the trench, following by forming a second sidewall spacer on the first sidewall spacer. The second sidewall spacer includes a second dielectric material that provides better growth selectivity towards the Group III nitride material than the first dielectric material, thus facilitating the growth of the Group III nitride material from the sub-surface of the (111) silicon layer.

Abstract: A magnetic tunnel junction device and a manufacturing method therefor are provided. The magnetic tunnel junction device comprises: a seed layer having an FCC (001) crystal structure; a first ferromagnetic layer located on the seed layer and having perpendicular magnetic anisotropy; a tunneling barrier layer located on the first ferromagnetic layer; and a second ferromagnetic layer located on the tunneling barrier layer and having perpendicular magnetic anisotropy, wherein the first ferromagnetic layer has a BCC (001) crystal structure and does not have boron. Therefore, the magnetic tunnel junction device, which is structurally and thermally more stable, can be provided by using the seed layer configured to assist the crystal growth of a boron-free magnetic layer in a BCC (001) direction and provide perpendicular magnetic anisotropy thereto, that is, W2N or TaN which is a nitrogen-doped metal material having a cubic crystal structure and having a similar lattice constant to that of a magnetic layer material.

Abstract: The disclosed subject matter provides a mask read-only memory (M-ROM) device and fabrication method thereof. In an M-ROM device, a first layer having a first type doping is formed in a substrate. A plurality of buried lines is formed in the first layer of the substrate. The plurality of buried lines are arranged in parallel in a first direction and isolated from each other. An epitaxial growth process is used to form a second layer on the first layer of the substrate. A plurality of diodes is formed in the second layer. The plurality of diodes is arranged in an array. Each diode includes a first electrode having a second type doping and connecting with one of the plurality of buried lines, and a second electrode having a first type doping and located on the first electrode.

Abstract: A flexible display and a method of manufacturing the same are disclosed. In one aspect, the flexible display includes a flexible display panel including an active area configured to display an image and an inactive area surrounding the active area. The flexible display also includes a plurality of wires formed over the flexible display panel in the inactive area and configured to transmit an electric signal to the active area. The inactive area includes a plurality of edges that are bent with respect to the active area of the flexible display panel. A bending hole is formed at each corner where two adjacent edges of the flexible display panel meet and each of the corners is folded so as to define a folding region.

Abstract: An optical functional device includes: a photodetector; a first optical waveguide which is connected to one end face of the photodetector; and a second optical waveguide which is connected to the other end face of the photodetector. The photodetector is formed in a multi-mode interferometer and has electrodes. Light input from the first optical waveguide to the photodetector focuses image at a position physically away from the second optical waveguide, and light input from the second optical waveguide to the photodetector focuses image at a position physically away from the first optical waveguide.

Abstract: A test pad structure includes a plurality of test pads and a plurality of connection leads. The test pads are sequentially arranged from a wiring pattern on a substrate and in rows parallel with one another. The test pads include first and second groups of test pads, the first group having at least one pad and the second group having at least two pads. The connection leads extend from end portions of the wiring pattern to be connected to the test pads. The connection leads include at least one inner lead passing between the at least two pads of the second group and arranged in a first row closest to the first group. The at least one inner lead may be connected to at least one pad of the at least two pads of the second group arranged in a second row next to the first row.

Abstract: A system for detecting electrical properties of a molecular complex is disclosed. The system includes an electrode electrically coupled to a molecular complex that outputs an electrical signal affected by an electrical property of the molecular complex, wherein the effect of the electrical property of the molecular complex on the electrical signal is characterized by an expected bandwidth. The system further includes an integrating amplifier circuit configured to: receive the electrical signal from the electrode. The integrating amplifier circuit is further configured to selectively amplify and integrate a portion of the electrical signal over time within a predetermined bandwidth, wherein the predetermined bandwidth is selected at least in part based on the expected bandwidth.

Abstract: A vertical-type memory device may include a channel layer vertically extending on a substrate, a ground selection transistor at a side of the channel layer on the substrate, the ground selection transistor including a first gate insulation portion and a first replacement gate electrode, an etch control layer on the first replacement gate electrode, and a memory cell on the etch control layer, the memory cell including a second gate insulation portion and a second replacement gate electrode. The etch control layer may include a polysilicon layer doped with carbon, N-type impurities, or P-type impurities, or may include a polysilicon oxide layer comprising carbon, N-type impurities, or P-type impurities. A thickness of the first replacement gate electrode may be the same as a thickness of the second replacement gate electrode, or the first replacement gate electrode may be thicker than the second.

Abstract: Some embodiments are directed to a bipolar junction transistor (BJT) with a collector region formed within a body of a semiconductor substrate, and an emitter region arranged over an upper surface of the semiconductor substrate. The BJT includes a base region arranged over the upper surface of the semiconductor substrate, which vertically separates the emitter and collector regions. The base region is arranged within, and in contact with, a conductive base layer, which delivers current to the base region. The base region includes a planar bottom surface, which increases contact area between the base region and the semiconductor substrate, thus decreasing resistance at the collector/base junction, over some conventional approaches. The base region can also include substantially vertical sidewalls, which increases contact area between the base region and the conductive base layer, thus improving current delivery to the base region.

Abstract: A display panel is provided. The display panel includes a first sub-pixel row including a plurality of sub-pixels electrically connecting to a scan line; and a second sub-pixel row including a plurality of sub-pixels, wherein the scan line overlaps with an area of the sub-pixels of the second sub-pixel row, and the scan line overlaps with an edge of a first sub-pixel of the sub-pixels of the first sub-pixel row, wherein the edge is adjacent to a driving transistor of the first sub-pixel.

Abstract: A GOA circuit and an LCD device. The GOA circuit includes multiple cascaded GOA units, and each includes a transferring circuit, a latch circuit and an output circuit. In a forward scanning, the transferring circuit receives a (N?1)th stage-transfer signal of a (N?1)th stage, and sending to the latch circuit. In a backward scanning, the transferring circuit receives a (N+1)th stage-transfer signal of a (N+1)th stage, and sending to the latch circuit. In the canning period, the latch circuit receives a first clock signal and a second clock signal simultaneously, and outputs an Nth stage-transfer signal the same as the first clock signal and opposite to the second clock signal. The output circuit receives the Nth stage-transfer signal, and outputs an Nth scanning signal the same as the Nth stage-transfer signal. The present invention utilizes two clock signals to commonly drive the GOA circuit to improve the stability.

Abstract: When a clock signal pulse number and a compensation-target-line address indicating a compensation-target row match, the following control is carried out with a time point being a starting point of a current measurement period, the time point being one horizontal scanning period after a time point of the match. At a current measurement period starting point and ending point, only the potential of the one of the clock signals applied to a unit circuit corresponding to the compensation-target row is changed. Throughout the current measurement period, the clock operation of the clock signals is stopped. A monitor enable signal, that is applied to a control terminal of an output control transistor for controlling active signal output to a monitor control line, is only set to a high level during the current measurement period.

Abstract: The steps of preparing a silicon carbide layer having a main surface, forming on the main surface, a first mask layer located on a first region to be a channel region and having a first opening portion on each of opposing regions with the first region lying therebetween, and forming a high-concentration impurity region having a first conductivity type and being higher in impurity concentration than the silicon carbide layer in a region exposed through the first opening portion, by implanting ions into the main surface with the first mask layer being interposed are included.

Abstract: A semiconductor device includes an interlayer dielectric on a semiconductor substrate, a contact plug penetrating the interlayer dielectric, a pillar pattern disposed on the interlayer dielectric and having a central axis laterally offset from a central axis of the contact plug, a pad extending on the contact plug and along a sidewall of the pillar pattern, the pad being electrically connected to the contact plug, and a data storage portion on the pillar pattern and electrically connected to the pad.

Abstract: The invention discloses a substrate with high fracture strength. The substrate according to the invention includes a plurality of nanostructures. The substrate has a first surface, and the nanostructures are protruded from the first surface. By the formation of the nanostructures, the fracture strength of the substrate is enhanced.

Abstract: A test structure and method to detect open circuits due to electromigration or burn-out in test wires and inter-level vias. Electromigration occurs when current flows through circuit wires leading to a circuit interruption within the wire. The test structure is a passive test wire arranged in one of several configurations within the circuit of a computer chip. The dimensions and resistances of test wires can vary according to the test structure configuration. Each test wire is measured for an electrical discontinuity after the computer chip is powered-on. If a wiring interruption is detected, it is concluded that the chip had been powered-on before.

Abstract: Multi-layer fin field effect transistor devices and methods of forming the same are provided. The devices may include a fin shaped channel structure on a substrate. The channel structure may include stressor layers stacked on the substrate and a channel layer between the stressor layers, and the stressor layers may include a semiconductor material having a wide bandgap that is sufficient to confine carriers to the channel layer and having a lattice constant different from a lattice constant of the channel layer to induce stress in the channel layer. The devices may also include source/drain regions on respective first opposing sides of the channel structure and a gate on second opposing sides of the channel structure and between the source/drain regions.

Abstract: A method for integrating fin field effect transistors (FinFETs) and resistors on a common substrate is provided. By employing a digital alloy as a channel material for each FinFET and as a resistor body for each resistor, FinFETs with improved charge carrier mobility, and resistors with good temperature coefficient of resistance are obtained.

Abstract: A power semiconductor device includes a wiring structure adjoining at least one side of a semiconductor body and comprising at least one electrically conductive compound. The power semiconductor device further includes a cooling material in the wiring structure. The cooling material is characterized by a change in structure by means of absorption of energy at a temperature TC ranging between 150° C. and 400° C.

Abstract: An organic light-emitting diode includes a carrier substrate, a scattering layer, a first electrode, an organic layer sequence with at least one active layer, and a second electrode wherein all the components are arranged in the stated sequence, the scattering layer has a higher average refractive index than the organic layer sequence, the first electrode has at least n or at least n+1 non-metal layers and n metal layers, n is a natural number greater than or equal to 1 or greater than or equal to 2, and the non-metal layers and the metal layers succeed one another alternately.

Abstract: A fin is formed over a first barrier layer over a substrate. The first barrier layer has a band gap greater than the band gap of the fin. In one embodiment, a gate dielectric layer is deposited on the top surface and opposing sidewalls of the fin and is adjacent to a second barrier layer deposited on the first barrier layer underneath the fin. In one embodiment, the gate dielectric layer is deposited on the top surface and the opposing sidewalls of the fin and an isolating layer is formed adjacent to the first barrier layer underneath the fin. In one embodiment, the gate dielectric layer is deposited on the top surface and the opposing sidewalls of the fin, and an isolating layer is formed adjacent to the second barrier layer deposited between the fin and the first barrier layer.

Abstract: Embodiments of the present disclosure include a MISFET device. An embodiment includes a source/drain over a substrate, a first etch stop layer on the source/drain, and a gate dielectric layer on the first etch stop layer and along the substrate. The embodiment also includes a gate electrode on the gate dielectric layer, and a second etch stop layer on the gate electrode.

Abstract: Provided are a light-emitting diode which prevents degradation of reflectance and which enables high-luminosity light emission, and its manufacturing method. Such a light-emitting diode includes a substrate (1) upon which are provided, in this order, a reflecting layer (6), a transparent film (8) wherein multiple ohmic contact electrodes (7) are embedded at intervals, and a compound semiconductor layer (10) including a current diffusion layer (25) and a light-emitting layer (24) in this order. The periphery of the surface of each ohmic contact electrode (7) on the substrate (1) side are covered by the transparent film (8), and the ohmic contact electrodes (7) contact the reflecting layer (6) and the current diffusion layer (25).

Abstract: A method for producing an array or bed of metallic nanotubes includes formation of nanowires made from sacrificial material on a growth support, deposition of a metal layer on the nanowires so as to form metallic nanotubes concentric with the nanowires, deposition of a polymer binding layer between the nanowires, elimination of the support, the binding layer supporting the metallic nanotubes, and etching of the sacrificial material.

Abstract: A method of manufacturing a semiconductor device includes etching a recess into a substrate and epitaxially growing a source/drain region in the recess. The source/drain region includes a first undoped layer of stressor material lining the recess, a lightly doped layer of stressor material over the first undoped layer, a second undoped layer of stressor material over the lightly doped layer, and a highly doped layer of stressor material over the second undoped layer.