Abstract: A semiconductor memory device in an embodiment includes a semiconductor layer, a control gate electrode, an organic molecular layer provided between the semiconductor layer and the control gate electrode, and a first insulating layer provided between the organic molecular layer and the semiconductor layer, the first insulating layer having a first layer containing alkyl chains and a second layer containing siloxane, the second layer being provided between the first layer and the organic molecular layer.

Abstract: A method and structure for integrating gallium nitride into a semiconductor substrate. The method may also include means for isolating the gallium nitride from the semiconductor substrate.

Abstract: Method for forming a through semiconductor via (TSV) in a semiconductor wafer comprising: etching an annular recess into a front side of the semiconductor wafer, the annular recess surrounding a pillar of the semiconductor material; filling the annular recess with an insulative material to form an insulative annulus; etching a recess into the front side in the pillar of the semiconductor material; filling the recess in the portion of the semiconductor material with a metal to form a through semiconductor via (TSV); thinning the semiconductor wafer from a backside of the semiconductor wafer and stopping on the insulative annulus to expose the pillar of the semiconductor material; recessing the pillar of the semiconductor material from the back side to form a recess that exposes an end of the TSV; and filling the recess with a metal to a level at least even with a level of the insulative annulus.

Abstract: A flexible display includes a flexible base substrate, a thin film transistors layer formed on the flexible base substrate, and a light emitting elements layer formed on the thin film transistors layer, where the flexible base substrate includes a first support layer formed below the thin film transistors layer, a second support layer disposed below the first support layer, and a heat-energy blocking/reflecting layer provided between the first support layer and the second support layer. The heat-energy blocking/reflecting layer is configured to block or reflect a sufficient portion of radiated heat-energy that is generated when the flexible base substrate is separated from a supporting carrier substrate so as to prevent the damage from the radiated heat-energy to the light emitting elements layer.

Abstract: A method of fabricating a microelectronic unit includes providing a semiconductor element having a front surface and a rear surface remote from the front surface, forming at least one first opening extending from the rear surface partially through the semiconductor element towards the front surface by directing a jet of fine abrasive particles towards the semiconductor element, and forming at least one conductive contact and at least one conductive interconnect coupled thereto. The semiconductor element can include a plurality of active semiconductor devices therein. The semiconductor element can include a plurality of conductive pads exposed at the front surface. Each conductive interconnect can extend within one or more of the first openings and can be coupled directly or indirectly to at least one of the conductive pads. Each of the conductive contacts can be exposed at the rear surface of the semiconductor element for electrical connection to an external device.

Abstract: A semiconductor device and a method for fabricating the device are provided. The semiconductor device has a substrate having a first device region and a second device region. A p-type fin field effect transistor is formed in the first device region. The p-type fin field effect transistor has a first fin structure comprised of a first semiconductor material. An n-type fin field effect transistor is formed in the second device region. The n-type fin field effect transistor has a second fin structure comprised of a second semiconductor material that is different than the first semiconductor material. To fabricate the semiconductor device, a substrate having an active layer present on a dielectric layer is provided. The active layer is etched to provide a first region having the first fin structure and a second region having a mandrel structure. The second fin structure is formed on a sidewall of the mandrel structure.

Abstract: A light emitting structure includes lower and upper semiconductor layers having different conductive types, and an active layer disposed between the lower and upper semiconductor layers. The light emitting structure is provided on the substrate. A first electrode layer provided on the upper semiconductor layer includes a first adhesive layer and a first bonding layer overlapping each other. A reflective layer is not provided between the first adhesive layer and the first bonding layer.

Abstract: Disclosed is a method for manufacturing a solar cell module (10), said method being provided with: a first step for a first step for manufacturing a laminated body by sequentially stacking and thermocompression-bonding a solar cell (11), sealing material (14), first protection member (12) and second protection member (13); and a second step, which is a step of heating the solar cell (11) of the laminated body, and in which the sealing material (14) is indirectly heated due to a temperature increase of the solar cell (11).

Abstract: In an active region, p+ regions are selectively disposed in a surface layer of an n? drift layer on an n+ semiconductor substrate. A p-base layer is disposed on surfaces of the n? drift layer and the P+ regions, and an MOS structure is disposed on the p-base layer. In another portion of the active region, a p+ region is disposed to be in contact with the source electrode on the p+ regions. In a breakdown voltage structure region (100), a JTE structure having at least a P? region is disposed separately from the P+ regions and the p-base layer, to surround the active region. The P? region is electrically in contact with the P+ region in a portion in which the MOS structure is not formed, in the vicinity of the boundary between the active region and the breakdown voltage structure region.

Abstract: [It is an object] to provide an organic electroluminescent element having a transparent electrode, with which there is no need to produce a separate light extraction layer, [which can be produced by] a simple film formation process, and which is advantageous in terms of cost. [This is] an organic electroluminescent element in which a substrate, a first transparent electrode that is adjacent to this substrate, an organic layer including at least one organic light-emitting layer, a second transparent electrode, a low refractive-index layer with a refractive index of 1.3 or less, and a reflector layer are formed in this order, with this organic electroluminescent element being such that the aforementioned first transparent electrode contains at least one type of transparent particle with a primary particle size of 0.5 ?m or more.

Abstract: A bank partitions a plurality of pixels and has an opening in each of the plurality of pixels. An organic layer includes a light emitting layer, and covers the bank opening. A first inorganic barrier layer is formed of an inorganic material, and covers the bank and the organic layer. A plurality of organic barrier portions are formed of organic materials, and are disposed on the first inorganic barrier layer. A second inorganic barrier layer is formed of the inorganic material, and covers the first inorganic barrier layer and the plurality of organic barrier portions. A recessed portion is formed on the bank and the first inorganic barrier layer (for example, the recessed portion is formed in an area which covers a contact hole), and a portion of the organic barrier portion is formed in the recessed portion.

Abstract: There is herein described electronic components with improved display contrast and a method of manufacturing such electronic components. More particularly, there is described electronic components having improved display contrast by using a non-transparent or substantially non-transparent material (520) to block light from an emitter source (512, 514, 516) to surrounding components such as emitters, sensors or components of this nature.

Abstract: A semiconductor device includes a substrate, a III-nitride buffer layer on the substrate, an N-channel transistor including a III-nitride N-channel layer on one portion of the buffer layer, and a III-nitride N-barrier layer for providing electrons on top of the N-channel layer, wherein the N-barrier layer has a wider bandgap than the N-channel layer, a P-channel transistor including a III-nitride P-barrier layer on another portion of the buffer layer for assisting accumulation of holes, a III-nitride P-channel layer on top of the P-barrier layer, wherein the P-barrier layer has a wider bandgap than the P-channel layer, and a III-nitride cap layer doped with P-type dopants on top of the P-channel layer.

Abstract: A display substrate and a method of manufacturing a display substrate are disclosed. The display substrate includes an active pattern, a first gate electrode and a second gate electrode. The active pattern is disposed on a base substrate. The first gate electrode overlaps the active pattern. The first gate electrode is spaced apart from the active pattern by a first distance. The second gate electrode overlaps the active pattern. The second gate electrode is spaced apart from the active pattern by a second distance which is larger than the first distance.

Abstract: Technology capable of improving performance of a phase-change memory is provided. A recording/reproducing film contains Sn (tin), Sb (antimony), and Te (tellurium) and also contains an element X having a bonding strength with Te stronger than a bonding strength between Sn and Te and a bonding strength between Sb and Te. Here, the recording/reproducing film has a (SnXSb)Te alloy phase, and this (SnXSb)Te alloy phase includes a self-assembled superlattice structure.

Abstract: Provided is an organic electroluminescent device including, in an order mentioned: a reflective electrode; an organic electroluminescent layer; a light extraction layer; and a transparent substrate, wherein a ratio (w/d) is 9 or more where “d” denotes a total average thickness from the organic electroluminescent layer to the transparent substrate and “w” denotes a minimum width of a non-light-emitting region present outside of an outer periphery of an effective light-emitting region in the organic electroluminescent layer.

Abstract: A method of epitaxially growing nitrogen-based compound semiconductor thin films on a semiconductor substrate, which is periodically patterned with grooves. The method can provide an epitaxial growth of a first crystalline phase epitaxial film on the substrate, and block the growth of an initial crystalline phase with barrier materials prepared at the sides of the grooves. Semiconductor devices employing the epitaxial films are also disclosed.

Abstract: An electrical device including a plurality of fin structures. The plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures. The decoupling capacitor is present underlying the power line to the semiconductor fin structures.

Abstract: Embodiments of the present disclosures are directed to improved approaches for achieving high-performance light extraction from a Group III-nitride volumetric LED chips. More particularly, disclosed herein are techniques for achieving high-performance light extraction from a Group III-nitride volumetric LED chip using surface and sidewall roughening.

Abstract: According to one embodiment, a nonvolatile variable resistance element includes a first electrode, a second electrode, a variable resistance layer, and a dielectric layer. The second electrode includes a metal element. The variable resistance layer is arranged between the first electrode and the second electrode. A resistance change is reversibly possible in the variable resistance layer according to move the metal element in and out. The dielectric layer is inserted between the second electrode and the variable resistance layer and has a diffusion coefficient of the metal element smaller than that of the variable resistance layer.

Abstract: A high electron mobility field effect transistor (HEMT) having a substrate, a channel layer on the substrate and a barrier layer on the channel layer includes a stress inducing layer on the barrier layer, the stress inducing layer varying the piezo-electric effect in the barrier layer in a drift region between a gate and a drain. A two dimensional electron gas (2DEG) has a non-uniform lateral distribution in the drift region between the gate and the drain.

Abstract: A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited over sidewalls of a fin including the graded III-N semiconductor channel allowing for formation of a transport channel in the III-N semiconductor channel adjacent to at least both sidewall surfaces in response to a gate bias voltage. In embodiments, a gate stack is deposited completely around a nanowire including a III-N semiconductor channel compositionally graded to enable formation of a transport channel in the III-N semiconductor channel adjacent to both the polarization layer and the transition layer in response to a gate bias voltage.

Abstract: A method of selectively etching a semiconductor device and manufacturing a BSI image sensor device includes etching a doped silicon substrate with an HNA solution for a predetermined time duration to obtain an etching solution having a concentration C1 of nitrite ions, etching the semiconductor device using the obtained etching solution. Etching the semiconductor device requires an initial concentration C0 of nitride ions that is lower than C1. The HNA solution comprises a hydrofluoric acid (HF), a nitric acid (HNO3), and a acetic acid (CH3COOH). The BSI image sensor device will have a uniform thickness when etched using the thus obtained etching solution.

Abstract: This disclosure discloses a light-emitting display module display. The light-emitting display module comprises: a board; and a plurality of light-emitting diode modules arranged in an array configuration on the board; wherein one of the light-emitting diode modules comprises a plurality of encapsulated light-emitting units spaced apart from each other; and one of the encapsulated light-emitting units comprises a plurality of optoelectronic units, a first supporting, and a fence; and wherein the plurality of optoelectronic units are covered by the first supporting structure, and the fence surrounds the first supporting structure and the plurality of optoelectronic units.

Abstract: A method of fabricating a semiconductor device includes providing one or more semiconductor layers, providing a gate contact on a first surface of the one or more semiconductor layers, then using the gate contact as a mask to deposit a source contact and a drain contact on the first surface of the one or more semiconductor layers, such that the source contact and the drain contact include an interior edge that is laterally aligned with a different lateral edge of the gate contact.

Abstract: Apparatus and techniques for use in manufacturing a light emitting device, such as an organic light emitting diode (OLED) device can include using one or more modules having a controlled environment. The controlled environment can be maintained at a pressure at about atmospheric pressure or above atmospheric pressure. The modules can be arranged to provide various processing regions and to facilitate printing or otherwise depositing one or more patterned organic layers of an OLED device, such as an organic encapsulation layer (OEL) of an OLED device. In an example, uniform support for a substrate can be provided at least in part using a gas cushion, such as during one or more of a printing, holding, or curing operation comprising an OEL fabrication process. In another example, uniform support for the substrate can be provided using a distributed vacuum region, such as provided by a porous medium.

Abstract: The present disclosure relates to a field of display technology, and provides an AMOLED pixel circuit, a method for driving the same, and a display device, which can improve an integration of an in-cell touch control circuit with an AMOLED driving circuit. The AMOLED pixel circuit comprises a light-emitting module, a touch control module, a control module, and a driving and amplifying module. The MOLED pixel circuit provided in embodiments of the present disclosure can be used in the manufacture of the AMOLED display device.

Abstract: A method of manufacturing a semiconductor device includes etching a recess into a substrate and epitaxially growing a source/drain region in the recess. The source/drain region includes a first undoped layer of stressor material lining the recess, a lightly doped layer of stressor material over the first undoped layer, a second undoped layer of stressor material over the lightly doped layer, and a highly doped layer of stressor material over the second undoped layer.

Abstract: According to one embodiment, a semiconductor light emitting element includes: a support substrate; a bonding layer provided on the support substrate; an LED layer provided on the bonding layer; and a buffer layer softer than the bonding layer. The buffer layer is placed in one of between the support substrate and the bonding layer and between the bonding layer and the LED layer.

Abstract: Embodiments of a semi-insulating Group III nitride and methods of fabrication thereof are disclosed. In one embodiment, a semi-insulating Group III nitride layer includes a first doped portion that is doped with a first dopant and a second doped portion that is doped with a second dopant that is different than the first dopant. The first doped portion extends to a first thickness of the semi-insulating Group III nitride layer. The second doped portion extends from approximately the first thickness of the semi-insulating Group III nitride layer to a second thickness of the semi-insulating Group III nitride layer. In one embodiment, the first dopant is Iron (Fe), and the second dopant is Carbon (C). In another embodiment, the semi-insulating Group III nitride layer is a semi-insulating Gallium Nitride (GaN) layer, the first dopant is Fe, and the second dopant is C.

Abstract: A semiconductor device comprising at least one active layer on a substrate and a a Schottky contact to the at least one active layer, the Schottky contact comprising a body of at least titanium and nitrogen that is electrically coupled with the at least one active layer.

Abstract: Embodiments of the present disclosure include a method for forming a semiconductor device, a method for forming a MISFET device, and a MISFET device. An embodiment is a method for forming a semiconductor device, the method including forming a source/drain over a substrate, forming a first etch stop layer on the source/drain, and forming a gate dielectric layer on the first etch stop layer and along the substrate. The method further includes forming a gate electrode on the gate dielectric layer, forming a second etch stop layer on the gate electrode, and removing the gate dielectric layer from over the source/drain.

Abstract: The invention relates to an avalanche diode that can be employed as an ESD protection device. An avalanche ignition region is formed at the p-n junction of the diode and includes an enhanced defect concentration level to provide rapid onset of avalanche current. The avalanche ignition region is preferably formed wider than the diode depletion zone, and is preferably created by placement, preferably by ion implantation, of an atomic specie different from that of the principal device structure. The doping concentration of the placed atomic specie should be sufficiently high to ensure substantially immediate onset of avalanche current when the diode breakdown voltage is exceeded. The new atomic specie preferably comprises argon or nitrogen, but other atomic species can be employed. However, other means of increasing a defect concentration level in the diode depletion zone, such as an altered annealing program, are also contemplated.

Abstract: A memory device includes a memory array, a test circuit suitable for detecting a first repair address corresponding to a defective cell in the memory array, in a test mode, an external input circuit suitable for receiving a second repair address from an exterior, in response to an address input command, in an external input mode, and a nonvolatile memory circuit suitable for programming the first repair address in a first region in response to a first program command in the test mode, and programming the second repair address in a second region in response to a second program command in the external input mode, wherein the first repair address is programmed in the second region in response to the second program command while the address input command is deactivated in the external input mode.

Abstract: The present invention provides a silicon-compatible germanium-based high-hole-mobility transistor with high-hole-mobility germanium channel comprising a semiconductor material having a valence band offset instead of the conventional gate insulating film, a germanium channel region, and a quantum well formed by heterojunctions of the upper and lower portions of the germanium channel on a silicon substrate. Thus, the present invention enables to gain maximum hole mobility of the germanium channel by using the two-dimensional hole gas gathered into the quantum well for high-speed and low-power operations and device reliability improvement.

Abstract: A bias circuit sets a value of a bias current using a correction coefficient ?=0.5 for a predetermined time period from when a state in which a first capacitor and a second capacitor are not charged, then changes the correction coefficient to ?=0.9 which is larger than ?=0.5, and sets a value of the bias current obtained by using the correction coefficient ?=0.9. The constant current source supplies the light emitting element with the bias current obtained by using the correction coefficient ?=0.9 and supplies the bias current with a switching current, and thus an electrostatic latent image is formed.

Abstract: Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.

Abstract: Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds.

Abstract: Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

Abstract: The present invention relates to a circuit board. A circuit board in accordance with an embodiment of the present invention includes a base substrate; an interlayer insulating layer covering the base substrate; a via structure passing through at least the interlayer insulating layer of the base substrate and the interlayer insulating layer in the vertical direction; and an etch stop pattern disposed on the interlayer insulating layer in the horizontal direction to surround the via structure and made of an insulating material.

Abstract: Systems and methods for lead frame locking design features are provided. In one embodiment, a method comprises: fabricating a lead frame for a chip package, the lead frame having a paddle comprising a step-out bottom locking feature profile across at least a first segment of an edge of the paddle that provides an interface with a mold compound; etching the paddle to have at least a second segment of the edge having either an extended-step-out bottom locking feature profile or an overhanging top locking feature profile; and alternating first and second segments along the edge of the paddle.

Abstract: A device structure and system for connecting optical waveguides to optical transmit and receive components is described. The structure is made of two parts. The lower part contains active optoelectronic components, such as lasers and photodetectors, and optical lenses. The lower part can be assembled by steps of aligning and bonding planar components. The upper part contains optical waveguides and lenses for coupling light into and out of the waveguides. The top part is mechanically connected to the lower part to form a mechanically sound connection. The lens system provides some tolerance to mis-alignment between the top and bottom parts. The system has features that enable fiber optic components to operate and survive in harsh environments, particularly large temperature extremes.

Abstract: A transistor device may include a first source portion including a first InSb material set and a first first-type dopant set. The transistor device may include a first drain portion including a second InSb material set and a first second-type dopant set. The transistor device may include a first gate and a corresponding first channel portion disposed between the first source portion and the first drain portion and including a third InSb material set. The transistor device may include a second drain portion including a first GaSb material set and a second first-type dopant set. The transistor device may include a second source portion including a second GaSb material set and a second second-type dopant set. The transistor device may include a second gate and a corresponding second channel portion disposed between the second source portion and the second drain portion and including a third GaSb material set.

Abstract: The invention relates to an optical component (10), comprising a first spherical reflector (12) and a second spherical reflector (14), which is arranged in order to reflect a light beam several times between the first reflector (12) and the second reflector (14) and which spans an interior together with the first spherical reflector (12), wherein a coupling-in device is provided, which comprises a coupling-in reflector element (16) arranged within the interior, said coupling-in reflector element being arranged in order to reflect a light beam (24) to be coupled in onto the first spherical reflector (12).

Abstract: An array substrate for a gate-in-panel (GIP)-type organic light-emitting diode (OLED) display device is provided. A plurality of circuit blocks are formed on gate circuit units and separated into pixel lines in which respective gate lines are disposed, and a plurality of clock lines formed in each of signal input units. Each of the signal input units includes at least one group. Each of the groups includes the plurality of clock lines. Each of the circuit blocks includes one or two partial circuit blocks, which are sequentially disposed in a row in a lengthwise direction of the gate line in each of the pixel lines. Each of the partial circuit blocks is included in a signal input unit disposed most adjacent thereto, and connected to a clock line formed in one group disposed most adjacent thereto through a plurality of first connection lines.

Abstract: A field-effect transistor including at least one lower substrate having two electrodes deposited thereon, respectively a source electrode and a drain electrode, a dielectric layer made of a dielectric material, and a gate electrode deposited on the dielectric layer. It includes an intermediate layer, made of a material comprising molecules having a dipole moment complying with specific direction criteria, deposited between the gate electrode and the dielectric layer, said intermediate layer extending at least under the entire surface area taken up by the gate electrode, the intermediate layer being made of an organic compound comprising at least one binding function for the gate electrode.

Abstract: According to one embodiment, a semiconductor device, including a semiconductor layer including a first region and a second region isolated from the first region, a source in a surface of the first region, a drain in a surface of the second region, a back-gate in the surface of the source, a gate insulator on a surface of the first region, an end of a drain side of the back-gate being located closer to the drain side than an end of the drain side of the source, a gate insulator on a surface of the semiconductor layer between the first region and the second region, a gate electrode on the gate insulator, a source electrode being contacted to both the source and the back-gate, and a drain electrode being contacted to the drain area.

Abstract: A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer.

Abstract: A hetero-junction bipolar phototransistor includes a photo-absorption layer formed of a first conductivity type semiconductor layer, and a collector operating as a barrier layer, a base layer, and an emitter layer, which are stacked in sequence on the photo-absorption layer. The photo-absorption layer, collector, base layer and emitter layer forms a first mesa structure, and an emitter contact layer forms a second mesa structure. The photo-absorption layer includes a semiconductor layer with a narrow gap corresponding to a light-sensing wavelength of the phototransistor. The collector includes a semiconductor layer with a wider gap than a gap of the photo-absorption layer. The base layer has an energy level equal to or higher than the energy level of the collector. The emitter layer has a wide gap as compared to the base layer, and an energy level in a valence band is lower than an energy level of the base layer.

Abstract: A decoupling capacitor formed from a fin field-effect transistor (FinFET) and method of using the same are provided. An embodiment decoupling capacitor includes a fin field-effect transistor (FinFET) having a semiconductor substrate supporting a gate stack, a source, and a drain, a first terminal coupled to the semiconductor substrate and to the gate stack, the first terminal configured to couple with a first power rail, and a second terminal coupled to the source and to the drain, the second terminal configured to couple with a second power rail having a higher potential than the first power rail.