Abstract: A semiconductor device includes a grating structure having a plurality of parallel lines, and at least one of the multiple parallel lines is a gate electrode line of a transistor, which includes source/drain regions proximate to the gate electrode line, and vias extending to the gate electrode line and the source/drain regions. A method of manufacturing the semiconductor device is also disclosed.

Abstract: An SRAM comprises a memory cell including first and second access nMOS transistors, first and second driver nMOS transistors and first and second load pMOS transistors, polysilicon wires forming gates of the first and second access nMOS transistors and polysilicon wires extending in the same direction as the polysilicon wires for forming gates of the first and second driver nMOS transistors and gates of the first and second load pMOS transistors. The gate widths of the first and second access nMOS transistors and those of the first and second driver nMOS transistors are equalized with each other.

Abstract: In methods for fabricating MOS transistors with notched gate electrodes, a notched gate electrode may be readily fabricated using a damascene process for filling a stair-shaped opening formed in a multi-layered insulation layer. In this manner, the width and a height of the notch region of the gate electrode may be readily adjusted and controlled.

Abstract: A digital pixel sensor-based modular digital imaging system includes several integrated circuit modules. At least one module includes an integrated circuit die having a digital pixel sensor array and a frame buffer, and at least one module includes an integrated circuit die having control circuitry and/or I/O circuitry. In certain embodiments all component modules are generally the same; in other embodiments the component modules include different integrated circuits that perform different functions. A higher pixel count imaging system may be made by disposing several component modules having lower pixel count digital pixel sensor arrays adjacent one another.

Abstract: A notched gate SONOS transistor includes: a substrate having source/drain regions; a gate insulator layer on the substrate between the source/drain regions; a notched gate structure, on the gate insulator leyer, having at least one notch; and at least one ONO wedge structure in the at least one notch, respectively, of the gate structure.

Abstract: The present invention pertains to formation of a PMOS transistor wherein a layer of silicon or SiGe inhibits p-type dopant from entering into an underlying gate dielectric layer. The p-type dopant can be added to a gate electrode material that overlies the silicon or SiGe layer and can diffuse down toward the silicon or SiGe layer. The layer of silicon or SiGe may be formed to a thickness of about 5 to 120 nanometers and doped with a dopant, such as indium (In), for example, to deter the p-type dopant from passing through the silicon or SiGe layer. The dopant may have a peak concentration within the layer of silicon or SiGe near the interface of the silicon or SiGe layer with the underlying layer of gate dielectric material. Allowing the gate electrode to be doped with the p-type dopant (e.g., boron) facilitates forming the transistor with an associated work function having a desired value (e.g., coincident with a Fermi level of about 4.8 to about 5.6 electron volts).

Abstract: A semiconductor circuit array comprises a plurality of repetitive circuit blocks. Each of the circuit blocks comprises a plurality of functional circuit segments. Each of the functional circuit segments is physically oriented in on of a plurality of predetermined orientations independent of other functional circuit segment orientations in the circuit block.

Abstract: A gate array integrated circuit is provided, which includes first and second voltage supply rails and a row of P-channel type transistors and adjacent N-channel type transistors located between first and second voltage supply rails. Adjacent ones of the P-channel and N-channel transistors have common control terminals. A multiple-bit memory cell is fabricated in the row and includes first and second latches, a read output, a first pass gate coupled between the first latch and the read output, and a second pass gate coupled between the second latch and the read output. The first pass gate includes a first one of the P-channel or N-channel transistors. The second pass gate includes a second one of the same type of the P-channel or N-channel transistors. The first and second same type transistors share a common diffusion region.

Abstract: Some embodiments provide a semiconductor substrate having a cell array region and a peripheral circuit region. A plurality of word line patterns are placed in the cell array region, each of which include a word line and a word line capping layer pattern stacked thereon. At least one gate pattern including a gate electrode and a gate capping layer pattern is formed in the peripheral circuit region, the gate capping layer pattern and the word line capping layer pattern having different etching selectivity ratios. A pad interlayer insulating layer and a bit line interlayer insulating layer having approximately the same etching selectivity ratio as the gate capping layer pattern are sequentially formed over a surface of the semiconductor substrate having the gate spacers.

Abstract: The object is the present invention is to provide a semiconductor device including a circuit employing two or more field-effect transistor that are desired to have equal characteristics, capable of realizing high reliability and superior transistor characteristics. The transistors which are desired to have equal characteristics are placed in the semiconductor device so as to have the same STI trench width (the width of shallow trench isolation adjacent to an active in which the transistor is formed). By such composition, stress growing in the active due to the shallow trench isolation is equalized among the transistors and thereby the characteristics of the transistors can be equalized.

Abstract: A semiconductor intergrated circuit including p-type active regions and n-type active regions provided on a semiconductor substrate. Gate interconnect lines are arranged in a first predetermined direction on the p-type active regions and the n-type active regions. One of the p-type active regions and the n-type regions is provided with at least one protruding part for holding contact holes. A width along a second predetermined direction of the protruding part is larger than a width along the second direction of a space defined between two adjacent gate interconnect lines on the p-type active regions and the n-type active regions.

Abstract: An organic EL display device including a first TFT (30) for switching operation, a second TFT (40) for driving an organic EL element, and an organic EL element (60) having an anode (61), a cathode (66), and a light emissive element layer (65) sandwiched between these electrodes. The first TFT (30) has an n-channel and an LDD structure, exhibiting a high-speed response and superior retaining characteristics. The second TFT (40) has a p-channel, and therefore exhibits superior current controllability. By combining these two types of TFTs to drive the organic EL element for each pixel, a high ON current can be achieved with a reduced leakage current, thereby producing a quality gradation display.

Abstract: Well bias circuitry for selectively biasing the voltages of the well areas of an integrated circuit. In one embodiment, the well bias circuitry includes a switching cell located in a row of cells of the integrated circuit for selectively coupling a voltage supply line to a well bias line. The switching cell may include two level shifters, each for providing a voltage to a gate of a coupling transistor to make the coupling transistor non conductive in response to an enable signal. The switching cells may be sequentially coupled such that the coupling transistors of each of the switching cells are not made conductive at the same time so as to reduce inrush current due to changing the well bias from a well bias voltage to a supply voltage. In one example, the switching cells may include delay circuitry for delaying the change in state of the enable signal before being provided to the next switching cell.

Abstract: A method of forming a semiconductor circuit (20). The method forms a first transistor (NT1) using various steps, such as by forming a first source/drain region (361) as a first doped region in a fixed relationship to a semiconductor substrate (22) and forming a second source/drain region (362) as a second doped region in a fixed relationship to the semiconductor substrate. The second doped region and the first doped region are of a same conductivity type. Additionally, the first transistor is formed by forming a first gate (283) in a fixed relationship to the first source/drain region and the second drain region. The method also forms a second transistor (ST1) using various steps, such as by forming a third source/drain region (341) as a third doped region in a fixed relationship to the semiconductor substrate and forming a fourth source/drain region (342) as a fourth doped region in a fixed relationship to the semiconductor substrate.

Abstract: A memory array including a bit cell row, a strap cell row, a first power supply line, and a first offset supply line is provided. The bit cell row may include a bit cell that includes a first transistor disposed in a first bit cell body region. The first transistor may include a first active region. The strap cell row may include a strap cell that includes a first strap cell body region. The first strap cell body region may be conductively coupled to the first bit cell body region. The first power supply line may be electrically coupled to the first active region and may provide a first supply voltage potential to the first active region. The first offset supply line may be electrically coupled to the first strap cell body region and may provide a first offset voltage potential to the first bit cell body region via the first strap cell body region. The first supply voltage potential is operable to be different from the first offset voltage potential.

Abstract: An integrated circuit including a field effect transistor (FET) is provided in which the gate conducter has an even number of fingers disposed between alternating source and drain regions of a substrate. The fingers are disposed in a pattern over an area of the substrate having a length in a horizontal direction, the area equaling the length multiplied by a width in a vertical direction that is occupied by an odd number of the fingers.

Abstract: A fabricated multiple layer integrated circuit in which adequate planarization is accomplished using irregularly shaped and properly spaced conductive filler features that are spaced in such a way that capacitive coupling of the conductive filler features with the active conductive regions is reduced. The overall layout area of the conductive filler features is reduced to thereby reduce capacitive coupling with active conductive above and below. In addition, a relatively small edge of the feature is closest to the active conductive in the same conductive layer thereby further reducing capacitive coupling.

Abstract: Disclosed herein are a semiconductor device and a method of manufacturing the same that increases the reliability of these devices as size design limitations decrease. Generally, a first insulating film, and wiring, including conductive film patterns and second insulating film patterns are formed on a substrate. Third insulating film patterns including a silicon-oxide-based material are formed on sidewalls of the wiring, and contact patterns and spacers on the sidewalls thereof for defining contact hole regions are formed on the wiring. The contact holes contact surfaces of the third insulating film patterns and pass through the first insulating film. Thus, the thickness of a second insulating film pattern used in the wiring can be minimized, thereby increasing a gap-fill margin between the wiring. A parasitic capacitance between the wiring can be reduced because silicon oxide spacers with a low dielectric constant are formed on sidewalls of the wiring.

Abstract: A memory cell of a DRAM is reduced in size by making the width of a bit line finer than the minimum size determined by the limit of resolution of a photolithography. The bit line is made fine by forming a silicon oxide film on the inside wall of a wiring trench formed in a silicon oxide film and by forming the bit line inside the silicon oxide film. The silicon oxide film formed in the trench is deposited so that the silicon oxide film has a thickness thinner than half the width of the wiring trench and in the fine gap inside the silicon oxide film is buried a metal film to be the material of the bit line.

Abstract: A semiconductor integrated circuit is provided, which comprises a first cell comprising a plurality of transistors, a second cell comprising a PMOS transistor section and an NMOS transistor section, the PMOS transistor section comprising a first PMOS transistor and a second PMOS transistor connected to the first PMOS transistor in series, the NMOS transistor section comprising a first NMOS transistor and a second NMOS transistor connected to the first NMOS transistor in series. A predetermined scheme is used to connect between the first cell and the second cell, between the plurality of transistors in the first cell, and between the PMOS transistor section and the NMOS transistor section in the second cell.

Abstract: A very efficient gate array core cell in which the base core cell consists of a group of 6 PMOS transistors and a group of 6 NMOS transistors. It also includes pre-wiring of 2 of the 6 PMOS transistors, with 2 of the 6 NMOS transistors at polysilicon level or at local interconnect level while leaving the remaining PMOS and NMOS transistors as individual transistors to be interconnected during the functional ASIC metallization process. The core cell also has 2 polysilicon or local interconnect wires embedded in it, which can be used to interconnect transistors for logic function implementation. The core cell defined in this invention is highly flexible and has been analyzed to interconnect all types of logic and memory functions needed for ASIC designs. The layout of the transistors, pre-wiring of the strategic transistors at polysilicon level or at local interconnect level, and embedded polysilicon or local interconnect wires reduce the core cell size significantly.

Abstract: A semiconductor device includes on the same chip at least an I/O region where an input/output pad is formed and active regions where a circuit can be mounted, where a plurality of logic circuits having the same functions or different functions are mounted in the active regions on the same chip.

Abstract: High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.

Abstract: A semiconductor integrated circuit includes cells, cell rows and potential feeders. Each cell includes a partial trunk that is used to constitute a power supply trunk and/or a ground trunk, and that is electrically isolated from the remaining components within the cell. Each cell row includes a plurality of cells placed adjacently, and the power supply trunk and/or ground trunk composed of the partial trunks. The potential feeders selectively connect one of the power supply trunk and ground trunk of any one of the plurality of cell rows to the components within the cells to supply them with the potential of the power supply trunk and/or ground trunk. This enables the components in the adjacent cells to be supplied with different potentials.

Abstract: A MOS device with first and second freestanding semiconductor bodies formed on a substrate. The first freestanding semiconductor body has a first portion thereof disposed at a non-orthogonal, non parallel orientation with respect to a first portion of the second freestanding semiconductor body. These portions of said first and second freestanding semiconductor bodies have respective first and second crystalline orientations. A first gate electrode crosses over at least part of said first portion of said first freestanding semiconductor body at a non-orthogonal angle, as does a second gate electrode over the first portion of the second freestanding semiconductor body.

Abstract: The present invention provides a semiconductor memory device. In the semiconductor device, third and fourth transistors are configured as a vertical structure. The third transistor is laminated over a first transistor, and the fourth transistor is laminated over a second transistor, whereby a reduction in cell area is achieved. A voltage set on the condition that the difference between a source potential applied to each of the first and second transistors and the potential of a select level of a word line becomes greater than or equal to a threshold voltage of each of the third and fourth transistors, is supplied to a source electrode of each of the first and second transistors to thereby perform “0” write compensation.

Abstract: The invention relates to a process for making a gate for a CMOS transistor structure, made from a stack realized on a face in a semi-conducting material of a substrate, said stack comprising a gate isolation layer, a gate material layer and a gate mask in sequence, the process comprising the following steps:

Abstract: In the driver for driving display having an anode driver, a cathode driver, and memory portions of a semiconductor device of the invention, anode driver regions connected to the memory portions are laid out equally in the chip, and SRAMs and are arranged equally in the vicinity of each of anode driver regions so that drawing of wiring becomes easy and size of the chip is miniaturized.

Abstract: Memory integrated circuitry includes an array of memory cells formed over a semiconductive substrate and occupying area thereover, at least some memory cells of the array being formed in lines of active area formed within the semiconductive substrate which are continuous between adjacent memory cells. Adjacent memory cells are isolated from one another relative to the continuous active area formed therebetween by a conductive line formed over said continuous active area between said adjacent memory cells. At least some adjacent lines of continuous active area within the array are isolated from one another by LOCOS field oxide formed therebetween. The respective area consumed by individual memory cells is less than 8F2, where “F” is no greater than 0.25 micron.

Abstract: A semiconductor integrated circuit which is capable of being manufactured with a higher packing density and a small-size structure of standard cells is described. In the semiconductor integrated circuit, substrate regions and source regions are shared by adjacent standard cells as well as common contact regions which are located inward displaced respectively from the centers of the substrate regions.

Abstract: A semiconductor circuit array comprises a plurality of repetitive circuit blocks. Each of the circuit blocks comprises a plurality of functional circuit segments. Each of the functional circuit segments is physically oriented in on of a plurality of predetermined orientations independent of other functional circuit segment orientations in the circuit block.

Abstract: There is provided a semiconductor integrated circuit device wherein functional circuit groups are arranged on a chip in a direction spreads, which aims to enhance layout efficiency and to prevent deterioration of element characteristics. A unit wiring region IL1P is constituted outside of a power voltage wiring VCC, a part of a second region BIP and a unit wiring region IL1N is constituted outside of a reference voltage wiring VSS, a part of a second region BIN. Within the second wiring regions BIP and BIN, connection wirings 11, 12A, 13, 14 are wired. These connection wirings connect between units within the logic circuits CIA11, CIR12 or between the logic circuits CIR11, CIR12. There is only arranged an input/output wiring region IOL1 on a first region A1 located between the power voltage wiring VCC1 and the reference voltage wiring VSS1. Since no unit wiring region exists in the first region A1, width of the first region A1 can be laid-out short.

Abstract: An SRAM capable of reducing the overall area consumed by the circuit and capable of improving the mobility and operational characteristics of a PMOS transistor is provided. The SRAM is formed on an SOI substrate having first and second active areas. A first access NMOS transistor and a first inverter, which is constituted by a first drive NMOS transistor and a first load PMOS transistor, are formed on the first active area of the SOI substrate. A second access NMOS transistor and a second inverter, which is constituted by a first drive NMOS transistor and a first load PMOS transistor, are formed on the second active area of the SOI substrate. Here, the channels of the first and second load PMOS transistors extend so that carriers move in a [110] silicon crystallization growth direction. In each active area, the drain (or source) of an access NMOS transistor, the drain of a drive NMOS transistor, and the drain of a load PMOS transistor contact one another in a shared region.

Abstract: An SRAM includes: first and second access PMOS transistors formed on an N well region; first and second driver NMOS transistors formed on a P well region; a word line; and first and second bit lines. Active regions are extended in the same direction, polysilicon wirings for forming gates of each of the MOS transistors are extended in the same direction, and drains of the first and second access PMOS transistors are connected to drains of the first and second driver NMOS transistors using first metal wirings without interposing the polysilicon wirings forming the gates of the first and second driver NMOS transistors therebetween, respectively.

Abstract: A vertical JFET architecture. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is disposed over the first region. A third doped region is formed over the second doped region having an opposite conductivity type with respect to the second doped region, and forming a source/drain region. A gate is formed over the channel to form a vertical JFET.

Abstract: A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on an active region of the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; gate electrode side wall insulating layers provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to the gate electrode side wall insulating layers so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other.

Abstract: Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micropatterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

Abstract: A dual structure is introduced to the transistor in a flip-flop or a data input step controlled by a clock of a semiconductor logic circuit. The dual structure is formed by connecting a transistor with a MOS transistor having a channel of the same conductivity type in series with respect to the line of a source or drain and connecting their gates to each other, or by connecting an inverter with p-MOS transistors, one for VDD side and one for VSS side of the output step. The dual structure prevents single event phenomenon in a semiconductor logic circuit, such as inverter, SRAM and data latch circuit.

Abstract: A folded bit line DRAM device is provided. The folded bit line DRAM device includes an array of memory cells. Each memory cell in the array of memory cells includes a pillar extending outwardly from a semiconductor substrate. Each pillar includes a single crystalline first contact layer and a single crystalline second contact layer separated by an oxide layer. A single crystalline vertical transistor is formed along alternating sides of the pillar within a row of pillars. The single crystalline vertical transistor includes an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer, an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer, and an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions.

Abstract: A compact SRAM cell that incorporates refractory metal-silicon-nitrogen resistive elements as its pull-up transistors is described which includes a semi-conducting substrate, a pair of NMOS transfer devices formed vertically on the sidewalls of an etched substrate by a metal conductor providing electrical communication between an n+ region in the substrate and a bitline on top, a pair of pull-down nMOS devices on the substrate connected to ground interconnects, and a pair of vertical high-resistive elements formed of a refractory metal-silicon-nitrogen and function as a load for connecting to Vdd. The invention further describes a method for fabricating such compact SRAM cell.

Abstract: A semiconductor memory cell having a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read by sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 Å thickness or less, as commonly available from presently available advanced CMOS logic processes.

Abstract: Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal.

Abstract: A first repair chip, wherein BANK 2 functions properly although BANKs 0, 1 and 3 have become defective, and a second repair chip, wherein BANKs 1, 2 and 3 function properly although BANK 0 has become defective, are mounted on a rear surface of a module substrate in order to substitute for the functions of BANK 2 of the first bare chip and of BANKs 1 and 2 of the second bare chip that have become defective on the front surface of the module substrate. Thereby, a semiconductor memory module is obtained that can be repaired by mounting chips that carry out functions substituting for those of defective banks while effectively utilizing the functions of other banks that are not defective.

Abstract: A semiconductor memory device includes a plurality of bit line structures arranged in parallel on a semiconductor substrate and having a plurality of bit lines and an insulating material surrounding the bit lines, an isolation layer formed in a portion in spaces between the bit line structures to define a predetermined active region and having substantially the same height as the bit line structures, a semiconductor layer formed in the predetermined active region surrounded by the bit line structures and the isolation layer and having substantially the same height as the bit line structures and the isolation layer, a plurality of word line structures arranged in parallel on the bit line structures, the isolation layer, and the semiconductor layer, and comprising a plurality of word lines and an insulating material surrounding the word lines, and source and drain regions formed in the semiconductor layer on either side of the word line structures.

Abstract: A semiconductor memory device provided with a plurality of memory cells each including first transistors having first conductivity type and second transistors having a second conductivity type, each memory cell comprising a first active region where channels of the first transistors are formed and a second active region where channels of the second transistors are formed, the first and second active regions being arranged so that the directions of channel currents of the transistors become parallel to each other in each cell and being separated between adjoining memory cells in a direction perpendicular to the directions of channel current.

Abstract: A new structure is disclosed for source/drain bit lines in arrays of MOSFET devices. Rows of conducting regions are formed by ion implantation through openings adjacent to gate structures and in isolation regions separating columns of active areas of the arrays. The openings are filled with insulating material.

Abstract: There is provided a driving circuit including active matrix type liquid crystal display capable of decreasing the electric power consumption of CMOS buffers contained in a scanning line driving circuit and picture signal line driving circuit. The liquid crystal display has an active matrix type liquid crystal display elements comprising switching elements connected to a plurality of scanning lines and a plurality of picture signal lines perpendicular to the scanning lines. The liquid crystal display includes a digital circuit wherein at least one of a scanning line driving circuit for applying a scanning pulse to the switching elements via the scanning lines and a picture signal line driving circuit for applying a picture signal to the picture signal lines comprises one stage of CMOS buffer or a plurality of CMOS buffers connected in multi stages, the CMOS transistor or each of the CMOS transistors including an N-type thin-film transistor and P-type thin-film transistor which are formed on the same substrate.

Abstract: The present invention realizes a display device having C-MOS p-Si TFTs which enable the high integration by reducing spaces for P-MOS TFTs and N-MOS TFTs in driving circuit or the like thereof. The present invention adopts a self-aligned C-MOS process which uses a half tone mask as an exposure mask for manufacturing the C-MOS p-Si TFTs mounted on the display device. With the use of the half tone mask, the alignment or positioning at a bonding portion between a P-MOS portion and an N-MOS portion becomes unnecessary and hence, the number of photolithography steps can be reduced and the high integration of C-MOS TFT circuits can be realized.

Abstract: A semiconductor device and method of fabrication are disclosed. The device includes a first trench isolation region having an allowable tiling area and a second trench isolation region having an allowable tiling area, wherein the second trench isolation region is doped differently from the first trench isolation region. First tile structures disposed within first trench isolation region have a first set of design parameters while second tile structures disposed within the second trench isolation region have a second set of design parameters. At least one of the first set of design parameters is different from a corresponding design parameter in the second set of design parameters. The corresponding design parameters may include the density, size, pitch, shape, exclusion distance, minimum width, minimum length, and minimum area. The first trench isolation region may be doped with a first-type dopant and the second trench isolation region may be undoped or doped with an opposite second-type dopant.

Abstract: An on-chip decoupling capacitor cell is disclosed that is compatible with standard CMOS cells. A cell boundary defining the area of the cell includes a first transistor area and a second transistor area. A PMOS transistor having an n-well is formed within the first transistor area. The on-chip decoupling capacitor cell further includes an n-well extension that extends the n-well into the second transistor area, thereby providing a decoupling capacitor cell having reduced leakage compared to a CMOS capacitor cell, and increased capacitance per unit area compare with a traditional PMOS capacitor cell.