Abstract: A method for improving a doping profile using gas phase doping is described. In the method, silicon nitride and/or products of decomposition from a silicon nitride deposition are introduced in a process chamber before or during the actual gas phase doping. This allows the doping profile to be significantly improved.

Abstract: A method of fabricating shallow trench isolation. In the method, a refill step of oxide layer and a step of forming a sacrificial layer on the semiconductor substrate are applied after filling insulating layer into the shallow trenches. The purpose of the steps is to protect the oxide layer on the semiconductor substrate and the corner of the shallow trenches, used to isolate the STI.

Abstract: The invention relates to a CCD of the buried-channel type comprising a charge-transport channel in the form of a zone (12) of the first conductivity type, for example the n-type, in a well (13) of the opposite conductivity type, in the example the p-type. In order to obtain a drift field in the channel below one or more gates (9, 10a) to improve the charge transfer, the well is provided with a doping profile, so that the average concentration decreases in the direction of charge transport. Such a profile can be formed by covering the area of the well during the well implantation with a mask, thereby causing fewer ions to be implanted below the gates (9, 10a) than below other parts of the channel. By virtue of the invention, it is possible to produce a gate (10a) combining a comparatively large length, for example in the output stage in front of the output gate (9) to obtain sufficient storage capacity, with a high transport rate.

Abstract: P-type ion implantation is done in N well 15, so as to form a charge drain control layer 17 and form a photodiode N well 16 and OFD drain 5, the result being that, even if there is variation in the potential of the photodiode N well 16 making up the photodiode, because the variation in the potential of the charge drain control layer 17 is in the same direction as the potential of the photodiode N well 16, so that variation does not occur in the maximum amount of electrical charge that can be accumulated, the result being that there is no variation in the signal in the saturation condition.

Abstract: The specification describes silicon MOS devices with gate dielectrics having the composition Ta1−xAlxOy, where x is 0.03-0.7 and y is 1.5-3, Ta1−xSixOy, where x is 0.05-0.15, and y is 1.5-3, and Ta1−x−zAlxSizOy, where 0.7>x+z>0.05, z<0.15 and y is 1.5-3. By comparison with the standard SiO2 gate dielectric material, these materials provide improved dielectric properties and also remain essentially amorphous to high temperatures. This retards formation of SiO2 interfacial layers which otherwise dominate the gate dielectric properties and reduce the overall effectiveness of using a high dielectric material.

Abstract: In a complete depletion type SOI transistor, the roll-off of a threshold value is suppressed, independently from the formation of an SOI film to be thinner. As for a semiconductor device (1), the impurity concentration in a channel formation portion (10) is implanted not uniformly along the length direction of a gate (2) in the complete depletion type silicon on insulation (SOI) transistor. In other words, high concentration regions (11) where impurity concentrations are higher than that at a central portion in the end parts of the channel formation portion (10) on the side of a source (4) and a drain (5).

Abstract: A method for reducing dark current within a charge coupled device includes the steps of providing three or more phases of gates separated by an insulating layer from a buried channel of the first conductivity type in a well or substrate of the second conductivity type, and a clock driver for causing the transfer of charge through the charge coupled device; providing a barrier for separating charge packets when in accumulation state; applying, at a first time period, voltages to all phases of gates sufficient to cause the surface of the first conductivity type to be accumulated by dark current reducing charge carriers; after the first time period, applying, at each gate phase n having a capacitance Cn to the layer of the second conductivity type, a voltage change on the gate phase n given by &Dgr;Vn such that the sum of products of the capacitances and voltage changes is substantially zero ∑ n ⁢   ⁢

Abstract: There is provided a semiconductor device having a new structure which allows a high reliability and a high field effect mobility to be realized in the same time. In an insulated gate transistor having an SOI structure utilizing a mono-crystal semiconductor thin film on an insulating layer, pinning regions are formed at edge portions of a channel forming region. The pinning regions suppress a depletion layer from spreading from the drain side and prevent a short-channel effect. In the same time, they also function as a path for drawing out minority carriers generated by impact ionization to the outside and prevent a substrate floating effect from occurring.

Abstract: A solid-state CCD device suitable for forming into arrays and for use with suitable hardware to form video image capture devices and methods for fabricating same are provided.

Abstract: A solid state imaging pickup device with a single-layer electrode structure which eliminates the release area at the terminal part of the charge transfer electrodes by surrounding the charge transfer electrodes with a dummy pattern, or with a pattern formed by connecting the charge transfer electrodes of a certain phase with each other at the outermost periphery. Surrounding the charge transfer electrode improves embedding performance when an insulating film is re-flowed for flattening inter-electrode gaps. This enables formation of a good metal wire or shielding film with no step-cut, thus improving the reliability of a solid state imaging pickup device.

Abstract: An oxynitride material is used to form shallow trench isolation regions in an integrated circuit structure. The oxynitride may be used for both the trench liner and trench fill material. The oxynitride liner is formed by nitriding an initially formed oxide trench liner. The oxynitride trench fill material is formed by directly depositing a high density plasma (HDP) oxide mixture of SiH4 and O2 and adding a controlled amount of NH3 to the plasma mixture. The resultant oxynitride structure is much more resistant to trench fill erosion by wet etch, for example, yet results in minimal stress to the surrounding silicon. To further reduce stress, the nitrogen concentration may be varied by varying the proportion of O2 to NH3 in the plasma mixture so that the nitrogen concentration is maximum at the top of the fill material.

Abstract: An asymmetrical channel implant from source to drain improves short channel characteristics. The implant provides a relatively high VT net dopant adjacent to the source region and a relatively low VT net dopant in the remainder of the channel region. One way to achieve this arrangement with disposable gate processing is to add disposable sidewalls inside the gate opening (after removing the disposable gate), patterning to selectively remove the source or gate side sidewalls, implant the source and drain regions and remove the remaining sidewall and the proceed. According to a second embodiment, wherein the channel implant can be symmetrical, a relatively low net VT implant is provided in the central region of the channel and a relatively high net VT implant is provided in the channel regions adjacent to the source and drain regions.

Abstract: A charge transfer device which comprises vertical charge transfer devices which transfer charges in the vertical direction, first and second horizontal charge transfer devices which transfer the charges from the vertical charge transfer devices in the horizontal direction, and a shift gate which controls the charges from the vertical charge transfer devices to be supplied to one the first horizontal charge device or the second horizontal charge transfer device, wherein the first. horizontal charge transfer device is a semiconductor region between the vertical charge transfer devices and the second horizontal charge transfer device and includes highly-doped regions having tapered portions whose one ends near the second horizontal charge transfer device are broader than another ends near the vertical charge transfer devices.

Abstract: A charge transfer device is provided, capable of preventing degradation of the charge transfer efficiency when the channel width becomes narrower due to the narrow channel effect. The charge transfer device of the present invention is obtained by forming a charge transfer electric field in a channel below a boundary portion between a terminal storage electrode and a terminal barrier electrode, which constitute a pair of charge transfer electrodes located closest to the output electrode, to be higher than a charge transfer electric field in a channel below a boundary portions of pairs of storage electrodes and barrier electrodes, which constitute pairs of storage electrodes and barrier electrodes other than the pair of the terminal electrodes.

Abstract: There is provided a semiconductor device having a new structure which allows a high reliability and a high field effect mobility to be realized in the same time. In an insulated gate transistor having an SOI structure utilizing a mono-crystal semiconductor thin film on an insulating layer, pinning regions are formed at edge portions of a channel forming region. The pinning regions suppress a depletion layer from spreading from the drain side and prevent a short-channel effect. In the same time, they also function as a path for drawing out minority carriers generated by impact ionization to the outside and prevent a substrate floating effect from occurring.

Abstract: There is provided a semiconductor integrated circuit device with high electrostatic resistance. A semiconductor device is provided with a transistor for input-output protection having a desired size in which its channel length is varied with respect to a channel width direction.

Abstract: In a solid-state image pickup device, a transfer register 10 is provided with an overflow control gate OFCG and an overflow drain OFD, and the gate electrode 12A of the overflow control gate OFCG is formed so as to be superposed on the lower-layer electrodes St1, 13 of the transfer register 10 side the overflow drain OFD side.

Abstract: This invention provides a manufacturing process for a charge transfer device comprising an N-type well formed in a P-type well on a semiconductor substrate for transferring a signal charge, an N+region formed on both sides along the charge transfer direction of the N-type well and containing a dopant in a higher concentration than that in the N-type well, a P-type region formed around the N+ region, and a gate electrode covering the N+ region and the N-type well and formed via a gate insulator, comprising ion-implanting an N-type dopant into the region to be the N-type well and the N+ region using the first mask and ion-implanting a P-type dopant into the region to be the N-type well using the second mask. Thus, there can be provided a charge transfer device which has a structure where there is an N+ region on both sides of the N-type well, a large maximum transferable charge and a compact CCD with a width up to 3 times the minimum design dimension.

Abstract: A charge coupled device has an n- type charge accumulating layer equal to or less than 5 micron in width, and the unit cells suffer from reduction of signal charge accumulated therein and an increased pulse height of a pulse signal for a substrate shutter, wherein at least one p- type local impurity region is formed in such a manner as to form a p-n junction together with the n- type charge accumulating layer and the n- type semiconductor substrate, thereby increasing the amount of signal charge accumulated in each unit cell without sacrifice of the pulse height of the pulse signal for the substrate shutter.

Abstract: There is provided a semiconductor device having a new structure which allows a high reliability and a high field effect mobility to be realized in the same time. In an insulated gate transistor having an SOI structure utilizing a mono-crystal semiconductor thin film on an insulating layer, pinning regions are formed at edge portions of a channel forming region. The pinning regions suppress a depletion layer from spreading from the drain side and prevent a short-channel effect. In the same time, they also function as a path for drawing out minority carriers generated by impact ionization to the outside and prevent a substrate floating effect from occurring.

Abstract: A field effect transistor (FET) structure, and method for making the same, which further suppresses short-channel effects based on variations within the gate dielectric itself. The FET structure utilizes non-uniform gate dielectrics to alter the vertical electric field presented along the channel. The thickness and/or dielectric constant of the gate dielectric is varied along the length of the channel to present a vertical electric field which varies in a manner that tends to reduce the short-channel effects and gate capacitances.

Abstract: A two-phase, single-ply-electrode type charge-coupled device is provided that has a pair of a potential barrier region and a charge storage region underlying one charge transfer electrode. The charge storage region is formed in such a manner that the potential of the charge storage region becomes gradually deep in charge transfer direction. This structure enables smooth charge transfer.

Abstract: A shallow trench isolation process is described. A pad oxide layer is formed over a substrate. A silicon nitride layer is formed over the pad oxide layer. The silicon nitride layer is patterned. The pad oxide layer and the substrate are etched using the patterned silicon nitride as an etching mask, and thus a trench is formed in the substrate. A liner oxide layer is grown over the trench. An oxide layer is deposited to fill the trench in the substrate and has a surface level higher than the silicon nitride layer. The oxide layer is polished to partially remove the oxide layer over the silicon nitride layer. The silicon nitride layer is removed from the substrate, by which removal the oxide layer has an exposed sidewall. A polysilicon spacer is formed on the exposed sidewall. The pad oxide layer is removed. The polysilicon spacer is oxidized and transformed into an oxide spacer.

Abstract: There is provided a semiconductor device having a new structure which allows a high reliability and a high field effect mobility to be realized in the same time. In an insulated gate transistor having an SOI structure utilizing a mono-crystal semiconductor thin film on an insulating layer, pinning regions are formed at edge portions of a channel forming region. The pinning regions suppress a depletion layer from spreading from the drain side and prevent a short-channel effect. In the same time, they also function as a path for drawing out minority carriers generated by impact ionization to the outside and prevent a substrate floating effect from occurring.

Abstract: A fabrication method for a MOSFET device including the steps of forming a first insulating film on a semiconductor substrate wherein an active region and an isolated region are defined, forming a channel ion region by implanting impurity ions into the active region of the semiconductor substrate, forming a first conductive film pattern on a portion of the semiconductor substrate which corresponds to the channel ion region, forming a channel region having lower concentration than the channel ion region by implanting impurity ions in a different type from the ions in the channel ion region into a center portion of the channel ion region through the first conductive film pattern, forming a second conductive film pattern on the first conductive film pattern, forming an impurity region of low concentration in the semiconductor substrate with the first and second conductive film patterns as a mask, forming a sidewall spacer at both sides of the first and second conductive film patterns, and forming an impurity regi

Abstract: A dipping in potential well due to direct contact between transfer electrodes and metal wiring causes a drop in transfer efficiency through a CCD register. In order to eliminate or at least reduce the potential dipping, an N.sup.- -type impurity layer that functions as a CCD channel is formed with N.sup.-- -type impurity regions that have impurity concentration lower than that of the N.sup.- -type impurity layer. The N.sup.- -type impurity regions are located below transfer electrodes in alignment with contact apertures.

Abstract: A solid state image pick-up device is disclosed in which potential wells formed between adjacent ones of charge transfer electrodes of a vertical charge transfer portion thereof, formed between adjacent ones of charge transfer electrodes of a horizontal charge transfer portion and formed in a connecting region between the vertical and horizontal charge transfer portions are uniformalized. Impurity densities of regions between the charge transfer electrodes of the vertical charge transfer portion thereof, between the charge transfer electrodes of the horizontal charge transfer portion and in a connecting region between the vertical and horizontal charge transfer portions are set independently from each other on the basis of the inter-electrode distances and amplitudes and potentials of driving pulses supplied these electrodes such that these potential wells become equal to each other.

Abstract: In a charge transfer device of the two-layer electrode, two-phase drive type, an N.sup.-- semiconductor region 108 and a first insulator film 103 are formed on a P-type semiconductor substrate 101 in the named order. Then, first transfer electrodes 104A are formed on the first insulator film 103, and a second insulator film 105 is formed on the surface of the N.sup.-- semiconductor region 108 and a third insulator film 105 is formed on a top surface and a side surface of each first transfer electrode 104A. Phosphorus is ion-implanted with an incident angle of 0 degree, so that an N-type semiconductor region 102A is formed in N.sup.-- semiconductor region 108 between the first transfer electrodes 104A in self-alignment. Second transfer electrodes 109A are formed, and an interlayer insulator 110 is formed on the whole, and metal interconnections 111-1A and 111-2A are formed.

Abstract: A gate insulating film and gate electrodes are formed on a substrate containing N-type impurities such as P or As. Under the gate insulating film is a gate region on both sides of which are a first and a second source drain region. The gate region is furnished in its central part with a high-concentration channel injection region containing N-type impurities at a concentration higher than that of the substrate. Between the high-concentration channel injection region on the one hand and the first and the second source drain region and on the other hand, there are formed a first and a second low-concentration channel injection region and having substantially the same impurity concentration as that of the substrate.

Abstract: A charge coupled device of buried channel type suitable to drive the device by clock pluses having a low voltage is disclosed. Channels of the charge coupled device comprises first to third regions. The first region has a first impurity concentration. The second region has a second impurity concentration lower than the first impurity concentration. The third region has a third impurity concentration lower than the second impurity concentration. A first transfer electrode is formed on the first region. A second transfer electrode is formed on the second region.

Abstract: The disclosure relates to charge-coupled devices taking the form of shift registers and, more specifically, to those working in the MPP (Multi-Pinned Phase) mode, i.e. with high negative polarisation of the electrodes during the phases of waiting or of integration of integration of the photosensitive charges. These registers use a potential barrier created by a P type compensating implantation in a zone 16 located beneath a first electrode of each stage of the register. This barrier separates the stages from one another. To increase the charge storage capacity during the storage phase and the charge transfer capacity during the transfer, it is provided that the compensating implantation of the zone 16 will extend beneath only one part (and not the totality) of the first electrode of each stage of the register. Application to photosensitive image sensors, analog delay lines, charge-coupled analog memories, working in MPP mode during the waiting phases to limit losses of information due to the dark current.

Abstract: The MOSFET has a stacked gate structure which has a first silicon layer, a second silicon layer, and a spacer structure. The first silicon layer is formed over the semiconductor substrate. The second silicon layer contains second type dopants and is formed on the first silicon layer. The spacer structure containing first type dopants is formed on the sidewall of the first silicon layer and the second silicon layer. A gate insulator layer is formed between the first silicon layer and the semiconductor substrate. The second silicon layer is also formed on the semiconductor substrate at a region uncovered by the stacked gate structure. A junction region is formed in the semiconductor substrate under the second silicon layer but not under the stacked gate structure. An extended junction is formed in the semiconductor substrate under the spacer structure.

Abstract: In a method of manufacturing a charge coupled device, a channel layer is formed on a surface of a semiconductor substrate. Then, first layer transfer electrodes are formed in a charge transfer direction above the channel layer via a first insulating film. Subsequently, second layer transfer electrodes are formed such that each of the second layer transfer electrodes is disposed between two of the first layer transfer electrodes without any portion overlapping the first layer transfer electrodes in a plane structure. The second layer transfer electrodes may be patterned after a polysilicon film is deposited and polished or may be polished after the polysilicon film is deposited and patterned.

Abstract: A charge coupled device has a plurality of N-diffused regions and a plurality of N.sup.- diffused regions arranged alternately along a charge transfer channel. A first electrode and second electrode overlying each N-diffused region and N.sup.- -diffused region form a pair of electrodes, four of which form a group of electrodes iteratively appearing along the charge transfer channel. Each first pair and each third pair are connected to a first signal line and second signal line, respectively, which receive two-phase driving clock signals, while each second pair and fourth pair are connected to a fixed potential line maintained at a middle potential between the high level and low level of the driving signals. A high-speed transfer of signal charges is obtained in the two-phase type charge coupled device.

Abstract: This invention provides a semiconductor device with a SOI structure and a method of manufacturing the same, preventing deterioration in and making improvement in device characteristics. Nitrogen ion implantation into NMOS and PMOS regions (NR, PR) with resists (22b) and (22c) as masks, respectively, introduces nitrogen ions into channel doped layers (31). The subsequent thermal treatment provides a structure with the channel doped layers (31) containing nitrogen having a prescribed concentration distribution in the depth direction.

Abstract: A linear CCD (charge-coupled device) including: a photodiode-array having a plurality of photodiodes for converting incident light plural charges, respectively; and a charge transfer part for transferring the charges of the photodiodes during a first phase of a first and second clock signal and for moving the charges during a second phase of the first and second clock signals. The charge transfer part includes: plural first shift electrodes connected to the photodiodes, respectively, for forming potential wells that receive charges from the photodiodes, respectively, during the first phase of the first and second clock signals; and plural second shift electrodes located between the first shift electrodes, respectively, for forming potential wells that receive the charges from the potential wells of the first shift electrodes during the second phase of the first and second clock signals. No shift gates are needed between charge outlets of the photodiodes and the first shift electrodes.

Abstract: The semiconductor device of the present invention is equipped with a plurality of photodiodes, a horizontal transfer part and a vertical transfer part, and in particular, the horizontal transfer part or the vertical transfer part has a configuration described as in the following. Namely, the device has a semiconductor region which is formed by regularly and consecutively arranging a plurality of blocks of the same conductivity type, where each of the plurality of the blocks is equipped with three regions of mutually different impurity concentrations, clock pulses are applied to two regions out of the three regions and the voltage of the high level or low level of the clock pulse is applied to the remaining region out of the three regions as a constant potential.

Abstract: The present invention provides an interline solid state image sensor comprising the following elements. A plurality of vertical charge coupled device resistors are provided, each of which extends in a vertical direction. The vertical charge coupled device resistors are parallel to each other. A plurality of photo-diodes are aligned along one side of each of the vertical charge coupled device resistors so that the photo-diodes are aligned between adjacent two vertical charge coupled device resistors. Each of the photo-diodes is connected via a charge read-out gate region to the vertical charge coupled device resistor. Each of the vertical charge coupled device resistor comprises laminations of a first conductivity type diffusion layer and a second conductivity type diffusion layer extending under the first conductivity type diffusion layer. A lateral charge coupled resistor extends in a lateral direction. The lateral charge coupled resistor is coupled with ends of the vertical charge coupled device resistors.

Abstract: In a charge coupled device including a semiconductor substrate having a semiconductor region, a plurality of nonactive barrier electrodes, a plurality of first electrodes and a plurality of second electrodes arranged between the nonactive barrier electrodes, an outermost one of the nonactive barrier electrodes is electrically isolated from the others of the nonactive barrier electrodes.

Abstract: A charge transfer device including a semiconductor substrate, a gate electrode provided in association with the substrate, the gate electrode having a corresponding channel region through which charge is propagated, the channel region having a predetermined potential; and means associated with the channel region for reducing charge trapping and recombination effects. In one aspect of the present invention, the reducing means includes a potential pocket defined within the channel region having a greater potential than the predetermined potential of said channel region. The potential pocket has a width dimension which is less than the corresponding width dimension of the channel region. The potential pocket is positioned in the center of the gate electrode, and is positioned so as to be aligned with a front edge of the gate electrode.

Abstract: In a charge coupled device having a plurality of output structures, the plurality of output structures including first and second output structures, a channel structure is defined in a channel region beneath a gate electrode and coupled to each of the plurality of output structures. The channel structure includes a plurality of area structures, each area structure being characterized by a uniform potential which is different from the potential characterizing each of the other area structures. The plurality of area structures are arranged within the channel region to define a first increasing stepped potential gradient from any point within the channel region to the first output structure and define a second increasing stepped potential gradient from any point within the channel region to the second output structure.

Abstract: The solid-state image sensor disclosed has a photodiode including a P-type layer provided on a surface of a semi-conductor substrate, an N-type layer provided in the N-type layer, and a P.sup.+ -type region which is disposed on a surface of the N-type layer. A P.sup.++ -type region is disposed in a region surrounding the photodiode excepting in a read region for reading out charges in the photodiode, and this P.sup.++ -type region has a higher impurity concentration and a greater depth than the P.sup.+ -type region. That is, the P.sup.++ -type region which isolates photodiode regions and vertical CCD regions from one another is formed as a high impurity concentration diffusion layer or an electron trap region containing a large amount of electron trap centers. Thus, it is possible to reduce smear generation in unit pixels and to produce sharp images.

Abstract: A charge transfer device formed on a semiconductor substrate comprising: a charge transfer section formed on the semiconductor substrate for transferring charges, a floating gate having a floating gate diffusion layer formed on the semiconductor substrate for accumulating the charges transferred from the charge transfer section, an output gate section formed between the charge transfer section and the floating gate on the semiconductor substrate, and a charge detecting circuit electrically connected to the floating gate for outputting a voltage corresponding to the amount of the charges accumulated in the floating gate diffusion layer, the output gate section having a first output gate region adjacent to the charge transfer means and a second output gate region adjacent to the floating gate diffusion layer, the first output gate region having a first output gate electrode formed thereon with an insulating film therebetween, the second output gate region having a second output gate electrode formed thereon wit

Abstract: An infrared solid-state image sensing apparatus is provided with a plurality of photoelectric converting sections arranged vertically and horizontally in a matrix pattern on a semiconductor substrate of a first conducting type; a plurality of vertical CCDs which have first buried channels of a second conducting type and electrodes disposed thereon with an insulating film between and which are disposed adjacently to the photoelectric converting sections; and a horizontal CCD having a second buried channel of the second conducting type and electrodes disposed thereon with an insulating film between and which is disposed adjacently to one side of the vertical CCDs. The first and second buried channels are provided with a low-concentration region having a uniform diffusion depth. Further, the surface of each first buried channel is provided with a high-concentration region of the second conducting type having a higher concentration than that of the surface of the second buried channel.

Abstract: In accordance with the invention, a full frame solid-state image sensor of altered accumulation potential comprises a substrate that includes a semiconductor of one conductivity type and has a surface at which is situated a photodetector that comprises a first storage area and a second storage area. The first and second storage areas each comprise a CCD channel of conductivity type opposite to the conductivity type of the semiconductor. A first barrier region separates the first storage area from the second storage area, and a second barrier region separates the second storage area from an adjacent photodetector; the second barrier region is shallower than the first barrier region. Adjacent to one side of the photodetector is a channel stop of the same conductivity type as the semiconductor.

Abstract: A CCD shift register includes a first gate electrode, a second gate electrode disposed adjacent to and longitudinally spaced from the first gate electrode, and a buried layer having a first dopant impurity concentration. The first gate electrode is disposed over the buried layer so as to define a first buried layer area. The second gate electrode is disposed over the buried layer so as to define a second buried layer area greater than the first buried layer area. In the buried layer, a trench region is formed so as to have a second dopant impurity concentration greater than the first dopant impurity concentration. The first gate electrode is disposed over the trench region so as to define a first trench area. The second gate electrode being disposed over the trench region so as to define a second trench area less than the first trench area.

Abstract: A method of making a signal charge transfer device, including the steps of: forming first conductivity-type channel regions (30) in each of second conductivity-type wells (20) formed in a first conductivity-type semiconductor substrate (10); forming a plurality of first electrodes (50a) uniformly spaced from one another, and then forming an insulation film (40) for insulating the first electrodes from one another; forming a primary potential barrier (70) in each of the channel regions by subjecting the channel regions to a primary-ion implantation process using the plurality of first electrodes as a mask; forming a secondary potential barrier (70a) in each of the channel regions at lower corners of each of the first electrodes by subjecting the channel regions to a sloped secondary-ion implantation process using the plurality of first electrodes as a mask; and forming second electrodes (80a), each being disposed between the adjacent ones of the first electrodes, and then forming an insulation film (60) to ins

Abstract: A solid-state imaging device that enables correction of the shading phenomenon effectively without overall sensitivity reduction. This device contains pixels arranged in an array to form an image area, photodetectors for detecting incident light to generate signal charges, and charge transfer devices for transferring the signal charges generated in the plurality of photodetectors. Each of the pixels contains one of the photodetectors and one of the charge transfer devices. The sensitivity of the photodetectors varies according to placement of the photodetectors in the image area, so that the sensitivity has a distribution that cancels nonuniformity of the incident light in the image area. The sensitivity of the photodetectors is preferably distributed concentrically with the center of the image area.

Abstract: A solid-state imaging device capable of removing undesired influences, includes a semiconductor substrate having one of conductive types, a well layer arranged on the substrate and having the other conductive type opposite to the substrate, photo-sensitive pixels recessed in a matrix having a predetermined number and having the conductive type opposite to the well layer to generate signal charges corresponding to an incident light amount, a transfer channel formed along one direction of the photosensitive pixels arranged by the conductive type as the same as that of the substrate to transfer the signal charges generated by the photosensitive pixels, an electrode provided to the transfer channel on a side opposite to the substrate to supply an electric field to the transfer channel, and a barrier well formed of the impurity semiconductor material of the conductive type opposite to the conductive type of the semiconductor substrate in the manner that an impurity density of the well layer becomes longer along th

Abstract: A charge transfer device is arranged such that a plurality of first kind charge transfer electrodes and a plurality of second kind charge transfer electrodes are alternately provided on an insulating film, and every other ones of the second kind charge transfer electrodes are grouped into a first and a second group. Potential barriers are provided at upstream portions of the charge transfer region beneath the respective second kind charge transfer electrodes. A first metal interconnect interconnects commonly the first kind charge transfer electrodes, a second metal interconnect interconnects commonly the first group second kind charge transfer electrodes, and a third metal interconnect interconnects commonly the second group second kind charge transfer electrodes.