Abstract: A solid state imaging device which reduces the occurrence of crosstalk between a plurality of picture elements arranged in a linear or matrix form. The solid state imaging device includes a plurality of photosensitive cells formed on a first principal surface of a semiconductor substrate, a transfer electrode formed in a gap area among the cells on the first principal surface to read out charges produced in the cells, a drive metal wiring formed on the transfer electrode within the gap area, a first insulating film covering the cells with a predetermined thickness, and a plurality of metal reflecting films formed on the first insulating film in such a manner that the whole surface of each of the metal reflecting films forms a reflecting surface substantially parallel to a surface of each of the cells on the side of the first principal surface whereby light passed through the photosensitive cells from a side opposite to the first principal surface is reflected back to each of the photosensitive cells.

Abstract: A solid state imaging device of the present invention includes: a semiconductor substrate of one conductive type; a well layer made of a semiconductor of the other conductive type formed on the semiconductor substrate; a photodetecting portion made of a semiconductor of one conductive type formed in an upper portion of the well layer; a high concentration semiconductor layer made of the other conductive type formed in an upper portion of the photodetecting portion; a first region of one conductive type formed in an upper portion of the semiconductor substrate, being in contact with the well layer and positioned at least below the photodetecting portion, having higher concentration than the semiconductor substrate; and a second region of the other conductive type formed in a lower portion of the well layer, being in contact with the semiconductor substrate and positioned on the first region.

Abstract: An image sensing device with electronic shutter having a semiconductor substrate of a first conductivity type and a buried channel layer of a second conductivity type disposed on the substrate. Virtual phase electrodes in the buried channel layer having the first conductivity type form virtual gate potential areas in the substrate below the virtual phase electrodes. An insulating layer is formed on the substrate. Conductive electrodes disposed on the insulating layer and located over portions of the substrate between the virtual phase electrodes form clocked gate potential areas in the substrate below the conductive electrodes. The virtual gate potential areas and the clocked gate potential areas form charge transfer columns along which charge can be transferred to an end of the charge transfer column.

Abstract: A method for driving a solid-state imaging device which includes the steps of (1) reading a signal from an i-th pixel in the pixel portion into a vertical charge transfer portion over k bit portions thereof starting from the i-th bit portion thereof; (2) transferring the read signal corresponding to k bits of the vertical charge transfer portion in the vertical direction during one horizontal blanking period; (3) reading a signal from an (i+1)-th pixel of the n pixels arranged in the pixel portion into the vertical charge transfer portion over k bit portions thereof starting from the (i+1)-th bit portion thereof after the completion of the transfer of signal portions corresponding to the (k-1) bits of the read signal corresponding to the k bits of the vertical charge transfer portion; (4) repeating the steps (1) through (3) for the pixels arranged in the pixel portion starting from the first pixel nearest to a horizontal charge transfer portion to a pixel farther therefrom; and (5) repeating the step (2) afte

Abstract: The backside surface potential well of a backside-illuminated CCD is confined to within about half a nanometer of the surface by using molecular beam epitaxy (MBE) to grow a delta-doped silicon layer on the back surface. Delta-doping in an MBE process is achieved by temporarily interrupting the evaporated silicon source during MBE growth without interrupting the evaporated p+ dopant source (e.g., boron). This produces an extremely sharp dopant profile in which the dopant is confined to only a few atomic layers, creating an electric field high enough to confine the backside surface potential well to within half a nanometer of the surface. Because the probability of UV-generated electrons being trapped by such a narrow potential well is low, the internal quantum efficiency of the CCD is nearly 100% throughout the UV wavelength range. Furthermore, the quantum efficiency is quite stable.

Abstract: A solid-state imaging device includes a semiconductor substrate in which an element part including a plurality of light responsive elements for generating charge carriers in response to incident light and a transfer part for transferring the charge carriers generated in each light responsive element are incorporated; a lens layer is disposed on the element part so that incident light is collected in the light responsive elements; and a light beam dispersion layer is disposed between the lens layer and the element part and includes two light transmissive layers having different refractive indices for dispersing light collected by the lens layer so that collected light entering respective light responsive elements is closer to a parallel beam than the incident light. By suppressing broadening of incident light in the semiconductor substrate at the light responsive elements, fewer charge carriers enter the CCD channel region and smear is reduced.

Abstract: A solid-state imaging device. An intermediate portion of a channel region have a tapered width from one shift register in which the signal charges to be read-out toward the other shift register. Therefore, the potential distribution of the channel region along the charge transfer direction has a continuous down-slope toward the one shift register. Thus, reading-out electric field can be improved.

Abstract: Solid-state image sensors, in general, comprise a photodetector for detecting radiation from the image and converting the radiation to charge carriers, and transfer means for carrying the charge carriers to an output circuit. One type of solid-state image sensor uses a CCD as both the photodetector and the transfer means. The solid-state image sensor generally includes a plurality of the CCD's arranged in spaced parallel relation to form an array. The image sensor of this disclosure utilizes only one antiblooming lateral overflow barrier. The excess signal charge of phase 1 flows into the preceding phase 2 and is saved. This eliminates the overflow barrier of phase 1 so that blooming protection is via the overflow barrier of the preceding phase 2. This results in an image sensor with blooming protection and increased charge capacity.

Abstract: An FIT or IT solid-state imaging device comprising a p-type Si substrate in which n-type regions forming storage diode portions, signal read-out portions, n-type CCD channels, and p.sup.

Abstract: A method and apparatus for reducing bloom in an output of a charge coupled device (CCD) image sensor is disclosed. The method includes the step of toggling at least two phases of said CCD after exposure of said CCD. The method and apparatus are particularly useful when a flash of light occurs during the exposure.

Abstract: The present invention is directed to a solid state imaging deice in which a light sensing region (3), a vertical register (4) and a channel stopper region (5) are formed within a well region (2) on an N-type silicon substrate (1). A positive electric charge storage region (6) is formed on the surface of the light sensing region (3) and a well region (7) is formed beneath the vertical register (4), respectively. Further, a transfer electrode (9) is selectively formed on the vertical register (4) through a gate insulating layer (8) and an Al light-intercepting layer (11) is formed on the transfer electrode (9) through an interlevel insulator (10). A surface protecting layer (12) is formed on the whole surface including the Al light-intercepting layer (11). In this solid state imaging device, a tapered portion (11a) is formed on the Al light-intercepting layer 11 corresponding to a peripheral edge portion of the light sensing region 3.

Abstract: The semiconductor image sensor element comprises a transistor gate potential well 102, a virtual potential well 100 adjacent the transistor gate potential well 102, a clear gate barrier 104 adjacent the virtual potential well 100, a clear drain 30 adjacent the clear gate barrier 104, and a charge sensor 28 for sensing charge levels in the transistor gate potential well 102. The charge levels are responsive to light incident on the device. Charge is stored in the virtual potential well 100 during charge integration. After charge integration, the charge is transferred into the transistor gate potential well 102 from the virtual potential well 100 for charge detection by the charge sensor 28. After charge detection, the charge is transferred from the transistor potential well 102 to the clear drain 30.

Abstract: Generally, and in one form of the invention, a method for multiplying charge in a CCD cell is disclosed comprising the step of causing impact ionization of charge carriers in the CCD cell.Other devices, systems and methods are also disclosed.

Abstract: Methods and apparatus for implementing charge skimming and variable integration time in focal plane arrays formed in a silicon substrate. The present invention provides for pulsing a field plate that lies over a diode disposed in the substrate in order to provide for charge skimming and variable integration time. The field plate is normally dc biased to suppress diode edge leakage. No additional structure is needed in the silicon substrate, and basic readout clocking is unaffected. Any interline transfer focal plane array can benefit from using the principles of the present invention.

Abstract: In a charge transfer image pick-up device including vertical registers and a horizontal register, impurity density of a well layer of the vertical registers is higher than that of a well layer of the horizontal register and a buried layer formed in the well layer of the vertical registers is composed of a first buried layer which is connected to a buried layer of the well layer of the horizontal register and a second buried layer formed on the first buried layer and having impurity density higher than that of the first buried layer, so that degradation of transfer efficiency of signal charge can be avoided and the manufacturing process can be simplified.

Abstract: A bulk charge modulated MOSFET for sensing light comprising a semiconductor substrate with a gate region of a first conductivity type formed in the substrate. The gate region forms a potential well for carriers of the first conductivity type. The well is formed at a substantial depth from the surface of the gate region. The carriers are formed responsive to incident light. The gate region collects the carriers generated at depths less than the well. A source region of a second conductivity type is formed in the semiconductor substrate laterally adjacent the gate region. The source region is operable to sense a change in threshold voltage of the MOSFET responsive to the collection of carriers by the gate region. A drain region of the second conductivity type is formed in the layer adjacent the gate region and spaced from the source. The drain region is connected to a voltage source.

Abstract: A solid imaging device that minimizes the degradation in charge transfer efficiency attributable to narrow channel effect by enlarging the apparent width of the horizontal output gate outlet. Miniaturization of the floating diffusion (FD) region is not hampered despite the apparent widening of the horizontal output gate outlet. The inventive imaging device utilizes a floating diffusion amplifier as the charge detector that detects a charge signal transferred from a horizontal CCD. In this device structure, ions are implanted into the substrate surface side of the region adjacent to the FD region in the horizontal output gate in such a manner that the channel potential of the adjacent region will become appropriately deeper than that of the forward-half region next to the adjacent region.

Abstract: A solid state image sensing device comprising first and second horizontal shift registers of two-phase drive system, a smear drain region disposed in an opposing relation to a first storage section of the second horizontal shift register to which the first phase drive pulse of the second horizontal shift register is applied and a channel stop region disposed in an opposing relation to a second storage section of the second horizontal shift register to which the second phase drive pulse is applied, wherein a smear component is drained to the smear drain region, and a hole component is drained to the channel stop region for thereby reducing a dark current of the second horizontal shift register to about that of the first horizontal shift register. Therefore, a dark current in the horizontal shift register of the solid state image sensing device can be reduced.

Abstract: The invention relates to photosensitive semiconductor devices and, more particularly, to linear arrays having several parallel rows of photoconductive points and operating in the integration and charge carry mode. In particular, the object of the invention is to reduce a smearing effect.The device of the invention comprises a photosensitive surface (SP) divided into photosensitive surface elements (SI1 to SMn) placed in rows (L1 to Ln) and in columns (C1 to CM). Each column forms a shift register that ends in a storage space (CS1 to CSM) of a readout register (RL) formed by a shift register of the charge transfer type: readout register (RL) being on same semiconductor substrate (10) as photosensitive surface (SP) the device includes.According to a feature of the invention, the device an intermediate zone (ZI) protected from light used to make a separation distance (DS) between photosensitive surface (SP) and readout register (RL).

Abstract: An exploiting or readout circuit for a linear or matrix type photodetector array is of the multiplex type, such as a charge-coupled device (CCD). The exploiting circuit has a number of input stages corresponding to the number of photodetectors or similar photosites, and the gains of the input stages are established as a function of the fields of view of their associated photodetectors. In one embodiment the input stages each comprise a storage device formed of a first and a second storage electrode separated by a dividing electrode, the storage electrodes having respective surface areas selected in a relation that varies as a function of solid angle field of view of the respective photodetector. In another embodiment the input stage can include an OpAmp with a negative feedback capacitor whose value is selected as a function of the viewing solid angle of the respective photodetector.

Abstract: A charge-coupled device comprises transfer gate electrodes separated from a substrate by a multi-layer insulating film, and gate electrodes of MIS transistors separated from the substrate by a single layer insulating film. The multilayer insulating film comprising at least a lower silicon oxide layer of 10 nm to 200 nm thickness and an upper silicon nitride layer of 10 nm to 100 nm thickness. Since each of the gate insulating films of the MIS transistors is the same layer as the lower silicon oxide layer, there occurs no degradation in the transistor characteristics due to the surface states or the trapping states present within the silicon nitride layer.

Abstract: A solid-state charge-coupled-device imager has an imaging region composed of a matrix of vertically and horizontally arrayed photosensitive areas for storing signal charges depending on the intensity of applied light, and a plurality of vertical shift resisters for vertically transferring the signal charges shifted from the photosensitive areas. The signal charges from the vertical shift registers are shifted to a horizontal shift register that transfers the signal charges in a horizontal direction. The horizontal shift register comprises a plurality of charge transfer electrodes horizontally spaced at predetermined intervals. The charge transfer electrodes are inclined to the horizontal direction. The charge transfer electrodes may be inclined linearly in their entirety to the horizontal direction or may be of a chevron shape.

Abstract: A solid-state CCD imaging device has a substrate, photosensitive pixel cells provided as pixel sections in the substrate, and a transfer section, provided in the substrate, for transferring signal charge carriers read out from the pixel cells in a predetermined transfer direction. The transfer section has a semiconductive charge transfer channel layer formed in the substrate and transfer electrodes insulatively provided above the substrate and arrayed in the above direction while predetermined gap sections are kept therebetween. Each of the transfer electrodes defines one charge transfer stage. A gap potential control electrode layer is insulatively disposed above the electrodes.

Abstract: A structure of a solid-state image sensing device applicable to an HDVS is disclosed in which at least one of the transmission paths for the drive pulses used for driving vertical registers and horizontal registers can achieve reduced propagation delays and signal distortions of the drive pulses. In the first preferred embodiment, a control gate for controlling the transfer of signal charges between the horizontal registers is constituted by a first polycrystalline silicon layer, a metal wiring layer is formed and is connected to the first polycrystalline silicon layer via contact regions and transfer electrodes provided for driving the horizontal registers are constituted by second and third semiconductor layers placed between the first polycrystalline silicon layer and the metal wiring layer without contacting the contact regions.

Abstract: An output circuit for sequentially receiving and converting charge collected in the photoelements of an image sensor and converting such charge into an output voltage. The output circuit includes a buried-channel LDD transistor having gate, source and drain electrodes. The source electrode provides a floating diffusion. When the transistor is turned off, a potential well is provided in the floating diffusion which collects charge. An output source-follower amplifier also employing buried-channel LDD transistors is connected to the floating diffusion and produces the output voltage.