Abstract: A driving substrate is provided. The driving substrate includes a substrate and a thin film transistor disposed on the substrate. The thin film transistor includes a first metal layer, a second metal layer, and a semiconductor disposed between the first metal layer and the second metal layer. The thin film transistor is divided into a first active block and a second active block, the first active block and the second active block are separated by a first gap in a first direction, and the first active block and the second active block are connected by a first bridge.

Abstract: To provide a mobile phone which can be used without hampering convenience in a condition where functions of the mobile phone are switched and can improve operability. The mobile phone includes an optical sensor, a display element, a pixel circuit portion where a plurality of pixels having a plurality of transistors are arranged in matrix, an optical sensor control circuit which is connected to an optical sensor driver circuit for driving the optical sensor and reads a signal from the optical sensor, a display portion control circuit which is connected to a display element driver circuit for driving the display element and outputs an image signal for displaying an image on a display portion, a gradient detection portion for outputting a signal in accordance with a gradient of the mobile phone, and an arithmetic circuit for performing display in the pixel circuit portion by switching image signals output to the display portion control circuit with a signal from the gradient detection portion.

Abstract: To provide a mobile phone which can be used without hampering convenience in a condition where functions of the mobile phone are switched and can improve operability. The mobile phone includes an optical sensor, a display element, a pixel circuit portion where a plurality of pixels having a plurality of transistors are arranged in matrix, an optical sensor control circuit which is connected to an optical sensor driver circuit for driving the optical sensor and reads a signal from the optical sensor, a display portion control circuit which is connected to a display element driver circuit for driving the display element and outputs an image signal for displaying an image on a display portion, a gradient detection portion for outputting a signal in accordance with a gradient of the mobile phone, and an arithmetic circuit for performing display in the pixel circuit portion by switching image signals output to the display portion control circuit with a signal from the gradient detection portion.

Abstract: The present disclosure provides an electronic device including a substrate, a common electrode, and a plurality of pixels. The common electrode is disposed on the substrate. The pixels are disposed on the substrate, and at least one of the pixels includes a thin film transistor, a first electrode, a second electrode, and an auxiliary electrode. The first electrode is electrically connected to the thin film transistor. The auxiliary electrode is electrically connected to the common electrode and electrically isolated from the first electrode, and the first electrode and the auxiliary electrode have a minimum distance less than a minimum distance between the first electrode and the common electrode.

Abstract: A solid state imaging device includes a pixel array unit in which color filters of a plurality of colors are arrayed with four pixels of vertical 2 pixels×horizontal 2 pixels as a same color unit that receives light of the same color, shared pixel transistors that are commonly used by a plurality of pixels are intensively arranged in one predetermined pixel in a unit of sharing, and a color of the color filter of a pixel where the shared pixel transistors are intensively arranged is a predetermined color among the plurality of colors. The present technology can be applied, for example, to a solid state imaging device such as a back-surface irradiation type CMOS image sensor.

Abstract: Disclosed is a display substrate including a base substrate, and gate lines, data lines, common electrode lines and common electrodes on the base substrate; the gate lines and the data lines intersect to define pixel areas; the common electrodes are located in the pixel areas; the gate lines and the common electrode lines are alternately arranged one by one; each common electrode lines includes target wire segments and non-target wire segments, the target wire segments are wire segments where the common electrode lines and the data lines intersect, and the non-target wire segments are wire segments on the common electrode line except the target wire segments; and for each common electrode line, a distance between any position point on the target wire segment and a target gate line is less than a distance between the non-target wire segment and the target gate line.

Abstract: Photovoltaic devices such as solar cells having one or more field-effect hole or electron inversion/accumulation layers as contact regions are configured such that the electric field required for charge inversion and/or accumulation is provided by the output voltage of the photovoltaic device or that of an integrated solar cell unit. In some embodiments, a power source may be connected between a gate electrode and a contact region on the opposite side of photovoltaic device. In other embodiments, the photovoltaic device or integrated unit is self-powering.

Abstract: An active matrix substrate includes a peripheral circuit including a TFT (30A) supported on a substrate (1). When viewed in a direction normal to the substrate (1), a first gate electrode (3) of the TFT (30A) includes a first edge portion and a second edge portion (3e1, 3e2) opposing each other. The first edge portion and the second edge portion extend across an oxide semiconductor layer (7) in a channel width direction. At least one of the first edge portion and the second edge portion includes, in a region overlapping with the oxide semiconductor layer (7), a first recess portion (40) recessed in a channel length direction and a first part (41) adjacent to the first recess portion in the channel width direction. When viewed in the direction normal to the substrate (1), a source electrode (8) or a drain electrode (9) of the TFT (30A) overlaps with at least a part of the first recess portion (40) and at least a part of the first part (41).

Abstract: An organic light emitting display unit is disclosed, which includes: a substrate; a light shielding layer and a first electrode disposed on the substrate, the light shielding layer and the first electrode are disposed on a same layer and made of a same material.

Abstract: A fin field effect transistor structure with particular gate appearance is provided in this disclosure, featuring a fin on a substrate and a gate on the substrate and traversing over the fin, wherein the fin is divided into an upper portion on a top surface of the fin and a lower portion on two sides of the fin, and the lower portion of the gate has protrusions laterally protruding in said first direction at positions abutting to the fin.

Abstract: The present technology relates to a solid-state imaging device and an electronic apparatus that perform a stable overflow from a photodiode and prevent Qs from decreasing and color mixing from occurring. A solid-state imaging device according to an aspect of the present technology includes, at a light receiving surface side of a semiconductor substrate, a charge retention part that generates and retains a charge in response to incident light, an OFD into which the charge saturated at the charge retention part is discharged, and a potential barrier that becomes a barrier of the charge that flows from the charge retention part to the OFD, the OFD including a low concentration OFD and a high concentration OFD having different impurity concentrations of the same type, and the high concentration OFD and the potential barrier being formed at a distance. For example, the present technology is applicable to a CMOS image sensor.

Abstract: A calibration method for a Hall sensor having a Hall sensitive layer with four electrical contacts and a first field plate, wherein, at a first temperature and at a first magnetic flux density, a resistance value of the Hall sensitive layer is determined for each of at least three different field plate voltages present at the field plate, a calibration curve is produced from the at least three resistance values, a deviation value of the calibration curve is determined from a reference calibration curve, and the field plate voltage that is present at the first field plate or an operating voltage that is present at the sensitive layer is readjusted by a correction value corresponding to the deviation value.

Abstract: A method of packaging CSP LED, comprising the following steps: placing LED chips on a carrier plate; coating light-blocking glue or fluorescent glue on the LED chips; at last cutting to form CSP LEDs with coating light-blocking glue or fluorescent glue outside the chip. Multiple LEDs with one light-emitting surface could be fabricated simultaneously. The process is simple and can prevent yellow light from appearing at the bonding surface of the light-blocking glue and the chip. The invention provides a CPS LED with the chip covered by packaging glue and the electrode of the chip protruding exposed and protruding. The invention provides CPS LED with three light-emitting surfaces and light-blocking glue arranged on two side surfaces and fluorescent glue arranged on other surfaces. This kind of LED could be used in various fields such as backlight and light bar, from side surfaces of which light could be emitted.

Abstract: An optical sensor device includes a semiconductor substrate including a conversion region to convert an electromagnetic signal into photo-generated charge carriers, a read-out node configured to read-out a first portion of the photo-generated charge carriers, a control electrode, which is formed in a trench extending into the semiconductor substrate, and a doping region in the semiconductor substrate, where the doping region is adjacent to the trench, where the doping region has a doping type different from the read out node, and where the doping region has a doping concentration so that the doping region remains depleted during operation.

Abstract: The disclosure provides a thin film transistor and a fabricating method thereof, and an array substrate. The thin film transistor includes a gate, a first active layer, a second active layer, a first source, a first drain, a second source and a second drain which are provided above a base substrate. The first active layer is located at a side of the gate facing the base substrate, and the second active layer is located at a side of the gate facing away from the first active layer. The first source and the first drain are located at a side of the first active layer facing away from the gate and are connected with the first active layer. The second source and the second drain are located at a side of the second active layer facing away from the gate and are connected with the second active layer.

Abstract: A microelectronic device includes a vertical Hall sensor for measuring magnetic fields in two dimensions. In one implementation, the disclosed microelectronic device involves a vertical Hall plate with a cross-shaped upper terminal and a lower terminal which includes a buried layer. The cross-shaped upper terminal has a length-to-width ratio of 5 to 12 where it contacts the vertical Hall plate. The length is measured from one end of one arm of the cross-shaped upper terminal to an opposite end of an opposite arm. The width is an average width of both arms. Hall sense taps are located outside of the cross-shaped upper terminal. Current returns connect to the buried layer.

Abstract: A double-sided electroluminescent display panel and a display device are provided. The double-sided electroluminescent display panel includes: a first absorption polarization structure disposed on a first light-emitting surface of a transparent electroluminescent (EL) structure, and a first reflective polarization structure disposed on a second light-emitting surface of the transparent EL structure; wherein transmission axes of the first absorption polarization structure and the first reflective polarization structure are perpendicular to each other; the first absorption polarization structure is configured to absorb light of a first wave component and transmit light of a second wave component; the first reflective polarization structure is configured to transmit the light of the first wave component and reflect the light of the second wave component.

Abstract: An optics system is provided that comprises a glass-based diffractive optical element (DOE) for coupling an optical signal passing out of an optical waveguide into a photodetector. The glass-based DOE improves optical link performance by performing one or more of shortening a response time of a photodetector, preventing an overloading condition of the photodetector from occurring and managing back reflection of light from the photodetector. The glass-based DOE is relatively inexpensively to manufacture and is reliable over a wide range of temperatures.

Abstract: The subject matter presented herein relates to a method for producing a backplane for electro-optic displays. The method may include providing a substrate coated with a first conductive material on a first side and a second conductive material on a second side, the second side being positioned opposite from the first side, patterning the first conductive material by cutting through the first conductive material, wherein the patterning of the first conductive material creates electrical isolated conductive segments to be controlled by a driver circuit and creating a plurality of vias on the substrate, the plurality of vias extending through the substrate and providing electrical conductivity between the first and second sides. The method may further include creating a plurality of conductive traces on the second side of the substrate by patterning the second conductive material by locally align the vias to the driver circuit.

Abstract: Techniques are provided that pumping of deep traps in GaN electronic devices using photons from an on-chip photon source. In various embodiments, a method for optical pumping of deep traps in GaN HEMTs is provided using an on-chip integrated photon source that is configured to generate photons during operation of the HEMT. In an aspect, the on-chip photon source is a SoH-LED. In various additional embodiments, an integration scheme is provided that integrates the photon source into the drain electrode of a HEMT, thereby converting the conventional HEMT with an ohmic drain to a transistor with hybrid photonic-ohmic drain (POD), a POD transistor or PODFET for short.

Abstract: A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect an additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity.

Abstract: A precursor cell for a transistor having a foundation structure, a mask structure, and a gallium nitride (GaN) PN structure is provided. The mask structure is provided over the foundation structure to expose a first area of a top surface of the foundation structure. The GaN PN structure resides over the first area and at least a portion of the mask structure and has a continuous crystalline structure with no internal regrowth interfaces. The GaN PN structure comprises a drift region over the first area, a control region laterally adjacent the drift region, and a PN junction formed between the drift region and the control region. Since the drift region and the control region form the PN junction having no internal regrowth interfaces, the GaN PN structure has a continuous crystalline structure with reduced regrowth related defects at the interface of the drift region and the control region.

Abstract: According to one embodiment, a substrate for display device includes an insulating substrate and a conductive film formed on at least one main surface of the insulating substrate. As to the substrate in an etching process in which a fluoric acid solution containing 10% or more hydrogen fluoride is used, a first etching rate of the conductive film is substantially the same as a second etching rate of the insulating substrate, or the first etching rate is greater than the second etching rate.

Abstract: This method concerns the protection against humidity of a device including a first and a second electronic components respectively having two opposite surfaces, the surfaces: being separated by a non-zero distance shorter than 10 micrometers; having an area greater than 100 mm2; being connected by an assembly of electrical interconnection elements spaced apart from one another by a space void of matter. This method includes applying a deposit of thin atomic layers onto the device to form a layer of mineral material covering at least the interconnection elements, the layer of mineral material having a permeability to water vapor smaller than or equal to 10?3 g/m2/day.

Abstract: The invention provides a method for manufacturing a TFT substrate and a TFT substrate manufactured thereof. In the above TFT substrate, the low temperature poly-silicon layer is produced by solid phase crystallization, the cost of production is under budget, and the TFT substrate is a double-grid structure that can guarantee the electrical characteristics of the thin film transistor and better the capacity of drive, and leakage phenomenon caused by groove light seldom happens.

Abstract: A semiconductor device includes: a nitride semiconductor multilayer; an insulating film disposed on the nitride semiconductor multilayer; and a gate electrode disposed on the insulating film, wherein the nitride semiconductor multilayer has a first oxidized region near an interface with a region of the insulating film below the gate electrode, the first oxidized region having an oxygen concentration higher than an oxygen concentration of a region near an interface with a region of the insulating film other than below the gate electrode.

Abstract: According to one embodiment, a sensor-equipped display device includes a display panel, a first driver, and a second driver. The display panel includes a first electrode, a second electrode and a detection electrode. The first driver delivers a common driving signal to the first electrode and the second electrode at a time of display driving, and selectively writes a write signal to one of the first electrode and the second electrode at a time of sensing driving. The second driver reads, from the detection electrode, a read signal indicative of a variation of a sensor signal occurring between the one of the first electrode and the second electrode, on one hand, and the detection electrode, on the other hand, at the time of the sensing driving.

Abstract: An imaging element includes: a plurality of pixels configured to receive light from outside and generate and output an imaging signal depending on an amount of the light received; a first transfer line connected to the pixel; a second transfer line; a column selection switch configured to select one pixel column and output the imaging signal to the second transfer line; a column source follower including a gate to which the imaging signal transferred by the first transfer line is input, a drain end being connected to a power supply voltage, and a source end being connected to the column selection switch; a constant current source configured to drive the column source follower and read out the imaging signal to the second transfer line; and a current generating unit configured to flow a predetermined current to the source end side of the column source follower.

Abstract: Manufacturing stability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes the steps of: forming an etching stopper film over a first interlayer insulating film; forming an inorganic insulating film over the etching stopper film; forming a resist film over the inorganic insulating film; selectively etching the etching stopper film and the inorganic insulating film by using the resist film as a mask to form a first opening in the etching stopper film and to form a second opening in the inorganic insulating film; removing the resist film by O2 plasma ashing; forming a second interlayer insulating film over the inorganic insulating film; and etching the second interlayer insulating film to form a wiring groove that is coupled to the second opening, and etching a portion located under the first opening of the first interlayer insulating film to form a via hole.

Abstract: A photocathode is formed on a monocrystalline silicon substrate having opposing illuminated (top) and output (bottom) surfaces. To prevent oxidation of the silicon, a thin (e.g., 1-5 nm) boron layer is disposed directly on the output surface using a process that minimizes oxidation and defects, and a low work-function material layer is then formed over the boron layer to enhance the emission of photoelectrons. The low work-function material includes an alkali metal (e.g., cesium) or an alkali metal oxide. An optional second boron layer is formed on the illuminated (top) surface, and an optional anti-reflective material layer is formed on the boron layer to enhance entry of photons into the silicon substrate. An optional external potential is generated between the opposing illuminated (top) and output (bottom) surfaces. The photocathode forms part of novel sensors and inspection systems.

Abstract: A semiconductor device is provided. The semiconductor device can be manufactured with a reduced cost. The semiconductor device (1D) includes, a substrate (100D), which includes a main surface (101D) and a recess (108D) depressed from the main surface (101D), and includes a semiconductor material; a wiring layer (200D) in which at least a portion thereof is formed on the substrate (100D); one or more first elements (370D) accommodated in the recess (108D); a sealing resin (400D) covering at least a portion of the one or more first elements (370D) and filled in the recess (108D); and a plurality of columnar conductive portions (230D) penetrating through the sealing resin (400D) in the depth direction of the recess (108D), and respectively connected with the portion of the wiring layer (200D) that is formed at the recess (108D).

Abstract: An image sensor with an array of pixels is provided. In order to achieve high image quality, it may be desirable to improve well capacity of individual pixels within the array. When forming each pixel, multiple n-type compartments having p-type isolation regions interposed between compartments may be formed. These compartments may have higher dopant concentrations due to lateral depletion that may occur within multiple PN-NP back to back junctions to assist full depletion at pinning-voltage. Compartments may allow distributing a moderately higher electric-field over a larger portion of the photodiode while lowering peak electric-fields that contribute to dark-current. Compartments will thereby improve the well capacity of the photodiode while preventing additional noise that may degrade the quality of the image signal. The quantity, doping, and depth of these compartments may be selected to maximize well capacity while minimizing effects on operating voltage, manufacturing cost, and power consumption.

Abstract: Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side.

Abstract: An example imaging sensor system includes a backside-illuminated CMOS imaging array formed in a first semiconductor layer of a first wafer. The CMOS imaging array includes an N number of pixels, where each pixel includes a photodiode region. The first wafer is bonded to a second wafer at a bonding interface between a first metal stack of the first wafer and a second metal stack of the second wafer. A storage device is disposed in a second semiconductor layer of the second wafer. The storage device includes at least N number of storage cells, where each of the N number of storage cells are configured to store a signal representative of image charge accumulated by a respective photodiode region. Each storage cell includes a circuit element that is sensitive to light-induced leakage.

Abstract: Devices incorporating a single to a few-layer MoS2 channels in combination with optimized substrate, dielectric, contact and electrode materials and configurations thereof, exhibit light emission, photoelectric effect, and superconductivity, respectively.

Abstract: Resistance variable memory cell structures and methods are described herein. One or more resistance variable memory cell structures include a first electrode common to a first and a second resistance variable memory cell, a first vertically oriented resistance variable material having an arcuate top surface in contact with a second electrode and a non-arcuate bottom surface in contact with the first electrode; and a second vertically oriented resistance variable material having an arcuate top surface in contact with a third electrode and a non-arcuate bottom surface in contact with the first electrode.

Abstract: A thin-film Light Emitting Diode (LED) and methods of manufacturing the same are disclosed. Specifically, the thin-film LED is provided with an epitaxial layer having a proton implantation that controls the size of the active volume. Controlling the size of the active volume enables the thin-film LED to enjoy decreased rise and fall times, thereby achieving a thin-film LED that is useable for transmission in high transmission rate communication systems.

Abstract: A stacked semiconductor device includes a first substrate. A multilayer interconnect is disposed over the first substrate. Metal sections are disposed over the multilayer interconnect. First bonding features are over the metal sections. A second substrate has a front surface. A cavity extends from the front surface into a depth D in the second substrate. The cavity has an interior surface. A stop layer is disposed over the interior surface of the cavity. A movable structure is disposed over the front surface of the second substrate and suspending over the cavity. The movable structure includes a dielectric membrane, metal units over the dielectric membrane and a cap dielectric layer over the metal units. Second bonding features are over the cap dielectric layer and bonded to the first bonding features. The second bonding features extend through the cap dielectric layer and electrically coupled to the metal units.

Abstract: Multiple control modules (14, 16, 18) provide various power control functions including occupancy sensing, ambient light level sensing, manual touch switch (push button) preset stations, light dimming and power control relay switching. The control modules (14, 16, 18) are interconnected in a conventional four-wire local area network for executing different power control functions in response to remote wireless commands as well as preset manual switch commands at the wall box level. The local area network (12) supplies DC operating power and communicates programming command and control module status information signals to all network control modules (14, 16, 18). One or more control modules (14, 16, 18) include an infrared signal sensor, a laser signal sensor, a signal decoder, a data microcontroller, a parameter lookup table and multiple light emitting diodes (LEDs).

Abstract: A semiconductor light emitting device including: a substrate made of GaAs; and a semiconductor layer formed on the substrate, in which part of the substrate on a side opposite to the semiconductor layer is removed by etching so that the semiconductor light emitting device has a thickness of not more than 60 ?m.

Abstract: A thin film diode (100A) includes a semiconductor layer (130) having first, second, and third semiconductor regions, a first insulating layer (122) formed on the semiconductor layer (130), and a second insulating layer (123) formed on the first insulating layer (122). The first semiconductor region (134A) contains an impurity of a first-conductivity type at a first concentration; the second semiconductor region (135A) contains an impurity of a second-conductivity type different from the first conductivity type at a second concentration; and the third semiconductor region (133A) contains the first-conductivity type impurity at a third concentration lower than the first concentration, or contains the second-conductivity type impurity at a third concentration lower than the second concentration. The first semiconductor region (134A) conforms to an aperture pattern in the second insulating layer (123), or the second semiconductor region (135A) conforms to an aperture pattern in the second insulating layer (123).

Abstract: This disclosure provides systems, methods and apparatus for combining devices deposited on a first substrate, with integrated circuits formed on a second substrate such as a semiconducting substrate or a glass substrate. The first substrate may be a glass substrate. The first substrate may include conductive vias. A power combiner circuit may be deposited on a first side of the first substrate. The power combiner circuit may include passive devices deposited on at least the first side of the first substrate. The integrated circuit may include a power amplifier circuit disposed on and configured for electrical connection with the power combiner circuit, to form a power amplification system. The conductive vias may include thermal vias configured for conducting heat from the power amplification system and/or interconnect vias configured for electrical connection between the power amplification system and a conductor on a second side of the first substrate.

Abstract: A micro-electromechanical system (MEMS) device includes a housing and a base. The base includes a port opening extending therethrough and the port opening communicates with the external environment. The MEMS die is disposed on the base and over the opening. The MEMS die includes a diaphragm and a back plate and the MEMS die, the base, and the housing form a back volume. At least one vent extends through the MEMS die and not through the diaphragm. The at least one vent communicates with the back volume and the port opening and is configured to allow venting between the back volume and the external environment.

Abstract: A process of forming a CMOS integrated circuit by forming a first stressor layer over two MOS transistors of opposite polarity, removing a portion of the first stressor layer from the first transistor, and forming a second stressor layer over the two transistors. A source/drain anneal is performed, crystallizing amorphous regions of silicon in the gates of the two transistors, and subsequently removing the stressor layers. A process of forming a CMOS integrated circuit by forming two transistors of opposite polarity, forming a two stressor layers over the transistors, annealing the integrated circuit, removing the stressor layers, and siliciding the transistors. A process of forming a CMOS integrated circuit with an NMOS transistor and a PMOS transistor using a stress memorization technique, by removing the stressor layers with wet etch processes.

Abstract: A light emitting diode is disclosed. The disclosed light emitting diode includes a light emitting structure including a first-conductivity-type semiconductor layer, an active layer, and a second-conductivity-type semiconductor layer. The first-conductivity-type semiconductor layer, active layer, and second-conductivity-type semiconductor layer are disposed to be adjacent to one another in a same direction. The active layer includes well and barrier layers alternately stacked at least one time. The well layer has a narrower energy bandgap than the barrier layer. The light emitting diode also includes a mask layer disposed in the first-conductivity-type semiconductor layer, a first electrode disposed on the first-conductivity-type semiconductor layer, and a second electrode disposed on the second-conductivity-type semiconductor layer. The first-conductivity-type semiconductor layer is formed with at least one recess portion.

Abstract: A backside illumination image sensor structure comprises an image sensor formed adjacent to a first side of a semiconductor substrate, wherein a first dielectric layer formed over the first side of the semiconductor substrate and an interconnect layer formed over the first dielectric layer. The image sensor structure further comprises a backside illumination film formed over a second side of the semiconductor substrate and a first silicon halogen compound layer formed between the second side of the semiconductor substrate and the backside illumination film.

Abstract: A depletion-mode phototransitor is disclosed. The phototransistor having a substrate, a gate, a source, a drain and a channel. The source, drain and channel are doped to be the same type of semiconductor. The substrate can be made of silicon and/or germanium. The gate can be made of either aluminum or polysilicon.

Abstract: A global shutter pixel cell includes a serially connected anti-blooming (AB) transistor, storage gate (SG) transistor and transfer (TX) transistor. The serially connected transistors are coupled between a voltage supply and a floating diffusion (FD) region. A terminal of a photodiode (PD) is connected between respective terminals of the AB and the SG transistors; and a terminal of a storage node (SN) diode is connected between respective terminals of the SG and the TX transistors. A portion of the PD region is extended under the SN region, so that the PD region shields the SN region from stray photons. Furthermore, a metallic layer, disposed above the SN region, is extended downwardly toward the SN region, so that the metallic layer shields the SN region from stray photons. Moreover, a top surface of the metallic layer is coated with an anti-reflective layer.

Abstract: A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source and drain regions. A gate stack is above the substrate over the channel region and between the pair of source and drain regions. The gate stack includes a high dielectric constant blocking region.

Abstract: An SRAM cell of a semiconductor device includes a load transistor, a driver transistor and an access transistor. First source/drains of the load, driver and access transistors are connected to a node. A power line, a ground line and a bit line are electrically connected to second source/drains of the load transistor, the driver transistor and the access transistor. The power line, the ground line and the bit line are disposed at substantially the same level to extend in a first direction. A word line is electrically connected to a gate of the access transistor to extend in a second direction perpendicular to the first direction. The word line is disposed at a different level from the level of the power line, the ground line and the bit line.